Documente Academic
Documente Profesional
Documente Cultură
Features
Applications
n
n
n
n
Typical Application
MODULE +
2.5A AVERAGE
DISCHARGE
The LT8584 is a monolithic flyback DC/DC converter designed to actively balance high voltage stacks of batteries.
The high efficiency of a switching regulator significantly
increases the achievable balancing current while reducing
heat generation. Active balancing also allows for capacity recovery in stacks of mismatched batteries, a feat unattainable
with passive balance systems. In a typical system, greater
than 99% of the total battery capacity can be recovered.
BAT 12
MODULE +
MODULE
V+
LT8584
ENABLE BALANCING
2.5A AVERAGE
DISCHARGE
BAT 2
MEASURABLE CELL
PARAMETERS
VCELL
IDISCHARGE
VREF
TEMPERATURE
EXTRACTABLE CELL
PARAMETERS
RCABLE + RCONNECTOR
SWITCHING FAULTS
UNDERVOLTAGE
SERIAL FAULTS
COULOMB COUNTING
MODULE +
MODULE
2.5A AVERAGE
DISCHARGE
BAT 1
C12
S12
LT8584
LTC6804
BATTERY STACK
MONITOR
C2
S2
MODULE +
MODULE
LT8584
ENABLE BALANCING
C1
S1
V/C0
LT8584 TA01a
MODULE
8584f
LT8584
Absolute Maximum Ratings
Pin Configuration
(Note 1)
TOP VIEW
GND
16 SW
GND
15 SW
GND
14 SW
GND
MODE
RTMR
11 VSNS
DIN
10 VCELL
OUT
17
GND
13 SW
12 DCHRG
VIN
FE PACKAGE
16-LEAD PLASTIC TSSOP
TJMAX = 150C, JA = 38C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
Order Information
LEAD FREE FINISH
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT8584EFE#PBF
LT8584EFE#TRPBF
8584FE
40C to 125C
LT8584IFE#PBF
LT8584IFE#TRPBF
8584FE
40C to 125C
LT8584HFE#PBF
LT8584HFE#TRPBF
8584FE
40C to 150C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
8584f
LT8584
Electrical
Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25C. VIN = 4.2V, DIN = GND unless otherwise noted. (Note 4)
PARAMETER
CONDITIONS
Switching
Nonswitching
Switching
Nonswitching
In Shutdown, DIN = OUT
In Shutdown, DIN = OUT
MIN
l
l
2.5
2.4
l
l
2.1
VSW = 4.2V
VSW = 4.2V
MAX
5.3
5.3
45
2.5
1
VIN UVLO
Switch VCESAT
TYP
6.3
3
90
1
UNITS
V
mA
mA
nA
A
2.35
6.8
450
ns
200
mV
5
l
70
4
nA
A
30
50
70
0.5
0.85
1.2
42
45
50
48
V
V
80
200
360
ns
VSW VVIN
40
95
150
mV
200mV Overdrive
100
180
ns
Note 5
ISW = 2mA
ISW = 6A
Note 6
230
MODE Threshold
ns
1.7
1.2
V
1.4
100
V
mV
VDIN = 0V
VDIN = 1V
6
18
0.7
3
14
1
6
A
A
DCHRG Threshold
0.5
0.8
1.1
DCHRG Hysteresis
100
mV
220
300
220
300
RRTMR = 50k
1.22
RRTMR = 50k
55
Gain Error 8%
Gain Error 3%
30
70
mV
15
45
mV
1.1
18.7
l
l
l
l
l
l
13
14
18
22
31
35
28
19
0.2
1.1
mV
19.3
V/V
13
14
18
22
31
35
28
mV
mV
mV
mV
mV
mV
mV
0.75
%/V
8584f
LT8584
Electrical
Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25C. VIN = 4.2V, DIN = GND unless otherwise noted. (Note 4)
PARAMETER
CONDITIONS
MIN
TYP
VTEMP
1.53
1.6
0.2
MAX
UNITS
mV/K
0.658
V
V
0.4
%/mA
Timing
Characteristics
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25C. MODE = 0V. Refer to Timing Diagram for parameter definition. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
tW
RRTMR = 10k
RRTMR = 50k
RRTMR = 100k
RRTMR = 200k
MIN
TYP
MAX
UNITS
l
l
l
l
1.76
8
15.6
29.3
1.86
8.4
16.4
31.5
1.96
8.8
17.2
33.7
ms
ms
ms
ms
1.76
33.7
ms
10
5
tRST
t1
t2
50
t3
50
t4
50
t5
t6
SR
RRTMR = 10k
RRTMR = 10k
900
2.1
l
s
1.8
ns
s
V/ms
Note 5: This is a measure of time duration from the onset of the switch
turning on to the time the short-circuit protection circuit is disabled. If the
current comparator trips during this duration, the switch error latch is set.
This indicates that the connection to the transformer primary is most likely
shorted.
Note 6: This is a measure of time duration for the switch clamp to operate
continuously without setting the switch error latch. If the switch clamp
remains engaged longer than the switch clamp blanking time, the switch
error latch is set and switching is disabled.
Note 7: The voltage proportional to temperature (VTEMP) is measured
on the OUT pin while in analog multiplexer MODE 3 or 4. VTEMP must be
subtracted from the VCELL voltage that is measured while in analog mux
MODE 1. Both measurements should be taken within 100ms of each other
to reduce errors in absolute temperature calculation.
8584f
LT8584
Typical Performance Characteristics
TA = 25C, VIN = VCELL = VSNS = 4.2V, unless otherwise noted.
VIN Pin Current
Switching Disabled
5
2.4
2.3
2.2
2.1
2.0
60
20
20
60
100
TEMPERATURE (C)
3
0.4
2
0.2
140
0.6
6
PIN VOLTAGE (V)
8584 G01
CURRENT (A)
6.2
5.8
5.4
2.1
20
20
60
100
TEMPERATURE (C)
5.0
60
140
20
60
100
20
TEMPERATURE (C)
8584 G04
48
53
44
42
40
60
60
100
20
TEMPERATURE (C)
140
8584 G07
0.4
30
0.3
25
20
20
60
100
TEMPERATURE (C)
140
20
110
51
49
90
70
47
20
35
8584 G06
VOLTAGE (mV)
55
VOLTAGE (V)
50
46
0.5
0.2
60
140
40
ISW = 5.8A
8584 G05
TIME (s)
Switch Characteristics
0.6
6.6
2.2
140
BETA (A/A)
VOLTAGE (V)
2.5
2.3
60
100
20
TEMPERATURE (C)
8584 G03
7.0
2.4
20
8584 G02
2.0
60
0
60
VCE,SAT (V)
2.6
DIN = OUT
DCHRG = 0V
MODE = VIN
4
SHDN CURRENT (mA)
CURRENT (mA)
2.5
0.8
CURRENT (A)
2.6
45
60
20
60
100
20
TEMPERATURE (C)
140
8584 G08
50
60
20
20
60
100
TEMPERATURE (C)
140
8584 G09
8584f
LT8584
Typical Performance Characteristics
180
1.6
150
90
60
10
4
2
0
DIN VOLTAGE (V)
15
60
20
20
60
100
TEMPERATURE (C)
8584 G10
VOLTAGE (V)
0.2
RISING
350
0.6
FALLING
0.4
0
60
140
20
60
100
20
TEMPERATURE (C)
RESISTANCE ()
VOLTAGE (V)
100
1.4
60
100
20
TEMPERATURE (C)
140
8584 G16
1.0
VCELL = 2.5V
VCELL = 3V
VCELL = 3.6V
VCELL = 4.2V
80
60
20
60
20
60
100
TEMPERATURE (C)
140
VTEMP
0.9
40
20
20
8584 G15
2.0
1.2
60
200
60
140
1.6
SINK
8584 G14
8584 G13
1.8
SOURCE
300
250
0.2
60
100
20
TEMPERATURE (C)
140
400
0.8
0.4
60
100
20
TEMPERATURE (C)
1.0
0.6
20
8584 G12
0.8
20
FALLING
8584 G11
0
60
1.2
0.8
60
140
CURRENT (A)
0
10
RISING
1.0
VDIN = 1V
30
1.0
1.4
VOLTAGE (V)
CURRENT (A)
CURRENT (A)
VDIN = 0V
120
0.8
0.7
0.6
0.5
20
60
100
20
TEMPERATURE (C)
140
8584 G17
0.4
60
20
60
100
20
TEMPERATURE (C)
140
8584 G18
8584f
LT8584
Typical Performance Characteristics
TA = 25C, VIN = VCELL = VSNS = 4.2V, unless otherwise noted.
1200
VSNS Amplifier
Input Referred Offset
500
19.25
250
600
OFFSET (V)
800
GAIN (V/V)
1000
19.00
400
18.75
250
200
0
10
30
40
50
20
VCELL VSNS (mV)
60
18.50
60
70
8584 G19
20
60
100
TEMPERATURE (C)
140
500
60
10
10
60
20
20
60
100
TEMPERATURE (C)
0.25
0.20
1
ERROR (%)
REGULATION (%/V)
SW, ERR
FAULT
MODE4
MODE3
MODE2
MODE1
140
0.30
100k
50k
20
60
100
TEMPERATURE (C)
8584 G21
Handshake Voltage
Line Regulation
20
8584 G20
20
0.15
0.10
0.05
0
60
140
20
8584 G22
60
100
20
TEMPERATURE (C)
10k
3
60
140
20
60
100
20
TEMPERATURE (C)
8584 G24
8584 G23
2.0
140
10
300
9
250
1.6
1.4
SINK
6
5
SOURCE
1.2
TIME (s)
8
CURRENT (mA)
1.8
200
150
3
1.0
60
20
60
100
20
TEMPERATURE (C)
140
8584 G25
2
60
20
60
100
20
TEMPERATURE (C)
140
8584 G26
100
60
20
20
60
100
TEMPERATURE (C)
140
8584 G27
8584f
LT8584
Typical Performance Characteristics
T1 = NA5920-AL
D1 = 2 SERIES ES1J
2.4
ISW
2A/DIV
2s/DIV
T1 = NA5920-AL
D1 = 2 SERIES ES1J
VCELL = 4.2V
VSTACK = 400V
8584 G28
2.0
1.8
1.6
1.4
50
80
75
VCELL = 2.5V
VCELL = 3V
VCELL = 3.6V
VCELL = 4.2V
1.2
1.0
T1 = NA5920-AL
D1 = 2 SERIES ES1J
85
2.2
EFFICIENCY (%)
VSW
10V/DIV
Conversion Efficiency
90
70
400
VCELL = 2.5V
VCELL = 3V
VCELL = 3.6V
VCELL = 4.2V
50
ISW
2A/DIV
2s/DIV
T1 = NA5743-AL
D1 = ES1D
VCELL = 3.6V
VMODULE = 40V
RCD SNUBBER = 4.99k, 22nF
8584 G31
T1 = NA5743-AL
D1 = ES1D
2.8
2.4
30
30
8584 G34
Conversion Efficiency
90
T1 = NA6252-AL
D1 = STPS3H100U
2.8
2.6
2.4
10
15
20
25
30
AUXILLARY VOLTAGE (V)
80
75
VCELL = 2.5V
VCELL = 3V
VCELL = 3.6V
VCELL = 4.2V
2.2
2.0
T1 = NA6252-AL
D1 = STPS3H100U
85
EFFICIENCY (%)
ISW
2A/DIV
40
50
60
70
80
MODULE VOLTAGE (VMODULE+ VMODULE)
8584 G33
VSW
10V/DIV
70
40
50
60
70
80
MODULE VOLTAGE (VMODULE+ VMODULE)
VCELL = 2.5V
VCELL = 3V
VCELL = 3.6V
VCELL = 4.2V
8584 G32
3.0
T1 = NA6252-AL
D1 = STPS3H100U
VCELL = 4.2V
VAUX = 13.8V
RCD SNUBBER = 4.99k, 22nF
80
75
VCELL = 2.5V
VCELL = 3V
VCELL = 3.6V
VCELL = 4.2V
2.2
2.0
T1 = NA5743-AL
D1 = ES1D
85
2.6
Switching Waveform
2s/DIV
Conversion Efficiency
90
EFFICIENCY (%)
VSW
10V/DIV
400
8584 G30
8584 G29
Switching Waveform
35
8584 G35
70
VCELL = 2.5V
VCELL = 3V
VCELL = 3.6V
VCELL = 4.2V
6
12
18
24
30
AUXILLARY VOLTAGE (V)
36
8584 G36
8584f
LT8584
Pin Functions
GND (Pin1, Pin 2, Pin 3, Pin 4, Pin 17): Must be soldered
directly to local ground plane.
MODE (Pin 5): Serial Enable Pin. Connect this pin to
ground to enable serial interface for analog mux control.
Connect this pin to VIN to disable the analog mux. When
the analog mux is disabled, the OUT pin defaults to VTEMP
measurement. Do not float this pin.
RTMR (Pin 6): Serial Interface Timer Pin. Place a resistor
from this pin to ground to set the serial count duration
window, tW. See the Applications Information section for
proper resistor selection.
DIN (Pin 7): Data Input Pin. Take this pin 1V below the OUT
pin to initiate switching if MODE pin is connected to VIN,
or to select the desired analog mux state if MODE pin is
tied to ground. This pin is designed to be directly driven
from the LT680x familys S pins.
OUT (Pin 8): Analog Output Pin. Connect this pin to an
accurate voltage monitor to measure a voltage proportional to the internal IC temperature, VTEMP, if MODE pin
is connected to VIN, or measure the output of the internal
analog mux if MODE pin is connected to ground. In analog
mux mode, the OUT pin allows voltage monitoring of the
VCELL pin, the VSNS pin, or VTEMP. This pin is designed
to be directly connected to the LTC680x familys C pins.
Must connect a compensation capacitor to this pin. See
the Applications Information section for proper capacitor
sizing and placement.
VIN (Pin 9): Supply Pin. Connect this pin directly to the
positive battery cell terminal. Must be bypassed with high
grade (X5R or better) ceramic capacitor placed close to
the transformers primary winding connection.
VCELL (Pin 10): Cell Voltage Monitor Pin. This pin provides
a Kelvin connection to the battery cell for accurate voltage
monitoring. Connect this pin directly to the positive battery
cell terminal. The recommended cell voltage is 2.5V to 5.3V.
VSNS (Pin 11): Voltage Sense Pin. Connect this pin to the
current sense resistor connected to the primary side of
the transformer. Use this pin to measure average current
discharged from battery cell (see the Block Diagram). MODE
pin must be connected to ground and the internal analog
mux must have the VSNS pin selected to use this feature.
Input current is determined as (VVCELL VVSNS)/RSNS.
DCHRG (Pin 12): Discharge Pin. The Discharge pin can
be configured as an input or output pin. Connect MODE
pin to ground to configure DCHRG as an output pin where
DCHRG is driven to VIN during switching and driven
to ground when switching is deactivated. The output
configuration can be used to drive multiple LT8584s or
other switching regulators in parallel, to boost discharge
capability. Connect MODE pin high to configure DCHRG as
an input. When configured as an input pin, drive DCHRG
pin to VIN to enable switching. Note in this mode that serial communication is disabled and the DIN pin must be
grounded to initiate switching.
SW (Pin 13, Pin 14, Pin 15, Pin 16): Switch Pin. This
is the collector of the internal 6A NPN power switch.
Minimize the metal trace area connected to this pin to
minimize EMI. Connect the bottom side of the transformer
primary to this pin.
8584f
10
CFBO
RRTMR
TO PARALLEL
DISCHARGERS
(OPTIONAL)
MODULE
VMODULE
MODULE+
VSW
RTMR
MODE
1.22V
40mV
6.3m
SW
DCHRG
Q1
T1
A3
VIN
VIN
SIMPLE
MODE
SERIAL
MODE
A1
TIMER
A2
LATCH
POWER
DURING
TIMER
VIN
DIE
TEMPERATURE
VSNS AMP
VVIN 1.4V
VTEMP
VVIN 1.2V
VVIN 0.8V
VVIN 0.6V
VVIN 0.4V
ANALOG MUX
1V
CHIP
ENABLE
VVIN 0.2V
95mV
TO S PIN (LTC680x)
DIN
VCELL
DCM
COMPARATOR
SWITCH
PROTECTION
CIRCUITRY
11-BIT
COUNTER
CONTROL LOGIC
Q
R SWITCH S
LATCH
CURRENT
COMPARATOR
CTRAN
D1
CHIP
POWER
M1
TO ANALOG
MUX
CVIN
1.55V
M2
VIN
14k
19x
VSNS AMP
8584 BD
GND
OUT
VCELL
VSNS
RSNS
CELL
BEING
BALANCED
CELL BELOW
COUT
TO C PIN
LTC680x
CVCELL
CELL ABOVE
LT8584
Block Diagram
8584f
LT8584
Timing Diagram
DIN
SR
tRST
t2
t3
t4
t6
RTMR
t1
tW
DCHRG
t5
8584 TD
Operation
Most systems use multiple battery cells connected in series
to increase the available capacity and voltage. Individual
battery cells must be properly charged where their voltage and temperature are constantly monitored and never
allowed to exceed safe levels; otherwise, the batterys
capacity and life span would be greatly reduced. Linear
Technology offers the LTC680x family series of multicell
battery stack monitors (BSM) to accomplish this task.
The LT680x monitors each individual cell in the stack and
communicates this information through a proprietary
serial bus to a central processing unit. If a cell begins
to approach the allowable voltage limit, commands are
issued to the LT680x to turn on that cells passive shunt,
bypassing the charging current to that cell and allowing
the current to continue to the rest of the cells. The passive shunt current and/or power capability constrains the
maximum charging current for the battery stack. Using a
passive shunt is also inefficient, and the shunted current
produces considerable heat at higher charging currents.
The LT8584 solves the two limitations of passive shunting
balancers by actively shunting the charging current and
returning the energy back to the battery stack. Instead of
the energy being lost as heat, it is reused to charge the
rest of the batteries in the stack. The architecture of the
LT8584 also solves the problem of reduced run time when
one or more of the cells in the stack reaches the lower
safety voltage threshold before the entire stack capacity
11
LT8584
Operation
mode, the LT8584 discharger is toggled on/off using a
logic input pin. In serial mode, the LT8584 allows the user
to measure the discharge current and the die temperature,
in addition to the cell voltage.
ILPRI
VVIN VCESAT
LPRI
IPK
ILSEC
VMODULE VDIODE
LSEC
IPK
N
t
VPRI
1. Primary-Side Charging
VVIN VCESAT
When the switch latch is set, the internal NPN switch turns
on, forcing (VVIN VCESAT) across the primary winding.
Consequently, current in the primary coil rises linearly at
a rate of (VVIN VCESAT)/LPRI. The input voltage is mirrored on the secondary winding as N (VVIN VCESAT)
which reverse-biases the secondary-side series diode and
prevents current flow in the secondary winding. Thus,
energy is stored in the core of the transformer.
t
(VMODULE VDIODE)
N
VSEC
VMODULE + VDIODE
t
VSW
VVIN +
VMODULE VDIODE
N
VVIN
VCESAT
VCESAT
t
12
N(VVIN VCESAT)
(1)
(2)
(3)
PRIMARY-SIDE SECONDARY-SIDE DISCONTINUOUS
CHARGING ENERGY TRANSFER
MODE
AND OUTPUT
DETECTION
DETECTION
8584 F01
8584f
LT8584
Operation
Switch Protection
Short-Circuit Detector
The short-circuit detector detects when the power NPN
switch turns off prematurely due to a short in the primaryside winding. If the current comparator trips before the
850ns short detection timeout, the switch error latch will
trip. The OUT pin is driven to VVIN 1.2V, VSW,ERR, during
a switch error. The part must be reset to clear the switch
error fault.
High-Impedance Detector
The high-impedance detector monitors how long the power
NPN switch has been on. If the switch remains on longer
than 50s, the switch maximum on-time, the switch error
latch is set and the OUT pin is driven to VVIN 1.2V, VSW,ERR.
The part must be reset to clear the switch error fault.
STACK+
STACK+
LOCAL
IC GND
LOCAL
IC GND
LT8584
MODE
VIN
OFF ON
DIN
GND
LT8584
MODE
OFF ON
STACK
VSNS VCELL
SW
DCHRG
OUT
LOCAL
IC GND
STACK
VSNS VCELL
VIN
LOCAL
IC GND
SW
DCHRG
DIN
OUT
RTMR
GND
RTMR
8584 F02
ACTIVE LOW
ACTIVE HIGH
13
LT8584
Operation
Simple Mode Operation
DCHRG
ENABLE
BALANCING
DIN
8584 F03
ENABLED WITH
CORRECT STATE
SERIAL DECODE
VVIN
SHUTDOWN
t
RTMR
DECODE WINDOW
1.22V
16.3ms
RRTMR = 100k
t
OUT
VVIN
VVIN 0.2V
VVIN 0.4V
VVIN 0.6V
VVIN 0.8V
VVIN 1.4V
VOLTAGE MODE
HANDSHAKE
ANALOG MUX
ACTIVATED TO DESIRED INPUT
VCELL SELECTED
8584 F04
14
8584f
LT8584
Operation
OSCILLATOR
EN
POR
11-BIT
Y0
RIPPLE
RST COUNTER Y11
24
DECODER
1-SHOT
POR
VDD
DIN
POR
2-BIT
RIPPLE Y0
RST COUNTER Y1
POR
VDD
MODE 1
MODE 2
MODE 3
D
b
MODE 4
8584 F05
Serial Architecture
DISCHARGER
STATE
MUX
OUTPUT
HANDSHAKE
VOLTAGE
(VVIN VOUT)
Part Disabled
Disabled
VCELL
N/A
PULSE
COUNT
0
Fault
Disabled
VFAULT
1.4
Enabled
VCELL
0.2
Enabled
VSNS
0.4
Enabled
VTEMP
0.6
Disabled
VTEMP
0.8
Fault
Disabled
VFAULT
1.4
8584f
15
LT8584
Operation
Serial Timer Decode Window
The timer initiates on the first negative edge on the DIN pin.
RTMR pin remains high for the duration of the timer which
signifies the decode window for the serial input counter.
A resistor from the RTMR pin to ground sets the decode
window duration. The duration can be accurately set from
1.9ms (RRTMR = 10k) to 31ms (RRTMR = 200k). The timer
can be set outside this range, but the accuracy decreases.
The serial input counter stops counting and latches the
data once the RTMR pin goes low; after which, the OUT
pin amplifier input MUX selects the desired measurement,
and the discharger is set to the right state.
Once the RTMR pin goes low, the MUX selects the OUT pin
mode corresponding to the number of serial input counts
(see Table 1 for available modes). The part can also be
placed in shutdown when RTMR is low and the decode
window has expired.
VCELL Measurement
16
VSNS 19 Amplifier
An amplifier is provided to allow the user to monitor the
discharger current. This measurement can only be performed when the discharger is on (MODE 2). The differential voltage between VVCELL and VVSNS is amplified 19.
8584f
LT8584
Operation
RSNS
1:4
VCELL
VIN
VSNS
LTC680x
SW
LT8584
ANALOG MUX
DCHRG
VMODULE
VCELL
VTEMP
VSNS AMP
VIN 0.2V
VIN 0.4V
BAT2
OUT
C2
DIN
S2
VIN 0.6V
RTMR
VIN 0.8V
VIN 1.2V
VIN 1.4V
MODE
GND
CONTROL
COUNTER
DCC2
BIT
RSNS
1:4
VCELL
VIN
VSNS
ANALOG MUX
DCHRG
ADC
VMODULE
SW
LT8584
VCELL
VTEMP
VSNS AMP
VIN 0.2V
VIN 0.4V
BAT1
OUT
C1
DIN
S1
VIN 0.6V
RTMR
VIN 0.8V
VIN 1.2V
VIN 1.4V
MODE
GND
CONTROL
COUNTER
DCC1
BIT
C0
8584 F06
8584f
17
LT8584
Operation
This reduces errors due to input offset in the measurement circuitry connected to the OUT pin. It also allows
the use of low-value resistors, and thus, yields greater
overall efficiency.
For accuracy, the VIN pin should be tied to the VSNS pin to
include both the LT8584 bias current and the internal NPN
base drive current. Tying the VIN pin to the VSNS pin changes
the overall gain to 20x. Tying the VIN pin to the VCELL measures
transformer current only and the overall gain remains 19x.
TJ (C) =
VTEMP 0.609
0.00197
18
During Decode
Window
MODE 2
MODE 3
MODE 4
8584f
BAT1
BAT2
BAT3
GND
GND
LT8584
VCELL
LT8584
VCELL2
VCELL
GND
LT8584
VCELL3
VCELL
GND
LT8584
VCELL4
VCELL
OUT
OUT
OUT
OUT
ANALOG MUX
SELECTING
VCELL
ANALOG MUX
SELECTING
VCELL
VCELL2
VCELL3
VCELL4
BAT1
BAT2
BAT3
BAT4
GND
GND
LT8584
VCELL
LT8584
VCELL2
VCELL
GND
VCELL
LT8584
VCELL3
GND
VCELL
LT8584
VCELL4
OUT
OUT
OUT
OUT
ANALOG MUX
SELECTING
VCELL
ANALOG MUX
SELECTING
PARAMETER
VCELL2
VCELL3
VPAR,3
VCELL4 +
VPAR,3
C0
C1
C2
C3
C4
ADC
LTC680x
8584 F07
C0
C1
C2
C3
C4
LTC680x
BAT4
MEASUREMENT 1 (VCELL)
LT8584
Operation
8584f
19
LT8584
Applications Information
The LT8584 can be used as a discharger for balancing the
charge in battery or supercapacitor stack systems. The
user can choose either simple mode or serial mode. Most
applications will use the LTC680x to drive the LT8584;
however, the LT8584 can be driven from any battery stack
monitor. Simple mode can be employed using either active
high or active low logic, increasing its interface flexibility.
Component Selection
turns to achieve a desired primary inductance; thus, a balance can be achieved between core and winding losses.
Recommended transformers are given in Table 3 that have
been optimized for efficiency and size. Use the following
guidelines when designing new transformers.
Reduce the transformer size by designing the boundarymode operating frequency between 100kHz and 150kHz.
The peak primary current is fixed at 6A by the chip. The
transformer turns ratio, N, should be selected by optimizing the converter input RMS current, i.e. battery discharge
current. The RMS input current can be estimated as:
Few external components are required to achieve balancing. The only external components are the transformer,
the output diode(s), the VIN bypass capacitors, the RSNS
resistor (for measuring discharge current), the RRTMR resistor (for serial mode), and in some cases, a RCD snubber.
IRMS,IN = IPK
BM tON
3
Transformer Design
The transformer design should yield overall converter
efficiencies greater than 80%. This reduces heat dissipation and allows for a smaller converter PCB footprint.
A proper transformer design balances core losses with
winding losses. The LT8584 converter operates in DCM
where the flux swing in the transformer is the greatest.
This shifts most of the heat loss from winding loss to core
loss. Reduce transformer core flux swing by lowering the
air-gap permeability. A lower permeability requires more
VSW
ISEC
NO SEC.
CAPACITANCE
IPRI
SEC. DISCHARGE
8584 F08
MANUFACTURER
PART NUMBER
Coilcraft
www.coilcraft.com
NA6252-AL
NA5743-AL
NA5920-AL*
10 to 35
30 to 80
100 to 400
Yes
Yes
No
4
4
4
11:15
1:4
1:24
Cooper Bussmann
www.cooperindustries.com
CTX02-19175-R
CTX02-19174-R
CTX02-19176-R*
10 to 35
30 to 80
100 to 400
Yes
Yes
No
15 13 12
15 13 12
15 13 12
4
4
4
3:4
1:4
1:24
Wrth
www.we-online.com
750314019_R01
750314018_R02
750314020_R03*
10 to 35
30 to 80
100 to 400
Yes
Yes
No
4
4
4
3:4
1:4
1:24
* Switch error latch may trip when starting at voltages lower than the recommended output range.
20
8584f
LT8584
Applications Information
The RMS input current can be increased by increasing
the ratio between the effective switch on-time, tON, and
off-time, tOFF. This off-time ratio is set by the transformer
ratio, N. The following equation sets the switch off-time
to approximately 1/3 of the switch on-time to optimize
power transfer and efficiency.
N=
LEAKAGE
SPIKE CLAMPED
TO 50V
VVIN + VSTACK/N
MUST BE LESS THAN 40V
0V
8584 F06
VSW
IPK
1
1
N
BM
+
VIN V MODULE
21
LT8584
Applications Information
Diode leakage current under high reverse bias bleeds the
output battery/capacitor stack of charge. Choose a diode
that has minimal reverse bias leakage current. Diode
junction capacitance is reflected back to the primary, and
energy is lost during negative NPN collection conduction.
Choose a diode with minimal junction capacitance. Table 4
recommends several output diodes for various output
voltages that have adequate reverse recovery times.
Flyback Output Capacitor
Every balancer flyback output must have a ceramic capacitor on its output. The output capacitor serves as a local,
low impedance return path. It also aids during a connection
failure, adding charge storage to allow the OVP circuit to
detect an open. The capacitor should be sized to allow
roughly 10 switch cycles when charging the output from
ground to the nominal output voltage, VOUTPUT,NOM. Use
the following equation to size the output capacitor:
C FBO
400 LPRIMARY
V 2OUTPUT,NOM
The voltage surge rating must exceed 50N. The voltage surge rating is usually specified as a multiple of the
maximum operating voltage. For capacitor maximum
operating voltages less than 100V, the surge rating is
Fairchild Semiconductor
www.fairchildsemi.com
Vishay
www.vishay.com
RECOMMENDED TRANSFORMER
TURNS RATIO (N) RANGE
1 to 2
PART NUMBER
IF(AVG) (A)
VRRM
(V)
trr (ns)
JUNCTION
CAPACITANCE (pF)
PACKAGE
STPS3H100U
100
N/A
90
SMB
STPS2H100AY*
100
N/A
50
SMA
2 to 4
STTH102AY*
200
20
12
SMA
10 to 24
STTH112A
1200
75
1 to 2
ES2B
100
20
SMA
18
SMB
2 to 4
ES1D
200
15
SMA
4 to 8
ES1G
400
35
10
SMA
6 to 12
ES1J
600
35
SMA
1 to 2
SS2H10*
100
N/A
70
SMB
U2B
100
20
16
SMB
2 to 4
10 to 20
ES1D
200
15
10
SMA
ES07D-M*
1.2
200
25
SMF
US1M
1000
50
10
SMA
*AEC-Q101 Qualified
22
8584f
LT8584
Applications Information
Discharge Current Sense Resistor
(k) = 0.015 t2
W + 5.9 tW 1.1
OUT
AMP
LT8584
OUT
OUT
AMP
COUT
47nF
50
COUT
47nF
100nF
TO BSM
2A
100nF
2A
FROM BSM
50
COUT
47nF
100nF
8584 F10
23
LT8584
Applications Information
Hot Swap Protection
Active Solution
Large currents are developed when hot swapping a battery with a LT8584 application due to the large input bulk
capacitance coupled with the low ESR of the batteries. In
most cases, the LT8584 should have no problem handling
the overshoot voltage that follows the large inrush current.
The downstream BSM, however, might encounter damage
that requires additional steps and/or circuitry to protect
against hot swapping. Several solutions use a two-path
method incorporating a pre-charge resistive path and a
shunt path (see Figure 11).
10
VBAT
CVIN
BATTERY
CONNECTION
LT8584
DIN
8584 F11
Mechanical Solution
A mechanical approach results in the most cost effective
solution. A 10 resistor is used to pre-charge the CVIN
capacitor to the battery voltage, limiting the inrush current. After the CVIN cap is charged, a mechanical short is
connected across the resistor and remains there during
all normal operations. There are three recommended solutions for the mechanical short: 1.) use a > 3A rated jumper
2.) use a mechanical switch or 3.) use a staggered-pin
battery connector. The staggered pin connection has the
long pins connecting to LT8584 through the 10 resistor.
The short pins connect directly to the LT8584, shorting
out the 10 resistor. Normal insertion has a delay on the
order of milliseconds between the long pin connecting
and short pin connecting to the circuit, allowing CVIN to
charge up through a current limiting resistor before the
mechanical short is made.
24
8584f
LT8584
Applications Information
TOP
OF STACK
VBAT
TOP
OF STACK
BATTERY
CONNECTION
D2
D1
CVIN
LT8584
VBAT
TO C12
F1, 5A
BATTERY
D1
CONNECTION
10
C1
M1
LT8584
100k
D2
VBAT
D1
CVIN
LT8584
F1, 5A
TO C11
VBAT
D1
10
C1
M1
VBAT
D1
CVIN
LT8584
F1, 5A
TO C10
VBAT
D1
CVIN
LT8584
100k
D2
CVIN
10
C1
M1
100k
CVIN
LT8584
8584 F12
ACTIVE SOLUTION 1
ACTIVE SOLUTION 2
20k
MODULE +
D13
BAT12
BAT2
BAT1
LT8584
GND
SW
D2A
T2
1:4
C2
1F
LT8584
GND
SW
C12
LT8584
GND
SW
D12A
T12
1:4
D1A
T1
1:4
C1
1F
MODULE
25
LT8584
Applications Information
Table 5. Recommended Transient Voltage Suppressors (TVS) for D1 in Figure 12
MANUFACTURER
PART NUMBER
VP-P AT IP-P
PACKAGE
STMicroelectronics
SM2T6V8A
50 at 5V
9.2V at 19.6A
DO-216AA
SM4T6V7AY*
20 at 5V
9.2V at 43.5A
SMA
SMA6T6V7AY*
20 at 5V
9.1V at 68A
SMA
VESD05A1-02V
1 at 5V
12V at 16A
SOD-523
GSOT05*
10 at 5V
12 at 30A
SOT-23
NXP
PESD5V0S1UA
4 at 5V
13.5V at 25A
SOD-323
Infineon
ESD5V0S1U-03W
20 at 5V
14V at 40A
SOD323
VP-P AT IP-P
PACKAGE
Vishay
*AEC-Q101 Qualified
PART NUMBER
STMicroelectronics
ESDALC6V1-1M2
0.1 at 3V
9.2V at 6A
SOD882
Vishay
VBUS051BD-HD1
0.1 at 5V
16V at 3A
LLP1006-2L
VESD05-02V
0.1 at 5V
20V at 6A
SOD-523
Diode Inc
T5V0S5-7
0.05 at 5V
15V at 5A
SOD-523
NXP
PESD9X5.0L*
0.2 at 5V
10V at 1A
SOD-882
*AEC-Q101 Qualified
PART NUMBER
Fairchild Semiconductor
www.fairchildsemi.com
Vishay
www.vishay.com
IDS,MAX
PACKAGE
FDS4465
10.5
13.5
SO-8
FDS6576
20
11
SO-8
FDMA905P
21
10
MicroFET 2x2
FDMA910PZ
24
9.4
MicroFET 2x2
Si7623DN
35
PowerPAK 1212-8
Si7615ADN
9.8
35
PowerPAK 1212-8
SiS407DN
13.8
25
PowerPAK 1212-8
SiA447DJ
19.4
12
PowerPAK SC-70
IF(AVG) (A)
VRRM (V)
PACKAGE
PART NUMBER
Diodes, Inc.
www.diodes.com
SBR8U60P5
60
POWERDI5
PDS760-13
60
POWERDI5
Vishay
www.vishay.com
V8P10-M3
100
TO-277A
SS10P6
60
TO-277A
26
8584f
LT8584
Applications Information
Operating Paralleled LT8584s
Multiple LT8584s may be used if more discharge current
is required. The LT8584 connected to a battery stack
monitor (LTC6804 is recommended) becomes the master balancer. Connect its MODE pin to ground. Limit the
maximum number of parallel slave balancers to 20. This
gives a maximum discharge current of 50A. Other converters may also be used as a slave, including the LT3751
(must connect its VIN to the cell above) and the LT3750.
Connect all slave MODE pins to VIN. This forces those parts
into simple mode and makes their DCHRG pin an input pin.
RSNS
MODULE+
BAT
BAT
VCELL
VSNS
MODE
BAT
MODULE+
BAT
TO ADJACENT
OUT PIN
VIN
SW
MODULE
VCELL VSNS
MODE
LT8584
VIN
MODULE
SW
LT8584
TO C PIN
OUT
DCHRG
OUT
TO S PIN
DIN
RTMR
DIN
GND
DCHRG
GND
RTMR
TO ADJACENT
OUT PIN
8584 F13
MASTER BALANCER
SLAVE BALANCER
8584f
27
LT8584
Applications Information
THERMAL VIAS
GND
16
15
14
13
17
R1 5
T1
11 VSNS
10 VCELL
OUT
GND
CFBO
12 DCHRG
DIN
CVIN
VIN
GND
D1
RTMR
COUT
THERMAL VIAS
TOP OF
BATTERY
STACK
RSNS
VIN
BATTERY
STACK
GROUND
CVTRAN
CVCELL
CELL INPUT
VIN
16
15
14
13
17
TOP OF
BATTERY
STACK
11
10
OUT
9 VIN
SERIAL MODE
BATTERY
STACK
GROUND
CVTRAN
CVCELL
GND
CFBO
12
DIN
COUT
D1
T1
CELL INPUT
8584 F14
SIMPLE MODE
Recommended Layout
The potentially high voltage operation of the LT8584
demands careful attention to the board layout, observing
the following points:
1. Minimize the board trace area of the high voltage end
of the secondary winding.
2. Keep the electrical path formed by CVTRAN, the primary
of T1, the SW node, and ground as short as possible.
Increasing the length of this path effectively increases
the leakage inductance of T1, resulting in excessive
energy loss in the internal Zener clamp or RCD snubber.
28
RSNS
VCELL
VBAT
RTRACE
VSNS
VIN
ISW
LPRI
Q1
8584 F15
8584f
LT8584
Applications Information
Connecting to a Battery Stack Monitor
There are two methods used to connect the LT8584 balancer to a battery stack monitor (BSM): either a single-wire
or two-wire. Both have advantages and disadvantages.
Both methods may require Kelvin connections for the
BSM supply rails depending upon the magnitude of IR
drop across the connections to the battery stack. In most
cases, keeping the individual connection resistances less
than 60m allows the BSM supply rails to share the return
path through RW0 and RW12, see Figure 16.
The single-wire connection is recommended due to complete system visibility of the wire connection impedance.
VMODULE+
BSM
C12
RW12
BAT 12
BSM
BAT 12
RW11
+ VERR
BAT 11
RW10
BALANCING
CURRENT
LT8584
BALANCER ON
BALANCING
CURRENT
LT8584
BALANCER ON
BAT 10
RW9
C12
BALANCING
CURRENT
LT8584
BALANCER ON
BAT 11
C11
RW0
LT8584
BALANCER ON
BALANCING
CURRENT
LT8584
BALANCER ON
C12
C11
RW10
C10
BAT 10
RW1
BAT 1
BALANCING
CURRENT
RW11
ADC
+ VERR
VMODULE
C12
RW12
ADC
BALANCING
CURRENT
LT8584
BALANCER ON
BALANCING
CURRENT
LT8584
BALANCER ON
C10
RW1
BALANCING
CURRENT
LT8584
BALANCER ON
C1
BAT 1
C0
V
C1
C0
V
VMODULE
8584 F16
8584f
29
LT8584
Applications Information
Integrating with the LTC680x Family
Write a 1 to the corresponding DCCx bit in the configuration register of the LTC680x. This pulls its S pin low and
activates the LT8584. Table 10 shows the required time
to turn on one balancer where N = number of LTC6802/
LTC6803s in the system and = frequency of the SCKI
clock.
COMMUNICATION
COMPATIBLE MODES
LTC6801
STEP
LTC6802-1
LTC6802-2
Addressable Parallel
30
Send WRCFG
Command, Write 1
to Enable Balancer
TIME (s)
LTC6802-1/LTC6802-3
LTC6803-1/LTC6803-3
LTC6802-2/LTC6802-4
LTC6803-2/LTC6803-4
(16 + 56 N)
72
LTC6803-1/
LTC6803-2
LTC6803-2/
LTC6803-4
(16 + 56 N)
72
(16 + 56 N) 9
648
8584f
LT8584
Applications Information
+
LTC6802
C(N+1)
VIN
VCELL
MODE
OUT
LT8584
10k
DIN
S(N+1)
ADC
GND
C(N)
VIN
VCELL
MODE
OUT
10k
LT8584
DIN
S(N)
GND
C(N1)
8584 F17
LTC6803/LTC6804
VIN
VCELL
OUT
C(N+1)
LT8584
DIN
GND
S(N+1)
SON
ADC
MODE
VIN
VCELL
OUT
C(N)
LT8584
DIN
GND
S(N)
SON
MODE
C(N1)
8584 F18
31
LT8584
Applications Information
Filtering and ADC Measurements
The LTC680x has an internal multichannel differential ADC
that measures the voltage between each consecutive pair
of C pins. Figures 17 and 18 show the ADC connected to
C(N) and C(N+1), measuring the difference between the
two adjacent LT8584s OUT pins. Most parameters require
two measurements, one with the top LT8584 selecting
VCELL and another one with the top LT8584 selecting
the desired parameter. The difference between these two
measurements yields the desired parameter value. This
is required since the LTC680x is not directly connected to
the battery cells. See the Serial Mode Differential Measurements section for more detail.
Filter capacitors (typically 47nF) have to be placed between
adjacent C pins to provide the required 16kHz lowpass
filter for the ADC input path. This provides 30dB of noise
reduction. No external filter resistors are needed since the
internal impedance from VCELL to OUT is approximately
55. Note that the effective capacitance on the OUT pin
100
VISHAY SFH6720T
5V
TO
10V
VOUT
PULSE
GENERATOR
LT8584
D2
49.9
D1
49.9
10
DIN
G1
GND
100nF
OUT
G2
VCC
2.3k
S2
S1
100
GND
8584 F19
VRTMR
1V/DIV
VDIN
2V/DIV
VOUT
1V/DIV
2ms/DIV
PREVIOUS MODE SELECTED RESET
PULSE COUNTING
MODE4 HANDSHAKE
MODE4 SELECTED
8584 F20
32
8584f
LT8584
Typical Applications
Stackable Fast-Charge 8 to 12-Cell Battery Module, 4.6A Discharge Capability with 2 Parallel LT8584 per Cell
MODULE+
R12A
5m
C12A
100F
2
D12A
C12B
22nF
R12C
4.99k
C12E
100F
T12B
1:4
BAT12
D12D
RTMR
LOCAL
VIN
R12B
100k
DIN
RTMR
C13
47nF
+
C12C
MODULE
1F
LTC680x
BSM
OUT
C12
DIN
S12
LT8584
MASTER
MODE
GND
T12A
1:4
SW
DCHRG
C12G
47nF
LT8584
SLAVE
D12F
OUT
MODE
R12D
4.99k
C12F
1F MODULE
SW
DCHRG
C12H
22nF
D12E
V+
D13
D12B
GND
R2A
5m
C2A
100F
2
D2A
C2B
22nF
R2C
4.99k
C2E
100F
T2B
1:4
D2D
BAT2
RTMR
LOCAL
VIN
OUT
MODE
R2B
100k
DIN
RTMR
C3D
47nF
+
C2C
MODULE
1F
OUT
C2
DIN
S2
LT8584
MASTER
MODE
GND
D3C
D2B
SW
DCHRG
C2G
47nF
LT8584
SLAVE
T2A
1:4
D2F
SW
DCHRG
R2D
4.99k
C2F
MODULE
1F
D2E
C2H
22nF
GND
KELVIN CONNECTION TO R1A
R1A
5m
C1A
100F
2
C1B
22nF
R1C
4.99k
C2E
100F
T1B
1:4
RTMR
D1D
BAT1
LOCAL
VIN
R1D
4.99k
C1F
MODULE
1F
SW
OUT
LT8584
SLAVE
C1H
22nF
D1E
D1A
D2C
DCHRG
R1B
100k
DIN
D1B
RTMR
MODE
MODE
GND
GND
LT8584
MASTER
+
C1C
1F
MODULE
D1F
VCELL VSNS VIN
C1G
47nF
T1A
1:4
C2D
47nF
SW
OUT
C1
DIN
S1
C1D
47nF
RPASS
250
10W
D1C
M1
GPIO1
C0
V
8584 TA02a
MODULE
3
2
1
ERROR (%)
0
1
VCELL = 2.5V
VCELL = 3V
VCELL = 3.6V
VCELL = 4.2V
30
35
40
45
50
MODULE VOLTAGE (VMODULE+ VMODULE)
8584 TA02b
VCELL = 2.5V
VCELL = 3V
VCELL = 3.6V
VCELL = 4.2V
2
3
30
35
40
45
50
MODULE VOLTAGE (VMODULE+ VMODULE)
8584 TA02b
8584f
33
LT8584
Typical Applications
Stackable Fast-Charge 8 to 12-Cell Battery Module
Application Notes
2. Up to 20 LT8584 balancers may be connected in parallel to farther increase discharge current. The DCHRG
pin can also drive an enable pin of a separate DC/DC
converter like the LT3750 capacitor charger.
3. Multiple modules can be stacked in series to achieve
a larger battery stack. Each module must contain an
integer multiple of the total number of cells in the stack.
For instance, an 80 cell stack should be constructed with
8 modules each having 10 cells. Use consecutive BSM
channels starting with BSM channel 1when populating
a module with less than 12 channels. Tie all unused
LTC680x C pins to MODULE+.
4. Place one CnE capacitor close to the Master LT8584s
transformer primary, and place the other CnE capacitor
close to the Slave LT8584s transformer primary. The
symbol n denotes a particular channel ranging from
1 to 12.
5. Place RCD snubber composed of DnF, DnE, RnC, RnD,
CnB, CnH, as close as possible to the respective transformer primary. The symbol n denotes a particular
channel ranging from 1 to 12.
6. RPASS and M1 may be omitted for applications using
only one module in the stack.
7. Each LT8584 channel should have no less than 650mm2
of PCB pad footprint for proper heat sinking.
8. Consult Application Engineering for proper communication with LTC680x family of parts as well as a proper
algorithm for extracting cell parameters.
9. Recommended for cells that operate within a 2.5V to
5.3V range.
34
8584f
LT8584
Package Description
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC
# 05-08-1663 Rev J)
FEDWG
Package
16-Lead Plastic TSSOP (4.4mm)
Pad#Variation
BC Rev J)
(ReferenceExposed
LTC DWG
05-08-1663
Exposed Pad Variation BC
4.90 5.10*
(.193 .201)
3.58
(.141)
16 1514 13 12 11
6.60 0.10
4.50 0.10
0.48
(.019)
REF
3.58
(.141)
2.94
(.116)
10 9
DETAIL B
6.40
2.94
(.252)
(.116)
BSC
SEE NOTE 4
0.45 0.05
1.05 0.10
0.51
(.020)
REF
DETAIL B IS THE PART OF
THE LEAD FRAME FEATURE
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
0.65 BSC
1 2 3 4 5 6 7 8
4.30 4.50*
(.169 .177)
0.09 0.20
(.0035 .0079)
0.25
REF
0.50 0.75
(.020 .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
1.10
(.0433)
MAX
0 8
0.65
(.0256)
BSC
0.195 0.30
(.0077 .0118)
TYP
0.05 0.15
(.002 .006)
FE16 (BC) TSSOP REV J 1012
8584f
35
LT8584
Typical Application
Stackable 8 to 12-Cell Battery Module, LT8584 in Serial Mode, Single-Wire Configuration
Average Cell Discharge Current
MODULE+
R12A
12m
C12E
22nF
C12A
100F
C12B
100F
D12A
BAT12
R12B
100k
R12C
4.99k
C12C
1F
MODULE
SW
DCHRG
OUT
V+
D13
C13
47nF
D12D
D12B
T12
1:4
BATTERY STACK
TO PCB CONNECTION
3.0
LTC6804
BSM
C12
LT8584
MODE
S12
DIN
C2A
100F
R2A
12m
C2B
100F
C2E
22nF
R2C
4.99k
T2
1:4
C2C
1F
MODULE
BAT2
R2B
100k
D3C
OUT
C2
DIN
S2
LT8584
GND
KELVIN CONNECTION TO R1A
C1A
100F
C1B
100F
D1A
C1E
22nF
R1C
4.99k
40
45
50
35
MODULE VOLTAGE (VMODULE+ VMODULE)
0.25
SW
R1A
12m
30
0.30
DCHRG
MODE
2.2
C3D
47nF
2.4
8584 TA03b
D2D
D2A
2.6
D2B
2.8
2.0
GND
VCELL = 2.5V
VCELL = 3V
VCELL = 3.6V
VCELL = 4.2V
D1B
T1
1:4
C1C
1F
MODULE
D1D
0.20
0.15
0.10
VCELL = 2.5V
VCELL = 3V
VCELL = 3.6V
VCELL = 4.2V
0.05
D2C
C2D
47nF
30
40
45
50
35
MODULE VOLTAGE (VMODULE+ VMODULE)
8584 TA03c
BAT1
R1B
100k
SW
DCHRG
OUT
C1
DIN
S1
RTMR
LT8584
MODE
GND
C1D
47nF
GPIO1
D1C
C0
8584 TA03a
MODULE
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
LTC3300-1
LTC6802-1
LTC6803-1/
LTC6803-3
LTC6804-1/
LTC6804-2
www.linear.com/LT8584
8584f
LT 1013 PRINTED IN USA