Documente Academic
Documente Profesional
Documente Cultură
de Electrnica
Microelectronica
Marcelino Santos
Table of contends
Acknowledgements: The author thanks Jos Jesus and Slvia Gomes for their precious help
in the elaboration of this tutorial.
1. Starting Cadence
Starting Cadence for the first time
At first, open a terminal program and source the configuration file cad.init.
> source cad.init
Then create a directory for the project files and change to that directory.
> mkdir cds_tutorial
> cd cds_tutorial
Then a script from AustriaMicroSystems is used to initialize the Cadence Custom IC Design
tools with the process technology C35B3 (-tech c35b3). Also the Command Interpreter
Window (CIW) is started in mode Front-To-Back Design (-mode fb).
> ams_cds -mode fb -tech c35b3
Command Interpreter Window (CIW): To start Cadence tools and enter SKILL
commands. The output of the running tools are displayed here and closing this
window causes the whole suite to close.
Library Manager: To manage the cells with their various views in the libraries. Here
new cells and libraries are created. This tool can be started from the CIW via the
menu bar: Tools - Library Manager.
Close the whats new windows and select the C35B3C0 process.
The library manager window (Fig. 1) can be used for opening existing libraries or cells or
creating new ones. The left column of the library manager window is a list of the current
(accessible) libraries. Among these PRIMLIB contains the transistors you will need for the
inverter.
Left click at PRIMLIB. The middle column shows the elements of PRIMLIB. Left click at
nmos4. This is the basic n-MOS transistor. In the third, rightmost, column you can see
several views of nmos4. You will need the symbol view for the schematic and the layout view
for building the layout.
To hide the Add Instance form during placing press the Hide button. To rotate or flip the cell
press the Rotate (shortcut <r>), Sideways or Uside Down buttons.
Miscellaneous
To zoom in on the schematic select Windows - Zoom - Zoom in (shortcut <z>) and drag a
box around the area of interest. Alternatively, right click and draw the rectangle to zoom in.
To fit the schematic window to the current design select Window - Fit (shortcut <f>).
To move an object:
Very
useful!
Select the object and move the mouse pointer over it until the pointer changes to a
move-object symbol. Press the left mouse button and move the object.
Select Edit - Move (shortcut <M>) from the menu bar and select the object to move.
To edit cell instance properties select the cell in the composer window and choose Edit Properties - Objects (shortcut <q>) from the menu bar.
In the Composer window you can see which command is currently activated and how many
instances are currently selected. In the lower status bar you can see the current actions
assigned to the mouse buttons according to the currently activated command.
Very
important!
shortcut
copy object
Edit - Copy
<c>
detele object
Edit - Delete
<DEL>
rotate object
Edit - Rotate
<r>
Edit - Undo
<u>
Design - Save
<S>
redraw window
<F6>
<ESC>
Very
useful!
Symbol Generation Options appear where the initial positions of the pins can be chosen.
Press OK after assigning the pins to the desired lists.
The Virtuoso Schematic Composer will open in symbol-editing mode and a default symbol will
be created for the cell. Now the symbol can be designed.
After finishing the design of the symbol check and save it with: Design - Check and Save.
The final symbol could look like this (click on the picture to enlarge it):
4. Schematic Simulation
Creating a test bench (schematic for simulation)
The first step to simulate the inverter is to create a schematic with an instance of the new
inverter1 (symbol). To create a schematic refer to section 2. Creating the Schematic of this
document. The schematic of the test bench must be created in the library STUDENTS and
the cell should be named inv_test.
The inverter gate in the simulation schematic is of course the cell inverter1 from the library
STUDENTS.
Add a instance (<i>) of a DC voltage source between vdd and gnd. Use the cell vdc from the
library analogLib and set the parameter DC Voltage to vdd_val V. By connecting this voltage
source to the cells vdd and gnd, from the library analogLib, you are defining vdd and gnd for
all the cells that use these labels.
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3.3 V
Voltage 2
0.0 V
Delay time 0 s
Rise time
5n s
Fall time
5n s
Pulse
width
45n s
Period
100n s
Note that all parameters in the previous table can be defined as function of parameters (e.g.
Pulse with = input_slew; Pulse with = 50n-input_slew). These parameters must be assigned
in the simulator environment, with a constant value or in a parametric analysis.
We also have to name the input wire (e.g. IN) and the output wire (e.g. OUT) so that we can
select them during simulation and plot their voltage curves.
Add a capacitor (cap) of 1pF to the output pin from the library analogLib.
You should end up with the test bench of Fig. 6.
vdc = vdd_value
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details
Setup - Simulator/Directory/Host
Setup - Temperature
- Set Degrees to 25
Setup - Environment
Analyses - Choose
12
Waveform Window
13
IO area
Expressions
It is also possible to enter expressions in the field Outputs of the Virtuoso Analog Environment
to calculate parameters of the cell (propagation delay, output slew, ...) from the simulation
results directly or to plot modified signal curves. These expressions can be tested with the
Calculator!
Select Outputs - Setup from the menu bar of the Virtuoso Analog Environment and add the
following expression:
The expression propagation delay gives the propagation delay of the gate when the input
value changes from IN = 0 to IN = 1.
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After plotting the expression with Results - Plot Outputs - Expressions the result of the
expression for the propagation delay is displayed in the field Outputs of the Virtuoso Analog
Environment.
The current curve of an object node can be accessed with the command i("/object/node"
?result "tran").
Parametric analysis
It is very important to evaluate the circuit behaviour with different temperatures, supply
voltages and technological parameters. Parametric analysis is used in this tutorial to sweep
the vdd_val parameter and the temperature. In the Virtuoso Analog Environment select
Tools Parametric Analysis
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Value
Linear Steps
-10
50
10
From/To
and select
Analysis Start
Fig. 13 Parametric analysis display in the waveform window (with a 1-> 0 zoom in).
Fig. 13 shows how results of parametric analysis with expressions are displayed in the
waveform window: a new graph is displayed with the expression result evolution.
In order to change the power supply value, in the Parametric analysis window select
Setup Pick Name for Variable sweep 1
and select vdd_val. In the Parametric analysis window assign:
Field
Step Control
From
To
Step Size
Range Type
Value
Linear Steps
2
4
1
From/To
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Fig.14 LSW
Check the Pin Label Shape = Label box and enter the Pin Label
Options dialogue window. Set the Layer Name and Layer Purpose to Same as Pin.
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18
shortcut
Design - Save
<F2>
zoom in
Window - Zoom - In
<z>
<f>
Window - Redraw
<F6>
create ruler
<k>
Edit - Undo
<u>
move object
Edit - Move
<m>
stretch object
Edit - Stretch
<s>
delete object
Edit - Delete
<DEL>
Edit - Properties
<q>
Very
useful!
<ESC>
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prBoundary =
limits of the cell
layout
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Also very useful is the mouse function indicator at the bottom of the Layout Window. There
the currently assigned functions to the mouse buttons according to the active command are
indicated.
21
22
23
Fig. 21 Gnd rectangle with pin assignment, substrate connection and nmos placement.
Create a ruler (<k>), starting from the top of the nplus of the nmos transistor, with 1.2 m of
lenght (see Fig. 22).
Rotate and move (<m>) the pmos transistor, centring in the prBoundary box and bringing the
nwell (ntub see Fig. 22) to the distance pointed by the ruler.
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shortcut
rectangle
Create - Rectangle
<r>
polygon
Create - Polygon
<P>
path
Create - Path
<p>
Before activating a command select the desired layer in the Layer Selection Window (LSW)!
When the path command is activated and the path has been started at an identifiable
connection Virtuoso XL highlights the geometries and terminals of other components which
should be connected. To change the layer while drawing a path use the path options invoked
by pressing <F3>. There the Change To Layer option can be modified and Virtuoso XL
automatically generates the contacts from one layer to another.
Inter-layer contacts can be created explicitly through Create - Contact (shortcut <o>). To
establish a connection between the metal layer 2 and the poly layer 1, two of these contacts
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have to be placed: MET2 -> MET1 (VIA1_C) and MET1 -> POLY1 (P1_C). They can be
placed right over each other.
With the command Connectivity - Show Incomplete Nets one can highligt signal nets that
haven't been routed correctly and completely. To end the highlighting of incomplete nets
select Connectivity - Hide Incomplete Nets from the menu bar.
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Fig. 24 Connection of the pmos source, n-well contact and vdd! pin assignment.
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6. Design-Rule-Check (DRC)
The layout of a cell must be drawn according to a set of strict design rules. During the DesignRule-Check a program checks the design against the design rules and reports any violations.
Starting DRC
To start the DRC for the layout select
Verify - DRC
from the menu bar of the Virtuoso Layout XL Editor where the layout intended for checking is
opened. In the appearing form, the DRC can be parameterized. Set the following options:
option
set to
comment
any instances of other cells found in the layout
should also be checked (layout of this cells must
also be available!)
Checking
Method
flat
Checking Limit
full
Switch Names
...
Rules File
../divaDRC.rul
Rules Library
TECH_C35B3
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After hitting OK the DRC is carried out and any violations are highlighted in the layout by
flashing markers and the errors are reported in the CIW (see Fig. 26).
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When we select an error in the list, Virtuoso XL focuses to the area in the layout where the
error occurs. If there is more than one error with the same name, we can switch between
these errors with the Error Number slider. The Zoom Factor applied by Virtuoso XL to focus to
an error can also be set with a slider.
To delete all markers press the button Delete all Marker in the DRC Error Search form or
select Verify - Markers - Delete All from the Virtuoso XL menu bar.
Some c35b3 rules are:
Minimal:
Width
Spacing
NTUB
3
3
DIFF
0,3
0,6
POLY1
0,35
0,45
PPLUS/NPLUS
1,6
1,6
POLY2
0,65
0,5
CONT
1
1,2
MET1
0,5
0,45*
VIA
1,2
1,6
MET2
0,6
0,5**
PAD
15
25
*
If the MET1 is wide (width>10m) then 0,8
**
If the MET2 is wide (width >10m) then 0,8
Spacing
Width
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7. Extraction
Circuit extraction is performed after the mask layout design of the cell is completed. It creates
a detailed netlist (extracted netlist) of the cell which can be used for example in the Layoutversus-Schematic check or by a circuit simulator. The circuit extractor is capable of identifying
the individual transistors and their interconnections as well as the parasitic resistances and
capacitances that are inevitably present in the cell. Thus, the extracted netlist provides a very
accurate model of the cell.
Starting extraction
To start the extraction select
Verify - Extract
from the menu bar of the Virtuoso Layout XL Editor where the layout intended for extraction is
opened. In the appearing form, the options for the extractor can be given. Set the following
options:
option
set to
comment
Extract Method
flat
Switch Names
capall
View
extracted
Names Extracted
Rules File
../divaEXT.rul
Rules Library
TECH_C35B3 Disable the library that contains the extraction rules file
After hitting OK the extraction is carried out and a new view called extracted is generated for
the cell (Library Manager).
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Parasitics probing
The different nets in the extracted netlist can be probed to get a summary of the parasitics
(resistances, capacitances) present on the nets. Since we could only extract parasitic
capacitances during the extraction of the netlist, no values for parasitic resistances are
indicated.
To set a parasitics probe press the button Parasitic Probe in the LVS Window. In the next
window press the button Whole Net and select a net in the layout window where the extracted
view is shown. It is also possible to get a summary of parasitics between nets. Therefore, use
the button Net To Net before selecting two nets in the extracted view.
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9. Post-Layout Simulation
It is now easy to simulate the layout (more exactly the extracted netlist) with the Virtuoso
Analog Circuit Design Environment. Close the layout editor window and open the test bench
for the simulation of the cell schematic (Section 4. Schematic Simulation). The same test
bench can be used for the extracted simulation. Open the test bench schematic and select
from the Composer window of the simulation schematic
Tools - Analog Environment
Configure the simulation conditions as described in Section 4 and choose:
Setup - Environment
and set Switch View List to spectreS cmos_sch extracted schematic. As a result of this, if the
simulator now creates the netlist of the simulated circuit it uses the extracted netlist of the cell
rather than the schematic.
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