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Documente Cultură
Datapath Design
General Objective:
Determine the hardware requirement of a digital computer
based on its instruction set.
Specific Objectives:
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0001
SUB
0010
OUT
HLT
0011
1111
Description
Load ACC with the contents of the memory specified
address.
Add the contents of the ACC with the contents of the B
register and place the result in the ACC.
SUBtract the contents of the B register from the ACC and
store the result in the ACC.
OUTput he contents of the ACC to the OUTR register.
Halt or stop MSAP.
Instruction Format
D7 D6 D5 D4
OPCODE
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D3 D2 D1 D0
OPERAND
ACC
ACC
+
TMP
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TMP
3
ACC
+/TMP
su
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MAR
Address
Data out
REG
rd
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EXecute
Cycle
MAR
Address
Data out
rd
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PC
PC
Memory Unit
(2N x M)
MAR
MAR
Address
Data out
rd
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Memory Unit
(2N x M)
IR
Address
Data out
ACC
rd
7
Din
Load
clk
Dout
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0
1
destination
select
N - 1 MUX
Reg0
Reg1
Reg2
RegN
source select
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the instruction set of a digital computer defines the set of operation its datapath
can support.
instructions defines the characteristics and capabilities of the processing elements
of the datapath.
arithmetic instructions such as addition and subtraction can be implemented using
adder and subtractor circuit.
registers are provided to hold data needed by arithmetic circuits.
computer cycles involve the fetch cycle and the execute cycle.
registers are organized to facilitate transfer of data to required parts of the system.
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10
Reset
Control Signals
Combinational
Network
Memory
(State)
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11
Reset
Control Unit
Datapath
Combinational
Network
(Binary Multiplier)
Memory
(State)
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12
Reset
Control Unit
Datapath
Combinational
Network
Memory
(State)
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13
Reset
Combinational
Network
Memory
(State)
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Datapath
IR
PC
Memory
14
Reset
Combinational
Network
Memory
(State)
Datapath
IR
PC
Memory
ACC
TMP
Processing
Elements
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+/su
15
Reset
Combinational
Network
Datapath
IR
PC
Data
Routing
circuits
Memory
(State)
Memory
ACC
TMP
Processing
Elements
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+/su
16
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17
MEMORY
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18
Fetch
Cycle
Elements
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19
Processing
Elements
(EXecute
Cycle)
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Data
Routing
Circuits
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Control
Unit
Memory
Unit
Central
Processing
Unit
InputOutput
Unit
22
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25
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26
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27
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30
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clrpc
incpc
desSel
srcSel
rd
su
000'
000'
PC 0
CLEAR PC or reset
000'
000'
MAR PC
PC to MAR
100'
001'
IR M[MAR]
000'
000'
PC PC + 1
INCrement PC
000'
101
MAR IR[3:0]
001'
001'
A M[MAR]
010'
001'
B M[MAR]
001'
100'
AA+ B
001'
100'
AA- B
011'
010'
OUTR A
ACC to OUTR
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Micro operations
Description
35
incpc
desSel
srcSel
rd
su
Hexcode
Micro operations
RESET
000'
000'
200
PC 0
Fetch Cycle
000'
000'
000'
MAR PC
100'
001'
186
IR M[MAR], PC PC + 1
LDA
000'
101
010'
MAR IR[3:0]
001'
001'
026'
000'
101
010'
MAR IR[3:0]
010'
001'
046'
B M[MAR]
001'
100'
030'
A A + B, goto Fetch
SUB
000'
101
010'
MAR IR[3:0]
010'
001'
046'
B M[MAR]
001'
100'
031'
A A - B, goto Fetch
OUT
011'
010'
068'
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000'
000'
000'
enstate 0
36
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Control
Unit
Memory
Unit
THANK YOU
Central
Processing
Unit
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InputOutput
Unit
38