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Integrated Circuit
Zou Zhige
Spring, 2010
Chapter 5
Passive and Active
Current Mirrors
Zou Zhige
Spring, 2010
Calculate the
out
AV = g m ( ron // rop )
in
2
SS
VLSI, EST
Table of Contents
Introduction
Basic Current Mirrors
Cascode Current Mirrors
Active Current Mirrors
Introduction
Large-signal analyses
Small-signal analyses
Common response
Zou Zhige
VLSI, EST
Introduction
We have learned current source:
Current source can act as a large resistor without consuming excessive
voltage headroom.
MOS in saturation can act as current source.
All the amplifier need current source or resistor for load current.
Zou Zhige
VLSI, EST
Table of Contents
Introduction
Basic Current Mirrors
Cascode Current Mirrors
Active Current Mirrors
Introduction
Large-signal analyses
Small-signal analyses
Common response
Zou Zhige
VLSI, EST
Zou Zhige
VLSI, EST
1
W
I out = nCox (VGS VT )2 ,
2
L
VGS
R2
=
VDD
R1 + R2
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Why?
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Copying Current
Current
Mirror
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10
Iout
W W
= ( )2 /( )1 Iref
L
L
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11
current source
REF
out2
out1
current sink
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12
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13
Another Example
Av=?
(W / L) 3
AV = g m1 RL
(W / L) 2
Current Transfer!
1
AV = g m1 (ro1 ||
|| ro 2 ) g m 3 (ro 3 || RL )
gm2
Zou Zhige
VLSI, EST
14
Table of Contents
Introduction
Basic Current Mirrors
Cascode Current Mirrors
Active Current Mirrors
Introduction
Large-signal analyses
Small-signal analyses
Common response
Zou Zhige
VLSI, EST
15
Drawback of Basic CM
Consider the channel length modulation effect:
I OUT =
1
W
u n C ox (VGS VTH ) 2 (1 + V DS )
2
L
I D 2 (W / L)2 (1 + VDS 2 )
=
I D1 (W / L)1 (1 + VDS1 )
VDS1 VDS 2
We should reduce the channel length modulation. Or there is
other method?
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16
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17
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18
Choose Vb , let
I out I REF
Output resistance:
Rout p = gm3ro3ro2
R Y = ro 2
ro 2
1
Vy =
V p =
V p
g m3 ro 3 ro 2
g m 3ro 3
How to get Vb ?
Zou Zhige
VLSI, EST
19
V X = VY
We should have :
Vb = VGS 3 + V X
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20
W
W
W W
( )o /( )3 = ( )1 /( )2
L
L
L
L
Zou Zhige
Then:
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V X = VY
21
Region of M2 and M3
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22
Voltage Headroom 1
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23
Voltage Headroom 2
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V X VY
I out I REF
24
Voltage Headroom 3
V p min = Vod 3 + VGS 2
= Vod 3 + VGS 2 VTH 2 + VTH 2
= 2Vod + VTH
To ensure:
So:
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V X = VY
I out I REF
25
DD
out
2
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26
V A = Vb VGS 2 VGS1 VT H 1
V X = VGS1
DD
Vx Vb VTH 2
Range of Vb
V x + VTH
out
2
Vb VGS 2 + V x VTH 1
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27
out
2
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28
I*R=VTH1
VGS2=VGS5
The right figure:
We need big (W/L)7 for VGS7=VTH1
VGS2=VGS5
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29
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30
Design Considerations
Work with integer ratios and unit devices as much as possible.
Using a unit device of size 1
Keep mirror ratio (IOUT/IREF) reasonably small
Typically no larger than 1020
Distribute currents
Have one global bias cell close to reference that sends currents into local
biasing sub-circuits
Disadvantage: Consumes additional current
Zou Zhige
VLSI, EST
31
Class Exercise
Ignore the output
voltage of IREF
All W/L, except M4:
W/4L
Please calculate :
Iout And the min Vp
and VDD
Zou Zhige
VLSI, EST
DD
REF
A
4
2
3
out
6
B
2
32
Thanks!