Existing methodology

CTRL

OR

AND

XOR

Multiplication is usually performed using booth and modified booth

algorithm.

Booth's multiplication algorithm is a multiplication algorithm that

multiplies two signed binary numbers in two's complement notation.

The algorithm was invented by Andrew Donald Booth in 1950 while

doing research on crystallography at Birkbeck
College in Bloomsbury, London.

Booth used desk calculators that were faster at shifting than adding
and created the algorithm to increase their speed. Booth's algorithm is
of interest in the study of computer architecture.

Booth's algorithm examines adjacent pairs of bits of the N-bit

multiplier Y in signed two's complement representation, including an
implicit bit below the least significant bit, y-1 = 0. For each bit yi,
for i running from 0 to N-1, the bits yi and yi-1 are considered. Where
these two bits are equal, the product accumulator P is left unchanged.
Where yi = 0 and yi-1 = 1, the multiplicand times 2i is added to P; and
where yi = 1 and yi-1 = 0, the multiplicand times 2i is subtracted from P.
The final value of P is the signed product.
The representation of the multiplicand and product are not specified;
typically, these are both also in two's complement representation, like
the multiplier, but any number system that supports addition and
subtraction will work as well. As stated here, the order of the steps is
not determined.
Typically, it proceeds from LSB to MSB, starting at i = 0; the
multiplication by 2i is then typically replaced by incremental shifting of
the P accumulator to the right between steps; low bits can be shifted

out, and subsequent additions and subtractions can then be done just
on the highest N bits of P.[1] There are many variations and
optimizations on these details.
The algorithm is often described as converting strings of 1's in the
multiplier to a high-order +1 and a low-order 1 at the ends of the
string. When a string runs through the MSB, there is no high-order +1,
and the net effect is interpretation as a negative of the appropriate
value.

DISAVANTAGES1.

Doesnot save in speed

2.

Increased area

3.

Increased power

To overcome these disadvantages proposed methodology is used.

As we had seen the disadvantages of using different memory space(area) for

different ALU operations In this propose methodology,we use the concept of Vedic
Maths where we combine the adder,subtractor and multiplier within an area and
hence we aim to overcome the disadvantages of using same memory space for
various ALU operations such as : Addition, Subtraction,Multiplication. Thereby
reducing the power consumption which plays a vital role in VLSI and thus making it
cost efficient.
THE HARDWARE AND SOFTWARE USED

HARDWARE:-SPARTON 3E FROM XILINX

The Spartan-3E family of Field-Programmable Gate Arrays (FPGAs) is
specifically design to meet the needs of high volume, cost-sensitive consumer
electronic applications.
The Spartan-3E family builds on the success of the earlier Spartan-3 family by
increasing the amount of logic per I/O,significantly reducing the cost per logic cell.
New features improve system performance and reduce the cost of configuration.
These Spartan-3E FPGA enhancements, combined with advanced 90 nm process
technology, deliver more functionality and bandwidth per dollar .
Because of their exceptionally low cost, Spartan-3E FPGAs are ideally suited to a
wide range of consumer electronics applications, including broadband access, home
networking, display/projection, and digital television equipment.

The Spartan-3E family is a superior alternative to mask programmed ASICs. FPGAs

avoid the high initial cost, the lengthy development cycles, and the inherent
inflexibility of conventional ASICs. Also, FPGA programmability permits design
upgrades in the field with no hardware replacement necessary, an impossibility with
ASICs.

The Spartan-3 platform was the industrys first 90nm FPGA, delivering more
functionality and bandwidth per dollar than was previously possible, setting new
standards in the programmable logic industry.

Features
Very low cost
Abundant, flexible logic resources
Densities up to 33,192 logic cells, including optional shift register or
Distributed RAM support.
Efficient wide multiplexers, wide logic
Fast look-ahead carry logic
Enhanced 18 x 18 multipliers with optional pipeline

Spartan-3E FPGAs support the following differential

standards:
LVDS
Bus LVDS
mini-LVDS
RSDS
Differential HSTL (1.8V, Types I and III)
Differential SSTL (2.5V and 1.8V, TySpartan-3E FPGAs support the following
differential
The Spartan-3E FPGA SelectIO interface supports many
popular single-ended and differential standards. IEEE 1149.1/1532 JTAG
programming/debug port

Spartan-3E FPGAs support the following single-ended

standards:

3.3V low-voltage TTL (LVTTL)

Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,1.5V, or 1.2V
3V PCI at 33 MHz, and in some devices, 66 MHz
HSTL I and III at 1.8V, commonly used in memory applications
SSTL I at 1.8V and 2.5V, commonly used for memory applications.

Spartan-3E FPGAs support the following differential standards:

LVDS
Bus LVDS
mini-LVDS
RSDS
Differential HSTL (1.8V, Types I and III)
Differential SSTL (2.5V and 1.8V, Type I)
2.5V LVPECL inputs

SOFTWARE:-MODELSIM
Mentor Graphics ModelSim ME HDL Simulator is a source-level verification tool,
allowing you to verify HDL code line by line. You can perform simulation at all levels:
behavioral (pre-synthesis), structural (post-synthesis), and back-annotated, dynamic
simulation.
Coupled with the most popular HDL debugging capabilities in the industry, ModelSim
ME is known for delivering high performance, ease of use, and outstanding product
support.
An easy-to-use graphical user interface enables you to quickly identify and debug
problems, aided by dynamically updated windows. For example, selecting a design
region in the Structure window automatically updates the Source, Signals, Process,
and Variables windows.. Once a problem is found, you can edit, recompile, and resimulate.
ModelSim ME fully supports current VHDL and Verilog language standards. You can
simulate behavioral, RTL, and gate-level code separately or simultaneously.
ModelSim supports all Microsemi FPGA libraries, ensuring accurate timing
simulations.
The comprehensive user interface makes efficient use of desktop real estate. The
intuitive arrangement of interactive graphical elements (windows, toolbars, menus,

etc.) makes it easy to view and access the many powerful capabilities of ModelSim.
The result is a feature-rich user interface that is easy to use and quickly mastered.

Future Scope and Applications:

The proposed Vedic mathematics based multiplier proves to be highly efficient in
terms of speed. Due to its regular and parallel structure, it can be realized easily on
silicon as well.
The multiplier is essential and abundant in DSP applications. Achieving maximum
implementation efficiency and clock performance is therefore critical to DSP
systems and frequently presents a significant challenge to hardware engineers.
Multipliers based on vedic mathematics increase the speed of operation of
multipliers.
Vedic mathematics multipliers are also used in Image Processing, VLSI circuits and
Intel microprocessors.
Another interesting application of these multipliers is in the implementation of
Advanced Encryption Standard algorithm. The Advanced Encryption Standard (AES)
is

specification

for

the encryption

of

electronic

data

established

by

the

U.S. National Institute of Standards and Technology (NIST) in 2001. It is based on

the Rijndael cipher developed

by

two Belgian cryptographers, Joan

Daemon and Vincent Rijmen, who submitted a proposal to NIST during the AES
selection process. Rijndael is a family of ciphers with different key and block sizes.
For AES, NIST selected three members of the Rijndael family, each with a block size
of 128 bits, but three different key lengths: 128, 192 and 256 bits.