CAD Interfaces Translator Notes

October 2012

CAD Interface
IC Package Design tools:
Sigrity UPD (Unified Package Designer)
Synopsys Encore
Cadence APD, SIP
PCB Design tools:
ODB++ - All CAD tools that support ODB++ output
(Expedition, P-CAD, Boardstation, Altium)
Cadence Allegro, PCB SI, Specctra Router
Mentor Board Station, Expedition, PowerPCB, ICX
Zuken CR-5000/8000, Visula
Altium Altium Designer pre-version 10 only (Protel), P-CAD
YDC Cadvance III Design

2012 Cadence Design Systems, Inc. All rights reserved.

ODB++ for most PCB Design tools

including Altium, Mentor Boardstation, Expedition, Zuken,
PCAD

Most CAD tools now support ODB++

ODB++ > .SPD

In the CAD Design tools menu select File -> Export ODB++ to create the ODB++ file. Be sure to
enable all options so that you get the most complete data set possible.
View the ODB++ database using Mentors ODB++ viewer to be sure your design is in the desired
state:
http://www.mentor.com/products/pcb-system-design/downloads/odb-viewer
If it is not then update the design in the CAD tool and regenerate the ODB++
ODB++ output should be written to a compressed archive with these typical extensions:

.zip
.tgz
.tar
.Z
.gz
.7z
Run SPDLinks.exe and select the ODB++ file browser filter
Browse to the ODB++ file
Modify your settings as needed
Modify the net set if applicable
Press the translate button

Sigrity modules: SPDLinks.exe, ODBExtractor.dll

2012 Cadence Design Systems, Inc. All rights reserved.

Package/Board/SIP Design Cadence

Package Designer, SIP or Board Designer

.MCM/.SIP/.BRD > .SPD
o
o
o
o

A working Cadence environment is required. Contact Cadence support for help

setting one up
Cadence .mcm/.sip/.brd files are binary. Cadence Extracta.exe will output
ASCII format which Sigrity translators uses to generate our SPD file.
SPDLinks BRDExtractor runs Extracta.exe and generates the SPD. Specify the
extracta and env paths using SPDLinks > settings > environment tab.
To determine the design file version:

On Allegro Package Designer installed machine, in command

prompt:
dbstat filename.mcm
System will return the version
o

To prevent unknown problem by incorrect .mcm database:

On Allegro Package Designer installed machine, DOS command

prompt type:
>dbdoctor filename.brd
Sigrity module: SPDLinks.exe, BRDExtractor.dll

2012 Cadence Design Systems, Inc. All rights reserved.

PCB Design Zuken, Visula

CR-5000 and CR-8000 Board Designer

.PCF, .FTF, .DSGF, .MRF > .SPD
(these files are the Zuken database in a non-compressed ASCII format)
o Licensed Board Designer software is required
o To generate .pcf and .ftf files:
Open a command window
Change to design directory
>pcout filename (no file suffix) will create filename.pcf
>fcout filename (no file suffix) will create filename.ftf
Refer to Zuken documentation on how to generate dsgf and mrf CR8000 files
Place the two files in the same folder. filename.mrf is optional.
Launch SPDLinks and select CR5000 (*.pcf;*.ftf;*.mrf) as the file format
to be translated
o Choose any of the .pcf, .ftf or .mcf file an the design will be translated

Sigrity modules: SPDLinks.exe, CR5000Extractor.dll

Visula
.RIF > .SPD
o Generate a .RIF file from Visula
o Use rif2spd.exe to translate RIF to SPD

Sigrity modules: RIF2SPD.exe

2012 Cadence Design Systems, Inc. All rights reserved.

PCB Design Altium (Refer to ODB++ , the recommended flow)

Altium Designer (Protel) (Obsolete)
AddOnServer only works with pre-version 10 release Protel Service Pack4. If Altium/Sigrity interface is new to you please refer
to ODB++ interface section

.PCBDOC > .SPD

Download these 3 Add-on files from SPDNet

AddOnServer.DLL , AddOnServer.RCS, AddOnServer.INS

Move the files to the System folder for Altium2004
C:\Program Files\Altium2004\System
In Altium Designer environment, select File -> Export to Sigrity SPD File to create a *.spd file in
the same folder as the original Altium design file.

Sigrity modules: SPDLinks.exe, AddOnServer.dll, AddOnServer.ins, AddOnServer.rcs

P-CAD (ODB++ recommended)

.PCB > .SPD
1. Export ODB++ with all entities enabled
2. Use SPDLinks to translate DesignName.zip or .tgz to DesignName.SPD
Sigrity modules: SPDLinks.exe, ODBExtractor.dll

2012 Cadence Design Systems, Inc. All rights reserved.

PCB Design Mentor Graphics - Boardstation

Recommended ODB++ to SPD

Generate ODB++ from Boardstation

Use SPDLinks with ODBExtractor

Sigrity modules: SPDLinks.exe, ODBExtractor.dll

Option1 Direct .SPD link (Integrated flow, requires

working licensed seat of Mentor Boardstation)

Direct export of SPD file from the Mentor Board Station

Interface (installation instructions in appendix).
After installation choose Export to Sigrity SPD file from
Boardstation menu

Option2 Manual .SPD generation from Board Station files

If you have access to the Mentor Board Station database, but not to Mentor
Board Station itself, this procedure can be used. The method uses the Sigrity
SpdLinks program and 4 files from the layout database: geoms.geoms_NN,
neutral_file, tech.tech_NN andtraces.traces_NN. More information in
appendix

Sigrity modules: SPDLinks.exe, BoardStationExtractor.dll

2012 Cadence Design Systems, Inc. All rights reserved.

PCB Design Mentor Graphics Expedition Discontinued

Please generate an ODB++ file and use SPDLinks instead
VBASCII > .SPD
The SPD file is generated using SpdLinks and the VBASCII output from
Expedition.
The procedure requires access to an Expedition license
The translation procedure is as follows
1. In Expedition Export the HKP files
2. Select all seven HKP files and click OK
NetProps.hkp and NetClass.hkp can be omitted if using Mentor CES
3. Recent versions of Expedition produce binary hkp so you will need a Mentor
provided utility to convert them to ASCII. Contact Mentor customer support.
4. Open SpdLinks
5. Locate the Layout.hkp file
6. Select output name and click translate
Note: For extremely large designs it may not be possible to Export>ASCII
and/or translate the layout on a 32bit machine. You may need to utilize a 64
bit machine.
Sigrity modules: SPDLinks.exe, ExpeditionExtractor.dll
2012 Cadence Design Systems, Inc. All rights reserved.

PCB Design YDC Cadvance III Design

.DBR/.DBG/.NET > .SPD
The SPD file is generated using SpdLinks and the DBR, DBG
and NET output from Cadvance.
The translation procedure is as follows
1. In Cadvance output the Design.dbr and Design.dbg files and
in output connection data select the output property text
option and write the netlist to Design.net in the same
directory.
2. Open SpdLinks
3. Choose the Cadvance dbr files file type and open the
Design.dbr file
4. Hit translate and the SPD output will be written to
Design.spd
Sigrity modules: SPDLinks.exe, CadvanceExtractor.dll

2012 Cadence Design Systems, Inc. All rights reserved.

PCB Design Mentor Graphics - PADS (formerly PowerPCB)

.ASC > .SPD
Note: PADS2SPD does not support negative plane layers
Plane layers must be split/mixed and poured prior to exporting ASCII. To
pour:
Go to Tools > Pour Manager
In the Plane Connect tab, Select All then Start, answer yes to ok to
connect planes
In the Hatch tab, choose Hatch All and press Start
In the Flood tab, choose Flood All and press Start.
PADS Export ASCII:
In Setup > Preferences > Split/Mixed Plane
Set Save to PCB to All Plane Data
Set Mixed Plane Display to Generated Plane Data
In File > Export set file type to ASCII (.asc) and press save.
In the ASCII Output window dialog that appears:
Press the Select All button to choose all sections
Set Units to Basic
Select the Expand attributes boxes for Parts and Nets.
Press OK
Translate the ASC file to SPD using Pads2SPD.exe

Sigrity modules: PADS2SPD.exe

2012 Cadence Design Systems, Inc. All rights reserved.

PCB Design Mentor Graphics

ICX
.ICX > .NDD > .SPD

Not a direct export from within ICX, instead, the translation relies
on a bat file included with ICX that allow bidirectional translation
between ICX and NDD files.
Use the xForm.bat utility to convert from .ICX to .NDD
Usage: xform -extract_ndd -icx <FileName.icx>
-ndd <FileName.ndd> -log <FileName.log>
Location: %MGC_HOME%\bin\xForm.bat
Use the Ndd2Spd translator to generate the .SPD file.
Please refer to the NDD related tips towards the end of this
presentation.
Sigrity modules: NDD2SPD.exe
2012 Cadence Design Systems, Inc. All rights reserved.

General tips for successful translation

If your CAD tool can generate ODB++ please try the SPDLinks ODB++
translator, view the file in the ODB viewer to be sure it is analysis-ready
Make sure planes are poured before export (in case you have static pour)
Do Not pour using stroked lines, they cause problems and lead to
unmanageable file sizes and node count
Define as much of the stackup as possible in the layout tool (i.e. thickness,
conductivity, dielectric constant and loss tangents). This will make the most
efficient translation flow.
o Alternatively, it is possible to keep one master .spd file for each stackup
type, and then use the Import button in the stackup editor in the Sigrity
tools to reuse it.
Make sure all vias are assigned a padstack. If antipads are defined as part of
the planes and not the padstack the simulation results will be less accurate or
manual correction will be required after translation.

2012 Cadence Design Systems, Inc. All rights reserved.

Specific NDD* related tips

Output ODB++ and use the ODB++ SPDLinks translator instead for best
results.
If you insist on NDD be warned that the NDD format is incomplete for
describing a PCB layout. This implies that some conducting areas / copper
shapes are not included. The Sigrity NDD2SPD translator allows you to link to
an ascii file that contains the relevant data this is the Layout.hkp file which
is typically included when using an ICX export from a layout tool.
If NDD file comes from Mentor Board Station thermal ties can be included by
linking to a trace.trace_NN file (see ref [1,39pp]).
The IBIS files used in the ICX project can be automatically included in the
translation if a subfolder named IBISModles is placed in the main directory
with the .NDD file. All the models can automatically be exported from within
the IS tool from the menu File->Export->Models

* NDD is an abbreviation for Neutral Design Data

Sigrity modules used: ndd2spd.exe

2012 Cadence Design Systems, Inc. All rights reserved.

Zuken FAQ
Q: What are the Zuken CR5000 ascii file output anyway?
A: The files represent the Zuken database in a non-compressed ASCII format that allows them to be read by 3rd party software. The ASCII output
consists of four (4) files:
name.pkf (Footprint Referrences)
name.prf (Parts File)
name.ftf (Footprint File)
name.pcf (PCB Layout File)
name.mrf (Material Definition File)

Q: How to generate ASCII output (.pcf and .ftf) from Zuken CR5000 (Zuken Redac Board Designer)?
A: Two Board Designer command-line de-compile utilities, pcout and ftout, must be run against the design in order to produce the required .ftf
and .pcf files. This procedure should be run on a system that has the Board Designer software installed and Licensed and also has access to the
design data to be worked with.
1. Open a Command Prompt (DOS shell).
2. Change Directory to the design directory.
3. Execute the following command: pcout BASENAME
* BASENAME: Basename of the pcb and pcf (without file suffix) There are many other options which can be specified with the pcout command. To
get a list of these options and usage instructions simply run "pcout" at the command prompt.
4. This will produce a file 'basename.pcf'. This is the .pcf file.
5. Execute the following command: ftout BASENAME
* BASENAME: Basename of the ftp (or pcb, pnl) and tft (without file suffix) There are many other options which can be specified with the ftout
command. To get a list of these options and usage instructions simply run "ftout" at the command prompt.
6. This will produce a file 'basename.tft'. This is the .tft file
Notes On File Generation
If running these commands produces the message: 'pcout' is not recognized as an internal or external command, operable program or batch file; or
'ftout' is not recognized as an internal or external command, operable program or batch file, then there are one of two possibilities.
One - The de-compilers or the Board Designer software is not installed on your workstation and will need to be installed.
Two - The location of the de-compilers is not part of the workstations 'PATH' variable and this location will need to be added to the 'PATH' variable or
the full path and executable will need to be specified at the Command Prompt.

2012 Cadence Design Systems, Inc. All rights reserved.

Translator FAQ 1
Q: For the NDD translator I see possibility to include a "Layout.hkp" file. What is that used for?
A: We now recommend you generate ODB++ from Mentor and use SPDLinks ODB++ option. But if you insist, the NDD format
unfortunately has some inherent flaws that cannot be accommodated for in the format. This implies that some conducting areas /
copper shapes are not included. The Sigrity NDD2SPD translator thus allows you to link to another layout description which can
include these missing shapes. The translator uses the ASCII HKP output that were generated from Expedition but have since been
discontinued by Mentor. Use ODB++ flow instead
Q: I am translating a package layout from APD / Allegro Package Designer and the wirebond layers are not converted correctly. What
could be wrong?
A1: The automatic conversion of wirebond layers by our SPDLinks BRDExtractor requires each die have the "COMP_WIRE_BOND"
flag set in APD. This normally occurs by default if the design has been created according to Cadence standard procedures.
A2: If you have the a special XML file describing the wirebond models rename it so it has the same name as the design. So for a
DesignName.sip you should have a DesignName.xml so SPDLinks knows to get the actual wirebond models. If not found it will creates
generic wirebond profiles which you can modify using the "Wirebond Model Library" in the Sigrity analysis tool.
Q: How to set the COMP_WIRE_BOND flag in APD in very old designs (not needed in a properly defined 16.3+ design)
A: Please follow below procedure:
1. Setup, Property Definitions
2. In the Name box enter, COMP_WIRE_BOND and hit the tab key.
3. Uncheck all Data Elements except Comps.
4. Set Data Type to BOOLEAN. Then click OK to exit the form.
5. Edit, Properties, and set Find box Comps only.
6. Click a die pin. When the form pops-up, select COMP_WIRE_BOND from available properties.
7. Make sure the Value is TRUE and click OK to close the form.
Now the COMP_WIRE_BOND flag should be set:
REFDES COMP_CLASS COMP_PACKAGE COMP_DEVICE_TYPE COMP_WIRE_BOND
BGA IO BGA BGA
DIE IC DIE DIE YES

2012 Cadence Design Systems, Inc. All rights reserved.

Translator FAQ 2

Q: Some interconnect is missing in a layout that was translated, Why?

A1: If an object has no net it will be ignored if the Include elements with
no net names setting is disabled.
Q: How do I translate a .sip, .mcm or .brd file?
First install the Cadence free viewer (follow the link at the end of the
appendix) then run SPDLinks and use the environment tab of the settings
section. Browse to the env and extracta.exe found in your companys
Cadence installation.
A: If you still have difficulty, contact si-support@cadence.com for
assistance

2012 Cadence Design Systems, Inc. All rights reserved.

Translator FAQ 3

Q: The translated SPD file only shows some component values and others are completely empty. Did
something go wrong in the translation?
A: Typical design databases have only capacitors, inductors and coils defined with default values i.e. no
parasitics. We suggest you maintain a circuit library with the appropriate model definitions, which can
quickly be merged with the SPD file after translation.
Q: My design contains negative plane layers. When I translate the board they are not handled correctly,
what could be wrong?
A1: We suggest trying ODB++ because the manufacturing ready plane data is stored in ODB++
A2 If the design comes from Mentor Board Station and you insist on using that interface, please make
sure that all split-plane layer information is defined on power layers within Mentor Board Station.
A3: A4: If the design comes from PADS we do not support negative planes. Have your CAD department
convert them to positive or use ODB++ if available

2012 Cadence Design Systems, Inc. All rights reserved.

Appendix: Mentor Board Station Translation

Installation of the direct SPD interface

1. Download the integration scripts from Sigrity customer website:

http://www.sigrity.com/spdnet/translators/pc/Sigrity_Interface.zip

2. Unzip the sigrity_interface directory to the <MGC_HOME>/pkgs

directory
3. Setup the AMPLE_PATH environment variable to point to the
<MGC_HOME>/pkgs/sigrity_interface/userware/En_na directory
4. Export the design from the Top Menu as
shown on the right (Export to Sigrity SPD File)

Sigrity modules used: SPDLinks.exe, BoardStationExtractor.dll

2012 Cadence Design Systems, Inc. All rights reserved.

Appendix: Mentor Board Station Translation

Manual database translation

1.
2.

3.
4.
5.
6.
7.
8.

Create a new directory

Locate the latest geometry, neutral, tech, and traces file in the Mentor Board Station directory and
place them in the newly created directory
1. The latest files are typically indicated by a number suffix. The file that has the highest suffix is
the latest files
2. The files must be ASCII sometimes e.g. the geometry file is appended with _ascii
3. The neutral file is often found in the mfg directory the rest of the files in the main pcb directory
Rename the 4 files to MentorGeometryFile, MentorNeutralFile, MentorTechFile and
MentorTracesFile respectively
Open SpdLinks
Select file type as Mentor Boardstation Files (Folder)
Navigate to the directory in (1)
Click Open Folder
Type a name for the translated file and click ok

Sigrity modules: SPDLinks.exe, BoardStationExtractor.dll

2012 Cadence Design Systems, Inc. All rights reserved.

Appendix: Free Layout Viewers

Free layout viewers , when you do not have access to the layout software
o Altium:
http://www.altium.com/community/downloads/en/viewer-edition.cfm
o Cadence viewers:
http://www.cadence.com/products/si_pk_bd/downloads/allegroviewers/index.aspx
o Mentor Board Station / Expedition:
http://www.mentor.com/products/pcb-system-design/browsers.cfm
o ODB++ Viewer:
http://www.mentor.com/products/pcb-system-design/downloads/odb-viewer
o PCAD Free viewer:
http://downloads.altium.com/P-CAD/PCAD2006_Viewer_19.02.9660.zip
o Sigrity UPD viewer:
http://www.sigrity.com/support/demo/upd_viewer_dl.htm
o Zuken Board Designer Viewer (CR5000):
http://www.zuken.com/products/cr-5000.aspx
o Zuken CADSTAR Design Viewer:
http://www.zuken.com/products/cadstar/downloads/designviewer.aspx
o Cadvance Design Viewer:
http://www.ydc.co.jp/download/trial/
Links updated on May 18, 2010

2012 Cadence Design Systems, Inc. All rights reserved.