Section-B

VLSI Circuit Design

Fall-2014-2015

BiCMOS INVERTER:
Made up of both Enhancement type Field Effect Transistor (MOSFET) and

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na ty Ib
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niv En Ala
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(A
I

biasing resistors {collector, base and emitter} has been ignored for simplicity)

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Bipolar Junction Transistor (BJT) and hence the name BiCMOS. (The BJT

Circuit Diagram of a BiCMOS INVERTER

Characteristics of BiCMOS Inverter:

The output cannot go to VDD or Ground unlike for what we saw in the case of

In
te
r

CMOS inverter.

This lowers the noise margins of the logic.

The maximum output logic voltage is approximately VDD-0.7V.

The minimum output logic voltage is approximately 0.7V.

ica

The 0.7V drop for high and low logic comes from the base to emitter junction

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er

voltage drop of Q2 and Q1 Bipolar Junction Transistors.

Tawsif Ibne Alam
Faculty Engineering
American International University-Bangaldesh (AIUB)

Section-B

VLSI Circuit Design

Fall-2014-2015

Note: Caution should be exercised when working with the output of BiCMOS
gates with CMOS logic. The low output voltage of 0.7V is very close to the

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)

threshold voltage of the n-channel transistor. (CMOS gates with switching point

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tio ul sif
na ty Ib
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niv En Ala
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sit ee
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To understand the operation of the basic BiCMOS inverter;

Operating Principle:

(A
I

voltages close to the threshold voltages are susceptible to noise.)

Consider the case when the input is grounded.

Vin=0

MOSFETs M4 and M1 are in ON

state and M2 and M3 are in OFF

HIGH / 1

state.

M1 is ON due to the fact that the

static CMOS inverter output is

high. This results the base of the

LOW / 0

LOW / 0

Q1 to be at held at ground
potential

by

the

short

circuited FET, M1.

The HIGH output of the static

CMOS inverter is also holding the base of Q2 at VDD.

As a result of that Q1 is OFF and Q2 is ON, providing an output voltage

of VDD-0.7V across the load capacitor. (0.7V drop is occurring due to

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ica

In
te
r

the p-n junction voltage drop of Q2).

Tawsif Ibne Alam

Faculty Engineering
American International University-Bangaldesh (AIUB)

Section-B

VLSI Circuit Design

Fall-2014-2015

Now consider when the input is

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held @ VDD.
LOW / 0

Vin=VDD.

HIGH / 1
HIGH / 1

OFF state.

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tio ul sif
na ty Ib
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M1 is OFF due to the fact that

state while M4 and M1 are in

(A
I

MOSFETs M3 and M2 are in ON

the static CMOS inverter

output is LOW.

The LOW output of static

CMOS inverter is also holding the base of Q2 at a LOW potential,

turning Q2 OFF as well.

As M2 is ON, the base of Q1 is at a HIGH potential turning it ON,

shorting the output terminal to the ground. But due to the p-n
junction of the base-emitter in Q1, the output is held at 0.7V at pull

Am

er

ica

In
te
r

down condition.

Tawsif Ibne Alam

Faculty Engineering
American International University-Bangaldesh (AIUB)