M.Tech EC (VLSI & ES) Course Structure and Syllabus PDF

GANPAT UNIVERSITY
U.V.PATEL COLLEGE OF ENGINEERING

GANPAT VIDYANAGAR, KHERVA-384012
ELECTRONICS & COMMUNICATION ENGINEERING DEPARTMENT
SYLLABUS SCHEME
FOR
1ST TO 4TH SEMESTER
M.TECH-EC (VLSI & EMBEDDED SYSTEMS)
U.V.Patel College OF Engineering

Constituent College of Ganpat University
Ganpat Vidyanagar,
Mehsana-Gozaria Highway,
Kherva (Dist: Mehsana) Gujarat
Phone: +91-2762-286805, +91-2762-286082
Fax: +91-2762-286650
Web: www.uvpce.ac.in
GANPAT UNIVERSITY
M. TECH. (ELECTRONICS & COMMUNICATION) VLSI & Embedded Systems
Teaching & Examination Scheme
Semester I
Teaching Scheme
Subject
Code
Credit
Subject
Lect.
Tutorial
Pract
Total
Theory
Examination Scheme
Theory
Tut.
&
Pract
Total
Practical
Total
Int.
Assess.
Ext.
Assess.
Total
Grand
Total
Sem End
Int.
Assess.
Marks
Hrs
3EC111
Digital VLSI Design
40
60
100
25
25
50
150
3EC112
Operating Systems
2
2
60
100
25
25
50
150
5
5
40
Algorithms
Digital Signal
Processing
1
1
3EC113
3
3
40
60
100
25
25
50
150
3
0
1
0
40
60
100
25
25
50
150
25
25
50
50
50
50
100
100
30
12
11
2
23
12
4
14
--
--
--
--
3EC114
3EC115
Seminar I
3EC116
Mini Project I
Total Contact Hours
Soft skills- Presentation, Attitude and Technical writing

Optimization Methods
Total Marks
750

Semester II
Teaching Scheme
Subject
Code
3EC211
3EC212
Credit
Examination Scheme
Theory
Subject
Lect.
Computer
Architecture
Data Interfaces &
Protocols
Tutorial
Pract
Total
Theory
Tut.
&
Pract
Total
5
5
Sem End
Int.
Ass
Marks
Hrs
40
60
40
Grand
Total
Practical
Total
Int.
Ass.
Ext.
Ass.
Total
100
25
25
50
150
60
100
25
25
50
150
3EC2**
Elective I*
40
60
100
25
25
50
150
3EC2**
Elective II*
System Level
Design Lab
40
60
100
25
25
50
150
25
25
50
50
Mini Project II
Total Contact
Hours
50
50
100
100
12
14
30
12
11
23
--
--
--
--
3EC213
3EC214
Total Marks
750
Note: In addition to the above, a certificate course on Interview Skills and Corporate Etiquettes must be cleared by students in
second semester based on internal assessment only.
*Elective I & II
1
2
3
4
5
6
Subject Code(**)
RTOS, Kernels and device drivers
15
Verification Techniques
16
Network Programming
17
Embedded System Design & Architecture
18
Hardware Board Designing with PCB Designing
19
Advanced VLSI Design
20

Semester III
Teaching Scheme
Subject
Code
3EC311
3EC312
3EC313
Subject
Elective III*
Quality
Assurance and
Reliability
Dissertation
Part-I
Total Contact
Hours
1
2
3
4
5
6
7
8
9
Lect
Tut
Prac
Credit
Total
Theory
Tut.
&
Pract.
Total
Int.
Ass.
Theory
Sem End
Grand Total
Total
Int.
Ass.
Ext.
Ass.
Total
100
25
25
50
150
40
Marks
60
25
45
70
15
15
30
100
16
16
100
100
200
200
20
27
12
17
--
--
--
--
*Elective III
Memory Designs
Wireless Sensors and Adhoc Networks
Image Processing
Advanced Digital Communication System
Android and iPhone stack
Systems Security
Multicore Architecture & Designing of
Processors
Low Power Design
Advanced Mixed Signal IC Design
Hrs
3
Examination Scheme
Practical
Total Marks
450

Semester IV
Teaching Scheme
Subject
Code
3EC411
Subject
Dissertation
Part-II
Total
Contact
Hours
Lect.
Tuto.
Pract
Credit
Total
Theory
Tut. &
Pract
Total
Theory
Sem End
Int.
Ass.
Marks
Hrs
Examination Scheme
Practical
Total
24
24
12
12
24
24
12
12
--
--
--
--
Grand
Total
Int.
Ass.
Ext.
Ass.
Total
200
200
400
Total Marks
400
400
GANPAT UNIVERSITY
DETAILED SYLLABUS
FOR
1ST SEMESTER

Ganpat Vidyanagar,
Phone: +91-2762-286805, +91-2762-286082
Fax: +91-2762-286650
SEMESTER I
3EC111 Digital VLSI Design
Teaching Scheme
Credit
Examination Scheme
Theory
Lect
Tuto.
Pract.
Total
Theory
Tut
&
Pra.
Total
Practical
Sem End
Int.
Ass.
Marks
Hrs
40
60
Total
Int.
Ass.
Ext.
Ass.
Total
Grand
Total
100
25
25
50
150
INTRODUCTION
Course program on Digital VLSI Design is assigned for Post Graduate education on
VLSI Design & Embedded Systems specialization and is taught in the Post Graduate 1st
semester. The course duration is 100 hours, lectures are 40-45 hours and
laboratory/assignment/project works are 35-40 hours.
Digital system Design
Concepts of Basic electronics
COURSE GOALSAND OBJECTIVES:
Trainees to understand the fundamentals of digital design and how each digital
systemworksUnderstanding of Finite state machine implementation of same. Hands on
with coding in Verilog and writing test benches for the same.
COURSE CONTENT:
1. Introduction:
Binary Number systems, One's complement, 2's complement and sign- magnitude,addition
of 2'complement numbers, Logical and arithmetic shifting, binary fractions, Fundamentals
of RC circuits, Low pass and high pass RC circuits, time constant, capacitor charging,
charging equations, rise time, propagation delay.
2. Boolean function and its minimization:
Canonical forms of two level logic circuits - POS and SOP canonical forms, Binary
decision diagrams, Binary decision diagrams and Reduced ordered BDD; example BDD
for a simple logic function, Reduction of logical functions using K-map; Design by the
usage of NOR / NAND gates implementation.
3. Basic Combination circuits:
Basic combinational circuits; multiplexer and application of multiplexer as a multipurpose logical element, Two-level multiplexer logic, Demultiplexers, decoders; using
multiplexers to construct basic gates like OR, AND, Priority encoders, comparators,
majority logic function, parity bit generator.
4. Arithmetic Circuits:
adder, half and full adder, types of adders, Fast adders, carry- lookahead adder etc.
concept of overflow and underflow, parallel (combinational) multipliers - basic design.
5. Sequential circuits:
General structure of a state machine; concept of a state, Types of Flops, conversion of one
flop to another Flop; excitation table for flip flops, Synchronous counters and ripple
counters; shift registers.
6. Finite State Machine:
Introduction to finite state machine - concept of state; types of state machines, reduction of
state machine, Simple state machine problems and writing Verilog code for them,
Advanced state machine problems and Writing Verilog code for them.
7. Designing of memory and gate arrays:
FIFO, SRAM, PLA, PAL, FPGA, CPLD
8. ASIC and FPGA Design Flow, Static timing analysis
LABORATORY WORKS (35HOURS):
Tools used during laboratory works: CVER, VCS, Design Vision,
Design Compiler.
Implementation of all the designs taught using Verilog HDL
COURSE PROJECT:
A project of suitable complexity, comprising of RTL design and directed testbench
formation must be completed by the student in approximately 35-40 hours.
REFERENCES:
1. R. Katz , Contemporary logic design by Pearson Prentice Hall.
2. Charles H. Roth, Jr. Larry L. Kinney, Fundamentals of Logic Design, 7thEdition,Cengage
Learning, 2013, ISBN-13: 9781133628477.
3. Switching and finite automata by Zvikohavi and Niraj Jha
4. J.F. Wakerly. Digital Design - Principles & Practices, Prentice Hall, 2001.
3EC112 Operating Systems

Teaching Scheme
Credit
Examination Scheme
Theory
Lect
Tuto.
Pract.
Total
Theory
Tut.
&
Pra.
Total
Practical
Sem End
Int.
Ass.
Marks
Hrs
40
60
Total
Int.
Ass.
Ext.
Ass.
Total
Grand
Total
100
25
25
50
150
INTRODUCTION
Course program on Operating Systems is assigned for Post Graduate education on
VLSI Design & Embedded Systems specialization and is taught in the Post Graduate 1st
semester.
The study of data structures, algorithms, programming languages, compilers and
operating systems. In the process of the laboratory work it is necessary to use and study
standard programming, compilation and debugging tools. A project of reasonable
complexity must be completed.
1. Introduction (3 hours):
What is an operating system, computer hardware review, Operating System Concepts,
System calls, Operating System Structure.
2. Processes and Threads (5 hours):
Processes, Threads, Inter process Communication and problems, Scheduling.
3. Memory Management (5 hours):
Memory Abstraction, Virtual memory, Page replacement algorithms, Design and
Implementation Issues, Segmentation
4. File systems (4 hours):
Files, Directories, File system implementation, File management and optimization,
Examples on file systems.
5. Input/output (6 hours):
I/O Devices, Device Controllers, Memory-mapped I/O, DMA, Programmed I/O and
Interrupt driven I/O, Interrupt handlers, Clocks, User Interfaces, Power management.
6. Deadlocks (6 hours):
Preemptable and Non-Preemptable resources, Resource acquisition, Introduction to
deadlocks, Ostrich algorithm, Deadlock detection and recovery, Deadlock avoidance and
prevention, Other Issues.

Tools used during laboratory works: Linux, Perl, Gcc,Gdb.
1. Study and implementation of processor performance using opencores.
(10 hours).
2. Study and implementation of performance of openSPARC and ARM /
ARC processors. (15 hours).
3. Study and implementation of SOC architectures (10 hours.).
COURSE PROJECT:
A project of suitable complexity, comprising of program design, coding, compilation
and debug must be completed in approximately 20 hours.
REFERENCES:
1. Computer Architecture, A Quantitative approach by D.Patterson and J.
Hennessy.
2. Computer Organization by D. Patterson and J. Henness
3EC113 Algorithms
Teaching Scheme
Credit
Examination Scheme
Theory
Lect
Tuto.
Pract.
Total
Theory
Tut.
&
Pra.
Total
Practical
Sem End
Int.
Ass.
Marks
Hrs
40
60
Total
Int.
Ass.
Ext.
Ass.
Total
Grand
Total
100
25
25
50
150
INTRODUCTION
Course program on Algorithms for Embedded Systems is assigned for Post Graduate
education on VLSI Design and Embedded Systems specialization and is taught in Post
Graduate 1st semester.
1. Linux
2. C concepts
COURSE GOALS AND OBJECTIVES
The goal of the course is to teach the essentials of Algorithms in terms of their usage in
VLSIand Embedded Field.
Mainly it is to develop the thought process for the logical development and comparison for
problem solving approach. In the process of the laboratory work it is necessary to
implement those algorithms and use and study standard and emerging architectures. A
project of reasonable complexity must be completed.
1. Basic Data Structure and its Complexity:
An activity-selection problem, Elements of the greedy strategy, Huffman codes
2. Greedy Programming:
Methods of optimization
3. String Matching:
The naive string-matching algorithm, The Rabin-Karp algorithm, string matching
with finite automation.
4. Hashing:
Hashing, Direct-address tables, hash tables, Hash functions, open addressing.
5. Trees:
Some binary trees. Tree terms. Recursive trees. Complete binary trees. Binary tree
heights. Heaps, maintaining the heap property, Building a heap, the heap-sort
Algorithm,priorityqueues, what is a binary search tree? Querying a binary search
tree, Insertion and deletion,AVL Tree
6. Graphs:
Graph algorithms. Directed graph. Graph representation: adjacency list, adjacency
matrix. Depth-First Search Algorithm. Breadth-First Search Algorithm. Shortest
path based algorithms. Prim`s Algorithm. Kruskals Algorithms. data-flow graph
(DFG). Data-flow Graph Representation. Graph-theoretical Formulation.
Maximum-distance constraints. Longest-path algorithm for DAGs. Maze routing
algorithms.
7. Polynomials and FFT:
Representing polynomials, The DFT and FFT, Efficient FFT implementations.
LABORATORY WORKS(35 HOURS)
Tools used during laboratory works: Linux, Gcc, Gdb.
1. Study and implementation all the data structures and Algorithms
studiedin the class
2. Examples solving mainly for complexity and analysis of Algorithms
REFERENCES
1. Introduction to Algorithms, Third Edition by Thomas H. Cormen, Charles E.
Leiserson, Ronald L. Rivest and Clifford Stein
2. The C Programming Language by Kernighan and Dennis Ritchie.
3EC114 Digital Signal Processing

Teaching Scheme
Credit
Examination Scheme
Theory
Lect
Tuto.
Pract.
Total
Theory
Tut.
&
Pra.
Total
Practical
Sem End
Int.
Ass.
Marks
Hrs
40
60
Total
Int.
Ass.
Ext.
Ass.
Total
Grand
Total
100
25
25
50
150
INTRODUCTION:
Course program on Digital Signal Processing is assigned for postgraduate education
on VLSI Design and Embedded Systems specialization and is taught in the 1st
semester The course duration is 68 hours, lectures volume is 34 hours, and laboratory
works are 34 hours.
The goal of the course is to teach the students to the theoretical bases of digital signal
processing, with the methods of description of discrete and digital signals and systems
in the domain, z and transform domain including discrete and fast Fourier
transforms.
The study of methods of design of digital filters.
In the process of the laboratory work it is necessary using Matlab program system, to
investigate and design the digital filters.
SYLLABUS:
1. Signal and signal processing (2 hours):
Classification of signals, examples of typical signals, signal applications.
2. Discrete signals in the time domain (4 hours):
Discrete time signals, the sampling process, characterization of linear time-invariant
systems, random signals, correlation of signals.
3. Discrete signals in the transform domain (8 hours):
The Fourier transforms, the discrete Fourier transform and its properties,
Linear convolutions, the fast Fourier transform the z-transform and inverse ztransform.
4. Linear time-invariant discrete systems in the transform domain (6 hours):
Finite dimensional discrete systems, the transfer function, simple digital filters,
Inverse systems, complementary transfer function, system identification, algebraic
Stability test, matched filter.
5. Digital processing of continuous-time signals (4 hours):

Sampling of continuous-time signals analog low pass filter design, design of analog
high pass, band pass and band shop filters, analog - to - digital converter, digital - to
analog converter.
6. Digital filter structures (4 hours):
Block diagram representation, basic finite impulse response (FIR) digital filter
structures,basic infinite impulse (IIR) response digital filter structures, all pass filters,
IIR Tapped cascaded lattice structure, FIR cascaded lattice structure, digital sinecosine generator.
7. Digital filter design (6 hours):
Preliminary considerations bilinear transformation method of IIR filter design, design
oflowpass, high pass, band pass, band shop IIR digital filters, spectral transformations
of IIR digitalfilters, spectral transformation of IIR filters, FIR filter design based on
Windowed Fourier series, design of FIR digital filters with least-mean-square error.

Tools used during laboratory works: Matlab.
1. Signal generation using Matlab. Sampling process (2 hours).
2. Discrete-time system and its classification (2 hours).
3. Output computation using Matlab. Correlation computation. Correlation computation
Of periodic signals (2 hours).
4. Discrete Fourier transformation computation using Matlab (2 hours).
5. Linear convolution (2 hours).
6. Discrete-time signals in the transform domain (2 hours).
7. Z-transform and inverse z-transform using Matlab (2 hours).
8. Linear time-invariant systems in the transform domain (2 hours).
9. Fourier fast transform (5 hours).
10. Analog filter design using Matlab (2 hours).
11. Realization of basic filter structures using Matlab (3 hours).
12. Digital filters design using Matlab (4 hours).
13. Window-based filter design (4 hours).
COURSE PROJECT:
A project of suitable complexity, comprising of Matlab based coding must be completed
by the student in approximately 34-40 hours.
REFERENCES:
To study the course the necessary list of references is given below.
1. Discrete-Time Signal Processing by A. V. Oppenheim and R. W. Schafer, EEE, 2nd

Edition, Prentice Hall.
2. Digital Signal Processing: Principles, Algorithms, and Applications by J. G. Proakis
and D. G. Manolakis, 4th Edition, Prentice Hall.
3. Digital Signal Processing in Communication Systems by Marvin E. Frerking, Springer.
4. Theory and Application of Digital Signal Processing by Rabiner and Gold, Printice
Hall.
5. Digital Signal Processing, Sanjit K Mitra, 3rd Edition, McGraw-Hill.
3EC115 Seminar I
Teaching Scheme
Credit
Examination Scheme
Theory
Lect
Tuto.
Pract.
Total
Theory
Tut.
&
Pra.
Total
Practical
Sem End
Int.
Ass
Marks
Hrs
Total
Int.
Ass.
Ext.
Ass.
Total
Grand
Total
25
25
50
50
Students have to choose seminar topic from recent trends and Technology and at the end
of semester they have to give presentation.
3EC116 Mini Project I
Teaching Scheme
Credit
Examination Scheme
Theory
Lect
Tuto.
Pract.
Total
Theory
Tut.
&
Pra.
Total
Practical
Sem End
Int.
Assess
Marks
Hrs
Total
Int.
Ass.
Ext.
Ass.
Total
Grand
Total
50
50
100
100
Students have to carry out the project under the guidance of faculty member using the
knowledge of subjects that he/she has learned in semester. Students have to submit project
report withcode at the end of the semester.
GANPAT UNIVERSITY
DETAILED SYLLABUS
FOR
2ND SEMESTER

Ganpat Vidyanagar,
Phone: +91-2762-286805, +91-2762-286082
Fax: +91-2762-286650
SEMESTER 2
3EC211Computer Architecture
Teaching Scheme
Credit
Examination Scheme
Theory
Lect
Tuto.
Pract
Total
Theory
Tut.
&
Pra
Total
Practical
Sem End
Int.
Ass.
Marks
Hrs
40
60
Total
Int.
Ass.
Ext.
Ass.
Total
Grand
Total
100
25
25
50
150
INTRODUCTION
Course program on Computer Architecture is assigned for Post Graduate education on
VLSI Design and Embedded Systems specialization and is taught in Post Graduate 1st
semester. The course duration is 100 hours, lectures are 45-48 hours and
laboratory/assignment/project works are 52-55 hours.
The goal of the course is to teach the essentials of Computer Architecture.
The study of architectural elements, performance metrics and system architecture of
computer systems. In the process of the laboratory work it is necessary to use and study
standard and emerging architectures. A project of reasonable complexity must be completed.
Basic concepts of computer organization.The stored program model.Classes of
computerarchitecture.Processor vs. System architecture.Elements of computer systems
processors, memories, I/Os, disks, buses etc.
2. Performance measurement in computer architecture (6 hours):
Goals of computer architecture performance, throughput, latency, power, cost. Processor
performance vs. system performance.Comparison of various platforms in terms of
performance and efficiency.
3. Processor Architectures (18 hours):
Internal elements and architecture of processors.Instruction execution. Instruction set
architectures, CISC vs. RISC architectures. Bus architecture.Multi-Processor
architecture.Memories and Caches.Cache coherency.Pipelining and data path elements.
4. System and System on Chip architecture (9 hours):

System architecture elements.H/W component selection and datasheet analysis.Bill of
Materials.IP selection and System on Chip integration. Standard interfaces and I/Os. Analog
and Mixed signal element integration. Reset and clocking elements. Multi-processor system.
5. Special processor/system architectures (3 hours):
Application
specific
processors.Packet
controllers.DSPandMultimedia processors.
processing.Microcontrollers.Network
6. Current Architectural survey (3 hours):

An overview of the latest Intel, ARM, TI, SPARC and Power PC architectures as modern
SOC architectural elements.
LABORATORY WORKS (35 hours)
Tools used during laboratory works: Verilog, Xilinx ISE, DC, Waveform viewer
1. Study and implementation of processor performance using opencores. (10 hours).
2. Study and implementation of performance of openSPARC and ARM / ARC processors
(15 hours).
3.Study and implementation of SOC architectures (10 hours.).
4.Design of entire one Processor using the tools as Mini Project.
COURSE PROJECT
A project of suitable complexity, comprising of program, computer architecture design,
coding, compilation.FPGA implementation and debug must be completed in approximately
20 hours.
METHODIC PROVISION OF THE COURSE
The course program is compiled taking into account that the following courses had
been studied Beforehand:
Digital design (undergraduate course)

Computer Organization
Understanding of the course is the basis for the further specialized subjects destined by the
educational plan of VLSI Design and embedded systems specialization.
REFERENCES BOOKS
1. Computer Architecture, A Quantitative approach by D.Patterson and J. Hennessy
2. Computer Organization by D. Patterson and J.Hennessy
3. Embedded Core Design with FPGAs, ZainalabedinNavabi
3EC212 Data Interfaces & Protocols

Teaching Scheme
Lect
Tuto.
Pract
Credit
Total
Theory
Examination Scheme
Theory
Tut.
&
Pra
Total
Practical
Total
Int.
Ass.
Ext.
Ass.
Total
Grand
Total
100
25
25
50
150
Sem End
Int.
Ass
Marks
Hrs
40
60

The goal of the course is to introduce the concepts, terminologies and technologies used in
modern days data communication, protocols and Interfacing.
1.
2.
3.
4.
5.
To make students familiar with the interfaces used for data communications.
To understand the concepts of data communications.
To study the functions of different layers.
To introduce IEEE standards employed in computer networking.
To make the students to get familiarized with different protocols and network
components.
COURSE CONTENTS
1. Introduction (8 hrs):
OSI Revision IP, TCP, UDP, PDP, x. 25
2. Wireless Protocols (4 hrs for each protocol):
a) High Frequency, short distance: (a)Bluetooth (b) ZigBee
b) High frequency, medium distance: (a)WiFi
c) High frequency, long distance: (a)GSM, 2G,3G,4G (b) Wi MAX (c)LTEandother
proprietary
3. Physical Layer, Data link layer and Transport Layer for all the protocols above:
Signal Analysis - Transmission Media Coaxial Cable Fiber Optics Wireless
Transmission PSTN Modulation Techniques.Error detection and correction Parity
LRC CRC Hamming code Link Layer Control Multiple access links Multiple Access
Protocols ARP - LAN - Ethernet IEEE 802.3 IEEE,802.4 - IEEE 802.5 - IEEE 802.11
PPP HDLC.Duties of transport layer Reliable Data Transfer protocols - Multiplexing
Demultiplexing Sockets User Datagram Protocol (UDP) Transmission Control Protocol
(TCP) Congestion Control Quality of services (QOS) Integrated Services.

Tools used during laboratory works: Verilog, DC, Waveform viewer
1. Study of Protocols and their implementation in Matlab
2. Understanding of OSI and TCP/IP working using Wireshark or Network Simulator.
COURSE PROJECT
A project of suitable complexity, comprising of program design, coding, compilation and
debug must be completed in approximately 20 hours.
The course program is compiled taking into account that the following courses had been
studied beforehand:
1. Digital design (undergraduate course)
2. Computer Organization
educational plan of VLSI Design and embedded systems specialization.
REFERENCE BOOKS
1. Behrouz A. Forouzan, Data communication and Networking, Tata McGraw-Hill, 2004.
2. James F. Kurose and Keith W. Ross, Computer Networking: A Top-Down Approach
Featuring the Internet, Pearson Education, 2003.
3. Larry L.Peterson and Peter S. Davie, Computer Networks, Harcourt Asia Pvt. Ltd.,
Second Edition.
4. Andrew S. Tanenbaum, Computer Networks, PHI, Fourth Edition, 2003.
5. William Stallings, Data and Computer Communication, Sixth Edition, Pearson
Education, 2000.
6. Data sheets for every Protocol for study.
Elective-I & II
3EC215 RTOS, Kernels and device drivers
Teaching Scheme
Lect
Tuto.
Pract
Credit
Total
Theory
Examination Scheme
Theory
Tut.
&
Pra
Total
Practical
Total
Int.
Ass.
Ext.
Ass.
Total
Grand
Total
100
25
25
50
150
Sem End
Int.
Ass.
Marks
Hrs
40
60

The study of embedded systems architecture, hardware-software abstraction, resource
allocation, software stacks, Real time Systems and operating systems internals.
In the process of the laboratory work it is necessary to use and study standard and emerging
development kit platforms for OS development. A project of reasonable complexity must be
completed on an embedded system platform.
COURSE CONTENTS
1. Introduction(3 hours):
Embedded System Architecture fundamentals.Hardware and
models.Operating Systems fundamentals.Real time OS overview.
Software
abstraction
2. OS internals and Kernels (15 hours):

Internal components of Operating systems. Study, compare and contrast of various OS
platforms. Unix/Linux kernel fundamentals. I/O devices, file systems and peripheral devices.
3.
RTOS Fundamentals (15 hours):

Study of Real
time OS
principles
and requirements.Application specific
requirements.Throughput and latency requirements.Schedulers, tasks and processes.Memory
management.Code and footprint optimization.Study of current and emerging RTOS.
4. Device drivers (9 hours):

Fundamentals of device drivers, device enumeration and configuration.Data transfer and
management mechanisms.Wired and wireless connectivity of devices. Power Management and
its impact on device management. Compliance to protocols.
5.
Real Time linux
Measuring real-time behaviour

The characteristics of a realtimetask
Different ways of instrumentingcode.
5.1 Features in the Linux kernel for measuring delays and variability:
What happens in overloadconditions (when the schedulecannot be met)

Scheduling, processes andthreads
Review the difference betweenprocess and threads in Linux
5.2 Scheduling policies and priorities for Real time and Non-Real time tasks:
Periodic tasks
Assigning priorities using ratemonotonic analysis
5.3 Synchronization between threads:
Description of the variousmutex types Linux has to offerand when to use each one
The problem of priorityinversion and priority
Inheritance mutexes
Timers and periodic tasks
A look at the accuracy oftimers
Configuring high resolution timers
5.4 Using POSIX timers:
Creating reliable periodic tasks

Interrupts and kernel
Preemption
5.5 Description of the interrupt model and factors that cause interrupt jiffer:
How kernel pre-emption helps

The problem with kernel spinlocks
PREEMPT_RT: The Real TimeLinux Kernel
Analysis of non-preemptivesections in Linux (atomiccontexts)
Description of PREEMTP_RTreal time Linux patch andhow it resolves the problem

Tools used during laboratory works: Keil, Cypress PSoC, Windows Mobile, Linux, VxWorks,
Symbian platforms.
1. Practical for linux kernel understanding.
2. Practical related to RTOS and Operating Systems.
3. Theory reading of Beegle board XM can be given to them and just one doubt solving session
on itSomepracticals on Beegle board XM.
4. Architecture and circuit designing of the interfacing board.
5. Study and implementation of kernel modifications.
6. Device driver writing finally for the same.
COURSE PROJECT (30 hours)
A project of suitable complexity, comprising of program design, coding, compilation and debug
must be completed in approximately 30 hours.
REFERENCE BOOKS
1. Cracking the code Programming for embedded systems by Dreamtech Software Team.
2. Embedded Linux: Hardware, Software, and Interfacing by Craig Hollabaugh.
3. Embedded Linux system design and development by P.Raghavan, Amol Lad,
SriramNeelakandan.
4. Embedded Linux by John Lombardo.
5. Linux Device Drivers, 3rd Edition by Greg Kroah-Hartman.
6. Understanding the Linux Kernel, Third Edition by Daniel P. Bovet.
7. Linux for Embedded and Real-time Applications, Third Edition (Embedded Technology) by
Doug Abbott.
8. ARM System Developer's Guide: Designing and Optimizing System Software Design) by
Andrew Sloss.
3EC216 Verification Techniques

Teaching Scheme
Lect
Tuto.
Pract
Credit
Total
Theory
Examination Scheme
Theory
Tut.
&
Pra
Total
Practical
Total
Int.
Ass.
Ext.
Ass.
Total
Grand
Total
100
25
25
50
150
Sem End
Int.
Assess
Marks
Hrs
40
60
COURSE GOALS AND OBJECTIVES:

Overview of ASIC verification in complete ASIC flow including covering,
1. Overview of digital systems, simulation of systems, view on HDLs,
2. What is verification?
3. Importance of Verification
4. Types of verification
1.
Advanced Verification using Verilog :

Overview of Verilog, Verilog for Verification, Tasks and function
Delay, race condition, File I/O operation, TB Construct, Sample self-checking TB
2.
Way of Functional Verification(HDL and HVL) :

Use and importance of OOP concepts, OOP Basics, Classes, objects-handles,Polymorphism,
Inheritance, examples
3. Introduction to System Verilog:

New data types,Tasks and functions, interface, Clocking blocks
Threads and virtual interfaces: fork_join_xxx,event control, mailbox,semaphore, virtual
interface,transactorsCallbacks:Class, building reusable transactors, inserting callbacks,
registering callbacksDPI, Functional Coverage:Coverage model, cover-points,cross coverage,
regression testing.
4. Advance Verification:
Environment configuration, Reference model, predictor logic, scenario generation, test cases:
random, directed and corner cases.
4.1 Verification Methodology: What is methodology, benefits, reusability, Overview of OVM,
VMM, UVM.
4.2 Introduction to VMM: VMM layered architecture, messages, utilities, VMM env, Atomic
and scenario generators, VMM Channel, Callbacks, test cases, VMM tutorial.
4.3 Introduction to UVM: UVM architecture, report utilities, OVM transaction, sequences,
configuration.
5. Verification Planning and Management:

Verification plan, Test bench architecture, Coverage model, tracking simulation process,
Building regression suite, test suite optimization, Verification IP, Components of BFM and its
architecture, Coding style of VIP, Modelling and example view
6. Types of Verification:
Formal Verification: introduction to formal verification, degrees of abstraction, formal activity
(equivalence check, static property, semi-formal), Formal verification technologies (Binary
decision, symbolic model etc.), Advantage and limitation of Formal verification, bugs v/s
correctness
7. Testability and Design-For-Test:
What is design for testability, challenges of DFT, Testability requirement, types of faults, fault
models, methods, test pattern generation(TPG), Types of TPG, Scan, Boundary test, ATE and
coverage.
8. Pilot Project: Theory (Lab will cover exercise):
Overview of DUT/Block/SoC, Project specification analysis(Reading specs), defining
verification plan, Creating test bench architecture,Implementingtransactors, generators, driver,
receiver, scoreboard,Implementing coverage model,Building top level environment,Defining
directed, random, weighted random test cases,Building regression suite, generating functional
coverage and code coverage reports.
LABORATORY WORKS
1. Working on various exercise for System Verilog and UVM
2. Designing a project using entire VIP creation.
REFERENCE BOOKS
1. J. Bergeron, E. Cerny, A. Hunter and A. Nightingale, VerificationMethodology Manual for
SystemVerilog, Springer, 2005.
2. J. Bergeron, Writing Testbenches using SystemVerilog, Springer, 2006.
3. H.D. Foster, A.C. Krolnik and D.J. Lacey, Assertion-Based Design, Springer, 2004.
4. J.M. Lee, Verilog Quickstart - A Practical Guide to Simulation and Synthesis in Verilog,
Springer, 2005.
5. C. Spear, SystemVerilog for Verification- A Guide to Learning the Testbench Language
Features, Springer, 2006.
6. S. Sutherland, S. Davidmann and P. Flake, SystemVerilog for Design - A Guide to Using
SystemVerilog for Hardware Design and Modeling, Springer, 2006.
7. S. Sutherland and D. Mills, Verilog and SystemVerilog Gotchas - 101 Common Coding
Errors and How to Avoid Them, Springer, 2007.
8. S. Vijayaraghavan and M. Ramanathan, A Practical Guide for System Verilog Assertions,
Springer, 2005.
3EC217 Network Programming

Teaching Scheme
Lect
Tuto.
Pract
Credit
Total
Theory
Examination Scheme
Theory
Tut.
&
Pra
Total
Practical
Total
Int.
Ass.
Ext.
Ass.
Total
GrandTo
tal
100
25
25
50
150
Sem End
Int.
Ass
Marks
Hrs
40
60
COURSE GOALS AND OBJECTIVES:

1. Networking & Hardware Basics:
Introduction to router, switch, interface, Ethernet interface, IP routing/forwarding/ARP, Layer 2
switching/VLAN basics, Basics of TCP/IP, Basics of Wireshark.
2. Network Programming:
Basics on Parallel Programming, Basic on Network Programming & Socket Programming
Fork and Join, MultiThreading, Client Server Programming,Wireshark usage to see the packets
working, Semaphore and Mutex with Shared Memory and Critical section, Optimization of
Programming for resources.
3. Accessing Hardware using C:
Accessing hardware with pointers, Manipulating information at the bit level, General Purpose
IO(GPIO), Functions, The Function as a logical program unit, How parameters are passed
Memory segments, Arrays, Pointers and Strings, Arrays as circular buffers, Relationship
between pointers & arrays, Pointer arithmetic, C string handling, Device Interaction &
Synchronization, Polling devices, Serial peripheral programming, Structures and Unions
4. Real Time linux:
Measuring real-time behavior, The characteristics of a realtime task, Different ways of
instrumenting code.
5. Features in the Linux kernel for measuring delays and variability:
What happens in overload conditions (when the schedule cannot be met), Scheduling, processes
and threads,Review the difference between process and threads in Linux
6. Scheduling policies and priorities for Real time and Non-Real time tasks:
Periodic tasks,Assigning priorities using rate monotonic analysis
7. Synchronization between threads:

Description of the various mutex types Linux has to offer and when to use each one, The
problem of priority inversion and priority, Inheritance mutexes, Timers and periodic tasks, A
look at theaccuracy of timers, Configuring high resolution timers
8. Using POSIX timers:

Creating reliable periodic tasks, Interrupts and kernel,Preemption
9. Description of the interrupt model and factors that cause interrupt jitter:
How kernel pre-emption helps, The problem with kernel spin locks. PREEMPT_RT: The Real
Time Linux Kernel, Analysis of non-preemptive sections in Linux (atomic contexts),
Descriptionof PREEMTP_RT real time Linux patch and how it resolves the problem.
REFERENCES BOOKS
1. Unix Network Programming: The Sockets Networking Api - Volume 1 ;Stevens W.
Richard, Fenner Bill, Rudoff M. Andrew.
2. Unix Network Programming: Interprocess Communications (Volume - 2) 2nd Edition;
Stevens W. Richard.
3EC218 Embedded System Design & Architecture

Teaching Scheme
Lect
Tuto.
Pract
Credit
Total
Theory
Examination Scheme
Theory
Tut.
&
Pra
Total
Practical
Total
Int.
Ass.
Ext.
Ass.
Total
Grand
Total
100
25
25
50
150
Sem End
Int.
Ass.
Marks
Hrs
40
60

The study of embedded systems architecture, hardware-software abstraction, resource
allocation, software stacks, application planning and development.
In the process of the laboratory work it is necessary to use and study standard and emerging
development kit platforms for application development. A project of reasonable complexity
must be completed on an embedded system platform. The focus of the course is not on
lecture, but a study of a real system and application development using its resources.
COURSE CONTENTS
1. Introduction(3 hours) :
Embedded System Architecture fundamentals.Hardware and Software abstraction
models.Types of embedded systems.
2. Embedded System platforms and components (21 hours) :
Use of development boards.Use of compilers, debuggers, tracers and prototype mechanisms.
Prototyping using Cypress PSoC kits
Application development components - sensors, control and status components, data
acquisition methods and components. Data formats raw, processed and encrypted.
3. Architectural constraints and optimization (6 hours):
Use of minimal resources.Throughput, latency, energy and memory optimization.
4. Application classes and segments (10 hours):
Industrial, Automotive, mobile, set top box, appliances, weaponssystems.
LABORATORY WORKS(25 hours)
Tools used during laboratory works: Keil, Cypress PSoC, Actel, Altera, Xilinx boards
1. Study and implementation of compilers and debuggers (5 hours).
2. Study and implementation of applications on various platforms (15 hours).
COURSE PROJECT
A project of suitable complexity, comprising of program design, coding, compilation and
debug must be completed in approximately 35 hours.
REFERENCES BOOKS
1.
2.
3.
4.
Product documentation from ARM (KEIL), Cypress, Altera, Actel.

Bus Specifications PCI, PCIe, SCSI, IDE, USB, 802.11x, SATA.
Standards specifications JPEG, MPEG etc. as required by project.
Instructors may recommend additional textbooks or reference material the subject content
is rapidly changing and an up to date text book at the time of the class may be
recommended.
3EC219 Hardware Board Designing with PCB Designing

Teaching Scheme
Lect
Tuto.
Pract
Credit
Total
Theory
Examination Scheme
Theory
Tut.
&
Pra
Total
Practical
Total
Int.
Ass.
Ext.
Ass.
Total
Grand
Total
100
25
25
50
150
Sem End
Int.
Ass
Marks
Hrs
40
60
COURSE CONTENT
1. Fundamentals of electronics with importance
a) Properties and types of Resistors, Capacitors, Inductors and crystals
b) Properties and types of active components
c) Linear Circuits
d) Digital Circuits
e) Understanding behavior of real components
2. Introduction of Hardware design and Embedded Product
a) Process
b) Flow of designing a product
c) Steps
d) Responsibilities
e) Outcomes
3. Product Architecture & Specifications. Major Component selection
a) Product Definition to Schematic Design Process
4. Board Designing Overview and Basics
a) Process Flow
b) Steps
c) Tools used
d) Fundamental Requirements
5. Interpreting Datasheets and How to select components in Board Design flow from
B.O.M perspective
a) Understanding the online Support for selecting components
b) Discrete component datasheets
c) Specifications
d) Interpretation
e) Examples
f) Exercise
6. Programmable Logic
a) PLA,PAL,CPLD,FPGA
7. Basic Information on different protocols.(UART,Ethernet,USB, HDMI,LCD,I2C,SPI,

SATA)
a) Background, Architecture, Mechanical and Electrical Characteristics of all
mentioned topics.
8. LT Spice Tool-Simulation of the circuit
a) Features
b) Circuit Design and Parameters
c) Examples
d) Exercise
9. Cadence OrCAD Features and Tool flow in Schematic design methodology
a) Features
b) Library Creations
c) BOM(Bill of Material)
d) DRC(Design Rule Check)
e) Annotate
f) Examples
g) Exercise
10. Cadstar Tool-Layout Design
a) Pad Design
b) Package Design
c) Placement and routing
d) Board Design
e) Examples, Exercise
11. Allegro Layout viewer Tool Features and Layout Consideration
a) Features
b) LayersMeasure
c) Visiblity
d) Status
e) Ret nets and Routing
f) Layout Guidelines
g) Examples
12. Fabrication Facts DFM,DFT
a) Terms and Definitions
b) DFM + DFT
c) Files and checklist
d) Relative Package and Files
13. Power supply design and Do's / Don'ts with practical approach
a) Types of Power supply & its importance
b) Importance of each components
c) Example and Design own power supply
14. High Speed Design Basic

a) High-speed design fundamentals
b) Mutual inductance and mutual capacitance
c) High speed properties of logic gates
d) Measurement techniques of high speed signals using Oscilloscope
e) Cross talk in measurement of high speed signals
15. Basic Board Bring up and Testing overview with soldering fundamentals.
a) Including Practical overview with HW if possible
16. Oscilloscope Fundamentals
a) Basic Oscilloscope fundamentals
b) Types of Oscilloscopes
c) Comparison between Analog and Digital Oscilloscope
d) Probe Tips
17. Basics of Transmission line
a) Fundamentals
b) Parameters
c) Types of terminators
d) Series and Parallel Termination
e) Terminator resistor selection and cross-talk
f) Features of Digital Oscilloscope
18. Emulation
a) Significance of Emulation
b) Different approaches to Emulation
c) Difference between Prototyping and Emulation
d) Emulation methodology Planning, Execution, Debugging
19. Electro Static Discharge - Basics
a) Problem, Prevention and Control
b) EMI
c) EMC
d)
20. Revise Complete Training with Embedded Product Design Overview and Link each
Training session Bonus = Interview Tips
a) All Modules
21. Prepare a project related to HW design
REFERENCES BOOKS
1.
Complete PCB Design Using OrCad Capture and Layout by Kraig MitznerPublisher Newnes .
3EC220 Advanced VLSI Design

Teaching Scheme
Lect
Tuto.
Pract
Credit
Total
Theory
Examination Scheme
Theory
Tut.
&
Pra
Total
Practical
Total
Int.
Ass.
Ext.
Ass.
Total
Grand
Total
100
25
25
50
150
Sem End
Int.
Ass
Marks
Hrs
40
60
INTRODUCTION
Course program on Advanced VLSI Design is assigned for undergraduate and Post
Graduate education on VLSI Design specialization and is taught in the 5th semester (3
years 1st semester) for under graduates or Post Graduate 1st semester.
The course duration is 100 hours, lectures are 45-48 hours and laboratory/assignment/project
works are 52-55 hours.
The courseis to teach the future designers the basic principles of IC design, as well as to
promote an interest in life-long learning together with the ability to advance professionally.
The study of IC design basics, levels, strategies, options, methods, styles, challenges,
economics and trends especially front-end.
In the process of the laboratory work it is necessary to study the main IC design tools and to
implement in the simplest electronic circuits design. A project of reasonable complexity
must be completed.
COURSE CONTENTS
Concept of IC. IC structure, components, applications. History and evolution of the IC
industry.Moores Law.Performance (speed, power, function, flexibility). Die size (cost of
die). Design time(cost of engineering and schedule). Testability and ease of testing (cost of
engineering and schedule).Trade-off among the design parameters. The design trends and
perspectives of IC manufacturing (complexity, transistor count, die size, frequency, power
dissipation, power density). Technologyscaling.
2.
Levels of IC design - Recap (2 hours):

System level Design. Top down design.Bottom up design. Back end design. Design
abstraction levels. Behavior Level.Register-Transfer Level (RTL).Logic Level.Circuit
Level.Component level.Examples of Domains and its Abstraction Levels.
3.
Design Flow - Recap (2 hours):

Problem specification.Architecture definition. Simulate and compare-modify architecture
definition. Logic design. Simulate and compare-modify logic design. Circuit Design.
Simulate and compare-modify circuit design. Layout design. Extract simulate and comparemodify layout design. Fabrication.Ideal design flow: problem specification, compiling for
behavioral description, behavioral description, compiling for structural description,
structural description, compiling for physical description, physical description, fabrication.
Need for testing, manufacturing tests, design for test, chip-level test, system-level test.
More advanced design flow. IP based design. Hardware components.IP cores. IP cores
types. Reusability.Providers of IP cores.IP market. Platform based design. System on
chip(Soc). Generic Soc model.SoC platforms.Platform architecture. Platform based SoC
design.
4. Netlist to GDSII flow (36 hours):

Complete tapeout flow starting with functionally verified RTL. Synthesis and
optimization.Behavioral synthesis. Scan insertion and stitch. Placement, Routing, Clock tree
synthesis. Post route optimization. RC extraction and timing analysis. Design rule checks
and LVS. Signoff process.
5. Post Tapeout flow (2 hours):
Mask generation, OPC and fabrication process.
Tools used during laboratory works: DC Expert, DC Ultra, DFT Compiler, Physical
Compiler/ICC, Power Compiler, Star-RCXT, Hercules, PrimeTime.
1.
2.
3.
4.
5.
6.
Study and implementation of DC Expert tool (4 hours).

Study and implementation of DC Ultra tool (4 hours).
Study and implementation of Physical Compiler (or ICC) tool (6 hours).
Study and implementation of Power Compiler and DFT compiler tool (4 hours).
Study and implementation of Star-RCXT and Hercules tools (6 hours).
Study and implementation of PrimeTime tool (6 hours).
COURSE PROJECT
A project of suitable complexity, comprising of complete netlist to GDSII flow must be
completed in approximately 25 hours.

The course program is compiled taking into account that the following courses had been
studied beforehand:
Electrical Engineering
Physical Fundamentals of Microelectronics or Solid State Electronics Fundamentals
CS for EE students or familiarity with Linux, Perl, compilers.
educational plan of VLSI Design specialization.
REFERENCES BOOKS
1. J.P. Uyenmura. Introduction to VLSI Circuits and Systems, J.Wiley& Sons, 2002.
2. J.M. Rabaey, A. Chandrakasan, B. Nikolic. Digital Integrated Circuits - A Design Perspective,
Prentice Hall, 2003.
3. J.P. Uyenmura. Modern VLSI Design System-on-Chip Design, Prentice-Hall, 2002.
4. D.A. Pucknell and K. Eshraghian. Basic VLSI Design, Systems and Circuits, Prentice-Hall,
1994.
5. W. Wayne. Modern VLSI Design: A Systems Approach, Prentice-Hall, 1994.
6. K. Martin. Digital Integrated Circuit Design, Oxford University Press, 2000.
7. J.F. Wakerly. Digital Design - Principles & Practices, Prentice Hall, 2001.
3EC213 SYSTEM LEVEL DESIGN LAB

Teaching Scheme
Lect
Tuto.
Pract
Credit
Total
Theory
Examination Scheme
Theory
Tut.
&
Pra
Total
Practical
Total
Int.
Ass.
Ext.
Ass.
Total
Grand
Total
25
25
50
50
Sem End
Int.
Ass
Marks
Hrs
Students to create a system level design using any of the tools, languages and technology
available in the lab.
REFERENCES BOOKS
1. Uwe Meyer-Baese, Digital Signal Processingwith Field ProgrammableGate Arrays,
3rd Edition.
3EC214 Mini Project II

Teaching Scheme
Lect
Tuto.
Pract
Credit
Total
Theory
Examination Scheme
Theory
Tut.
&
Pra
Total
Practical
Total
Int.
Ass.
Ext.
Ass.
Total
Grand
Total
50
50
100
100
Sem End
Int.
Ass
Marks
Hrs
Students have to carry out the project under the guidance of faculty member using the knowledge of
subjects that he/she has learned in semester. Students have to submit project report withcode at the
end of the semester.
GANPAT UNIVERSITY
DETAILED SYLLABUS
FOR
3RD SEMESTER

Ganpat Vidyanagar,
Phone: +91-2762-286805, +91-2762-286082
Fax: +91-2762-286650
SEMESTER 3
Elective III
3EC311 Memory designs
Teaching Scheme
Lect
Tuto.
Pract
Credit
Total
Theory
Examination Scheme
Theory
Tut.
&
Pra
Total
Practical
Total
Int.
Ass.
Ext.
Ass.
Total
Grand
Total
100
25
25
50
150
Sem End
Int.
Ass.
Marks
Hrs
40
60

The study of IC standard cell elements, memory types, memory failures, memory and cell
Characterization and testing.
In the process of the laboratory work it is necessary to study the main IC design tools and
to implement electronic circuits in the form of standard cells and memories. A project of
reasonable complexity must be completed.
COURSE CONTENT
IC design flows. Use of standard cell elements vs. custom design and Gate array
paradigms. Introduction to memory types and construction of memory elements.
2. Standard cell library composition and usage (12 hours) :
Types of standard cell elements. Logical and functional elements, primitives and complex
macros. Sequential elements and register files. (Flip flop and latch design). Data path
elements. Library size vs. usage in standard flows. Drive strength and cell families.
Layout of library elements single height, double height cells. Power Management cells.
3. Standard cell characterization (9 hours) :
Usage of standard cells by various tools. Information needed at each stage of design flow.
Characterization parameters, setup and runs across PVT corners. Library representation
formats. (Gate level simulation, synthesis, timing, layout, timing, LVS, DRC)
4. Memory elements and array design (12 hours) :
Volatile and Non-volatile RAM, ROM, EPROM, Flash (EEPROM), OTP elements and
cell design. State retention volatile memories. Array design architecture,
bitline/wordline, optimization, sense-amps and mux/demux architecture. Memory
banking, refresh cycle management. Multi-port memories. Cache memories. Special
memories such as CAMs.
REFERENCES
1. Low Power and Reliable SRAM Memory Cell and Array Design,Springer,Ishibashi,
Koichiro, Osada, Kenichi (Eds.)
2. VLSI Memory Chip Design (Springer Series in Advanced Microelectronics), by
KiyooItoh
3. VLSI-Design of Non-Volatile Memories, springer, Campardo, Giovanni, Micheloni,
Rino, Novosel, David, 2005
3EC311 Wireless Sensors and Adhoc Networks

Teaching Scheme
Lect
Tuto.
Pract
Credit
Total
Theory
Examination Scheme
Theory
Tut.
&
Pra
Total
Int.
Ass.
40
Practical
Sem End
Marks
Hrs
60
Total
Int.
Ass.
Ext.
Ass.
100
25
25
Total
Grand
Total
50
150
COURSE CONTENT
1.
Module I
a) Introduction: Motivation for a Network of Wireless Sensor Nodes, Sensing and Sensors
Wireless Networks, Challenges and Constraints
b) Applications: Health care, Agriculture, Traffic and others
2.
Module II
a) Architectures: Node Architecture; the sensing subsystem, processor subsystem,
communication interface, LMote, XYZ, Hogthrob node architectures
b) Power Management - Through local power, processor, communication subsystems and
other means, time Synchronization need, challenges and solutions overview for ranging
techniques.
c) Security Fundamentals, challenges and attacks of Network Security, protocol
mechanisms for security.
3.
Module III
a) Operating Systems: Functional and non-functional aspects, short overview of
prototypes Tiny OS, SOS, Contiki, LiteOS, sensor grid.
4.
Module IV
a) Physical Layer- Basic Components, Source Encoding, Channel Encoding, Modulation,
Signal Propagation
b) Medium Access Control types, protocols, standards and characteristics, challenges
c) Network Layer -Routing Metrics, different routing techniques
REFERENCES BOOKS
1. Dargie, W. and Poellabauer, C., "Fundamentals of wireless sensor networks: theory
and practice", John Wiley and Sons, 2010
2. Sohraby, K., Minoli, D., Znati, T. "Wireless sensor networks: technology, protocols,
and applications, John Wiley and Sons", 2007
3. Hart, J. K. and Martinez, K. (2006) Environmental Sensor Networks: A revolution in
the earth system science? Earth-Science Reviews, 78.
4. Protocols and Architectures for Wireless Sensor Networks Holger Karl, Andreas
Willig - 08-Oct-2007
3EC311 Image Processing

Teaching Scheme
Lect
Tuto.
Pract
Credit
Total
Theory
Examination Scheme
Theory
Tut.
&
Pra
Total
Practical
Total
Int.
Ass.
Ext.
Ass.
Total
Grand
Total
100
25
25
50
150
Sem End
Int.
Ass.
Marks
Hrs
40
60

The study of Image processing principles and implementation in an IC or System.
In the process of the laboratory work it is necessary to study the main Image
processing standards, platforms and to implement algorithms either in an IC design or
embedded system design. A project of reasonable complexity must be completed.
COURSE CONTENT
1. Fundamentals of Image Processing and Image Transforms
Basic steps of Image Processing System Sampling and Quantization of an image
Basic relationship between pixels Image Transforms: 2 D- Discrete Fourier Transform,
Discrete Cosine Transform Wavelet Transforms: Continuous Wavelet Transform,
Discrete Wavelet Transforms.
2. Image Processing Techniques
Image Enhancement. Spatial domain methods: Histogram processing, Fundamentals of
Spatial filtering, Smoothing spatial filters, Sharpening spatial filters. Frequency domain
methods: Basics of filtering in frequency domain, image smoothing, image sharpening,
Selective filtering. Image Segmentation Segmentation concepts, Point, Line and Edge
Detection, Thresholding, Region Based segmentation.
3. Image Compression
Image compression fundamentals - Coding Redundancy, Spatial and Temporal
redundancy, Compression models: Lossy& Lossless, Huffman coding, Arithmetic
coding, LZW coding, Run length coding, Bit plane coding, Transform coding,
Predictive coding, Wavelet coding JPEG Standards.
4. Basic steps of Video Processing
Analog Video, Digital Video. Time-Varying Image Formation models: ThreeDimensional Motion Models, Geometric Image Formation, Photometric Image
Formation, Sampling of Video signals, Filtering operations.
5. 2-D Motion Estimation
Optical flow, General Methodologies, Pixel Based Motion Estimation, Block- Matching
Algorithm, Mesh based Motion Estimation, Global Motion Estimation, Region based
Motion Estimation, Multi resolution motion estimation, Waveform based coding, Block
based transform coding, Predictive coding, Application of motion estimation in Video
coding.
6. Commercial image acquisition and projection systems

Study of OMAP, DLP, CCD and other devices in the market. 3-D TV and other
emerging applications.
LABORATORY WORKS(25 HOURS)
Tools used during laboratory works: VCS, Design Compiler, ICC, Primetime,
Prime Power, Matlab, TI or other Laboratory kits, gcc, gdb.
Study and implementation of various algorithms and transforms (30 hours)
(The implementation may be done either in VLSI domain or embedded systems
domain. Student must choose a platform on which standard algorithms and transforms
can be executed.)
COURSE PROJECT (33 Hours)
A project of reasonable complexity must be completed it must build an
implementation of an Image processing algorithm in RTL and demonstrate its
implemented form in Post Layout Netlist or demonstrate an application on an
embedded systems platform (from TI, Freescale, ARM or others).
REFERENCES
1.
2.
3.
4.
TI documentation on DSP/OMAP platforms.

Documentation manuals on DLP, 3-D TV and other projection systems
Digital Image Processing Gonzaleze and Woods, 3rd ed., Pearson.
Video processing and communication Yao Wang, JoemOstermann and Yaquin
Zhang. 1st Ed., PH Int.
3EC311 Advance Digital Communication System

Teaching Scheme
Lect
Tuto.
Pract
Credit
Total
Theory
Examination Scheme
Theory
Tut.
&
Pra
Total
Practical
Total
Int.
Ass.
Ext.
Ass.
Total
Grand
Total
100
25
25
50
150
Sem End
Int.
Ass.
Marks
Hrs
40
60
COURSE CONTENT
The focus is on coding techniques for approaching the Shannon limit of additive
white Gaussian noise (AWGN) channels, their performance analysis, and design
principles. After a review of 6.450 and the Shannon limit for AWGN channels, the
course begins by discussing small signal constellations, performance analysis and
coding gain, and hard-decision and soft-decision decoding. It continues with binary
linear block codes, Reed-Muller codes, finite fields, Reed-Solomon and BCH codes,
binary linear convolutional codes, and the Viterbi algorithm.
More advanced topics include trellis representations of binary linear block codes and
trellis-based decoding; codes on graphs; the sum-product and min-sum algorithms; the
BCJR algorithm; turbo codes, LDPC codes and RA codes; and performance of LDPC
codes with iterative decoding. Finally, the course addresses coding for the bandwidthlimited regime, including lattice codes, trellis-coded modulation, multilevel coding
and shaping. If time permits, it covers equalization of linear Gaussian channels.
Digital communications at the block diagram level, data compression, Lempel-Ziv
algorithm, scalar and vector quantization, sampling and aliasing, the Nyquist criterion,
PAM and QAM modulation, signal constellations, finite-energy waveform spaces,
detection, and modeling and system design for wireless communication.
We expect to introduce the following topics during the term.
Wireless Channel Models, Noise and Interference

Capacity and Outage
Diversity and Space-Time Coding
Diversity-Multiplexing Tradeoffs
Wireless Networks and Resource Management
Advanced Topics
REFERENCES BOOKS
1. Wireless communications, principles and practices By Theodor S. Rappaport (Pearson
Edition).
2. Wireless Digital Communications By Dr. KamiloFeher, (PHI).
3. Error Control Codes by Todd K. Moon
4. Mobile cellular Telecommunication analog and digital systems By William C. Y. Lee
(McGraw-Hill).
5. Mobile Cellular Telecommunication By William C. Y. Lee (McGraw Hill).
3EC311 Android and iPhone Stack

Teaching Scheme
Lect
Tuto.
Pract
Credit
Total
Theory
Examination Scheme
Theory
Tut.
&
Pra
Total
Practical
Total
Int.
Ass.
Ext.
Ass.
Total
Grand
Total
100
25
25
50
150
Sem End
Int.
Ass.
Marks
Hrs
40
60
COURSE CONTENTS
1.
Android
a. OOPs with Java
1. Class
2. Objects
3. Inheritance & Polymorphism
4. Using Widgets / Event Handlers/Callback Functions
5. TryCatch block
6. Java Native Interface
b. Android
1. Booting of Android device
2. Android Architecture
3. Android Application Components
4. Database Handling
5. Content Providers
6. Designing a remote interface using AIDL
7. Android Debug Bridge and Logcat
8. 2D Graphics and 3D Animation using OpenGL
9. Audio API's
10. Video APIs
11. Deploying application to a target device
12. JNI Interfacing
13. Adding Services in the Android Framework
14. Ethernet / USB - Mouse,Keyboard / Wireless - Wi-Fi , Bluetooth / LCD touch
15. Audio Subsystem
16. Video Subsystem
17. Optimization
c. Implementation on Hardware (Panda board / Beagle board - XM)
1. Reading Datasheet of Hardware
2. Booting Panda board
3. Formatting SD card
4. MLO(TI Primary boot loader)
5. Uboot(Secondary boot loader)
6. UImage (Kernel Image)
7. Root File system creation
8. Boot Process of Panda board

9. Cross Compilation for ARM
10. Loading Hello Module
11. Implementing UART Driver or Network Driver
d.
Installation of Android on Panda board
2.
iPhone
1. MVC and Intro to Objective-C
2. My First iOS Application
3. Objective C
4. Views
5. Protocols and Gestures
6. Multiple MVCs and Segues
7. Controller Lifecycle &Image/Scroll/Webviews
8. Table Views
9. Blocks and Multithreading
10. Action Sheets, Image picker, Core Motion
11. Working with iOS
12. Porting iOS on handheld device
13. Project Design a iOS application
REFERENCES BOOKS
1. Marko Gargenta, Learning Android, OReilly.
2. Alasdair Allan, Learning iOS Programming, 3rd Edition: From Xcode to App Store,
OReilly Media.
3EC311 Systems Security

Teaching Scheme
Lect
Tuto.
Pract
Credit
Total
Theory
Examination Scheme
Theory
Tut.
&
Pra
Total
Practical
Total
Int.
Ass.
Ext.
Ass.
Total
Grand
Total
100
25
25
50
150
Sem End
Int.
Ass.
Marks
Hrs
40
60
INTRODUCTION
System Security is a post-graduate, second year graduate course on network and
computer security.
COURSE CONTENT
1. Topics covered include (but are not limited to) the following:
a. Techniques for achieving security in multi-user computer systems and distributed
computer systems;
b. Cryptography: secret-key, public-key, digital signatures;
c. Authentication and identification schemes;
d. Intrusion detection: viruses;
e. Formal models of computer security;
f. Secure operating systems;
g. Software protection;
h. Security of electronic mail and the World Wide Web;
i. Electronic commerce: payment protocols, electronic cash;
j. Firewalls; and
k. Risk assessment.
REFERENCES
1. Saltzer & Kaashoek, Principles of Computer System Design: An Introduction
3EC311 Multicore Architecture & Designing of Processors

Teaching Scheme
Lect
Tuto.
Pract
Credit
Total
Theory
Examination Scheme
Theory
Tut.
&
Pra
Total
Practical
Total
Int.
Ass.
Ext.
Ass.
Total
Grand
Total
100
25
25
50
150
Sem End
Int.
Ass.
Marks
Hrs
40
60
COURSE CONTENT
1. Introduction:
a. Amdahls law
b. Short vector processing (multimedia operations)
c. Multicore and multithreaded processors
d. Flynns taxonomy: Multiprocessor structures and architectures
e. Programming multiprocessor systems
f. GPU and special-purpose graphics processors
g. Introduction to reconfigurable logic and special-purpose processors
2. Introduction to multi-core architecture: Parallel computing and why it failed.
Multi-processor architecture and its limitations. Need for multi-core architectures 4
one-hour lectures
3. Multi-core architecture: Architecting with multi-cores. Homogenous and
heterogeneous cores. Shared recourses, shared busses, and optimal resource sharing
strategies. Performance evaluation of multi-core processors. Error management 12
one-hour lectures
4. Intel Multi-core architecture: Detailed study of the architecture and programming
of the Intel processors. 12 one-hour lectures
5. Benchmarking multi-core architecture: Bench marking of processors. Comparison
of processor performance for specific application domains. 4 one-hour lectures
6. Code optimization: Need for code optimization. Tools for code optimization and
optimization strategies 4 one-hour lectures. The lab part will consist of 14 three-hour
sessions and will include basic programming exercises and a mini-project.
REFERENCES BOOKS
1. http://software.intel.com/en-us/courseware-multiprocessing
3EC311 Low Power Design

Teaching Scheme
Lect
Tuto.
Pract
Credit
Total
Theory
Examination Scheme
Theory
Tut.
&
Pra
Total
Practical
Total
Int.
Ass.
Ext.
Ass.
Total
Grand
Total
100
25
25
50
150
Sem End
Int.
Ass.
Marks
Hrs
40
60
INTRODUCTION
Course program on Low Power Design is assigned for postgraduate education on
VLSI Design specialization and is taught in the 4th semester (2 years 2nd
semester).The course duration is 104 hours, lectures volume is 52 hours, practice
classes are 26 hours, and laboratory works are 26 hours.
The goal of the course is to teach the future researchers the principles of design,
analysis, modeling and optimization of low power VLSI, as well as to promote an
interest in life-long learning together with the ability to advance professionally.
The study of CMOS low power IC design, modeling and optimization basics.
In the process of the practice classes and laboratory work it is necessary to study the
approaches for power consumption estimation and different methods of reduction of
switching and leakage power.
COURSE CONTENTS
IC Power consumption concerns. Limits of Power in Microelectronics. Low-power
design methodologies.
2. Power Consumption in CMOS Digital Designs (8 hours):
Switching component of power. Switching energy per transition. Conventional
CMOS circuits with rail-to-rail swing. Charge sharing. Components of node
capacitance. Definition of transition activity factor. Influence of logic level statistic
and circuit topologies on the node transition activity factor. Word level signal
statistics influencing activity. Influence of voltage scaling. Short-circuit component of
power. Leakage component of power. Diode Leakage. Sub-threshold leakage. Static
Power. Reduced voltage levels feeding CMOS gates. Pseudo-NMOS logic style.
3. Voltage Scaling Approaches (10 hours):

Reliability-driven voltage scaling. Technology-driven voltage scaling.
Energy x delay minimum based voltage scaling. Voltage scaling through optimal
transistor sizing. Voltage scaling usingthreshold reduction. Architecture-driven
voltage scaling. Trading area for lower power through hardware duplication. Optimal
supply voltage for architecture driven voltage scaling. Trading area for lower power
through hardware pipelining. Noise Considerations at reduced supply voltage. Digital
design with multiple supplies.
4. Adiabatic Switching (6 hours):
Adiabatic charging. Adiabatic amplification. One-stage adiabatic buffer in
conventional system. Two-stage adiabatic buffer in conventional system. Fullyadiabatic system. Comparison with conventional buffer. Supply voltage influence.
Adiabatic logic gates. Fully-adiabatic sequential circuits. Partially-adiabatic
sequential circuits. Stepwise charging. Pulsed-power supplies.
5. Minimizing Switched Capacitance (switching activity) (10 hours):
Algorithmic optimization. Minimizing the number of operations. Minimizing
temporal bit transition activity by choice of data representation. Architecture
optimization. Optimizing data representation for arithmetic computation. Ordering of
input signals. Reducing glitching activity. Degree of resource sharing. Logic
optimization. Logic minimization and technology mapping. Activity trade-off for
various logic structures. Logic level power down. Clock gating. Circuits optimization.
Dynamic logic vs. static logic. Pass transistor logic vs. conventional CMOS logic.
Synchronous vs. asynchronous. Physical Design. Layout optimization. Place and
route.
6. Leakage Power Reduction (6 hours):
Leakage current in deep submicron ICs. Gate oxide tunneling. Supply power control.
Bulk-source biasing. Bias voltage generator. Logic gate optimization for leakage
power. Input vector selection for standby mode.
7. Low Power Design for DSP applications (8 hours):
Power Estimation. High-level transformations. Application of transformations to
minimize power. Speed-up transformations. Operation reduction. Operation
substitution. Resource Utilization. Word length reduction. Cost function. Capacitance
estimate. Supply voltage estimation. Optimization algorithms. Examples: Wavelet
filter; IIR filter; Volterra filter.
LABORATRY WORKS (26 hours)
1.
2.
3.
4.
5.
6.
Node Transition activity analysis in logic networks (2 hours).

Estimation of short circuit power in CMOS gates (2 hours).
Energy x Delay minimization by voltage scaling (2 hours).
Switching power calculation in CMOS networks (2 hours).
Analysis of adiabatic charging (2 hours).
Analysis of methods of bit transition activity minimization by choice of data
representation (2 hours).
7. Analysis of switching capacitance reduction by operation

andsubstitution inDSP systems (4 hours).
8. Analysis of clock gating CMOS cells (2 hours).
9. Input vector selection for leakage current reduction (2 hours).
10. FIR filters optimization for low power (4 hours).
reordering
COURSE PROJECT
Tools used during laboratory works: Hspice, Nanosim, Power Compiler, PrimePower,
DC, Physical Compiler.
1. Exploration of leakage power component in CMOS logic gates (4 hours).
2. Study of clock gating cells (4 hours).
3. Exploration of leakage power reduction by bulk-source biasing (4 hours).
4. Exploration of switching power in pipelined structures (4 hours).
5. Exploration power vs. performance vs. area in digital IP design (6 hours).
6. Study of adiabatic logic gates (4 hours).
been studied beforehand:
Semiconductor Devices Semiconductor Technology IC Design
Introduction Digital Integrated Circuits Analog Integrated Circuits IC
Fabrication VLSI Design
Understanding of the course is the basis for the further specialized subjects
destined by the educational plan of VLSI Design specialization.
REFERENCES BOOKS
1. K.S. Yeo, S.S. Rofail, W.L. Goh. CMOS/BiCMOS VLSI: Low Voltage, Low
Power. -Prentice Hall, 2002.
2. K. Roy. Low-Power CMOS VLSI Circuit Design. - John Wiley & Sons Inc, 2003.
-320p.
3. A.P. Chandraksan, R.W. Brodersen. Low Power Digital CMOS Design. Kluwer
Academics,1996. -409p.
4. Y.G. Practical. Low-Power Digital VLSI Design. - Kluwer Academics, 1998. 388p.
3EC311 Advanced Mixed Signal IC Design

Teaching Scheme
Lect
Tuto.
Pract
Credit
Total
Theory
Examination Scheme
Theory
Tut.
&
Pra
Total
Practical
Total
Int.
Ass.
Ext.
Ass.
Total
Grand
Total
100
25
25
50
150
Sem End
Int.
Ass.
Marks
Hrs
40
60
Course program on Advanced Mixed Signal IC design is assigned for postgraduate

education on VLSI Design specialization and is taught in the 1st and 2nd semesters (1
years 1st and 2nd semesters). The course duration is 85 hours, lectures volume is 51
hours, laboratory works are 34 hours, and course work (1 years 1st semester).
The goal of the course is to teach the peculiarities, principles and methods of
contemporary Mixed Signal IC design and analysis to the future designers of
microelectronic circuits and systems.
The study of different types of Mixed Signal ICs and their design procedures with
methods applied in different stages of design. The understanding of the course will help
students to apply their knowledge in practice. In the process of the laboratory work it is
necessary to study the problems related to design of various Mixed Signal ICs.
COURSE CONTENTS
1. Introduction to Mixed signal Circuit Design: Challenges and opportunities, need for
mixed signal circuits and systems, software tools, industry trends.
2. Switched Capacitor Circuits Design: Introduction, general consideration, sampling
switches - speed and precision consideration, switched capacitor amplifiers, switched
capacitor integrators and switched capacitor filters.
3. Memory design : Introduction, need for memories, classification of memories,
Dynamic Random Access Memory (DRAM) and Static Random Access Memory
(SRAM), memory architectures, 6T SRAM memory cell architecture, peripheral
memory circuitry - sense amplifier, read/write circuitry, bit line pre-charge circuitry,
row and column decoders and memory timing.
4. Data converters Fundamental: Introduction, basic building blocks, analog versus
discrete time signal, sample and hold characteristics, DAC & ADC specificationsDifferential Non Linearity (DNL), Integral Non Linearity (INL),Offset error, gain
error, latency, dynamic range, Signal to Noise Ratio (SNR), Spurious Free Dynamic
Range (SFDR) and Effective Number of Bits (ENOB).
5. DAC Design: Introduction, transistor level design of sub circuits for ADCs and
architecture level design of resistor string DAC, mismatch errors related to the
resistor string DAC, R-2R DAC- current mode, Voltage mode, current steering
DAC, mismatch errors related to the current steering DAC, charge scaling DACs,
cyclic DAC and pipeline DAC.
6. ADC Design: Introduction, transistor level design of sub circuits for ADCs and
architecture level design of Flash ADC, two steps flash ADC, pipeline ADC,
integrated ADC, accuracy issues, successive approximation ADC and over sampling
ADC.
7. Phase Locked Loop (PLL) Design: Introduction, building blocks, Phase Frequency
Detector (PFD), charge pump, Voltage Controlled Oscillators (VCO), loop filter.
Non ideal effects in PLL, frequency multiplication and synthesis
8. RF Circuit: Introduction, building blocks, why RF circuit, applications.
9. Layout introduction: Introduction, MOS transistor layers, stick diagram, symbolic
diagram, design rules-lambda and micron rules 180nm, 90nm, 65nm, 45nm. MOS
transistor layout and physical verification, types full custom layout - data path
layout, custom digital layout, cell layout and analog layout.
10. Digital layout design: Introduction, guide line of transistor layout, PMOS and NMOS
transistor layout, CMOS transistor layout, sharing diffusion methods, layout
optimization using dual graph methods and Eulers path. Combinational and
sequential circuit layout
11. Analog MOS circuits: Introduction, MOS transistor analog model, current mirrors
simple, cascode/Cascade, Wilson and widlar. Single stage amplifier common
source amplifier, common drain amplifier and common gate amplifier. Differential
amplifier and two stages MOS operational amplifiers, cascade and folded cascade
operational amplifiers.
12. Analog layout design, mixed signal layout issues: Introduction, analog layout
techniques and Passive component layout - capacitor, resistor and inductor. Floor
planning of analog and digital components, power supply and ground pin issues,
matching, shielding, interconnection issues.
LABORATRY WORKS (34 hours)
Tools used during laboratory works: LT-Spice, H-Spice, Electric-CAD, ASLK.
1. Implementation of Op-Amps, Transconductanceckts, current mirror ckts, filters
usingLT-spice and ASLK.
2. Implementation of ADCs, DACs, PLL, VCO, filters, Op-Amps, memories using
ASLK.
3. Designing/Optimizationlayout of analog ckts using Electric-CAD.
COURSE WORK
The themes for Course Work, intended 1st year 3rd semester, are related to mixed
signal circuit design. Each student should design and verify one mixed signal circuit.

been studied beforehand:
IC Design Introduction
Introduction to Circuits
Digital Integrated Circuits
Analog Integrated Circuits
RF Circuits and Systems
Semiconductor Technology
educational plan of VLSI Design specialization.
REFERENCES BOOKS
1. Behzad Razavi Design of Analog CMOS Integrated Circuits".
2. Jacob Baker CMOS Circuit Design, Layout and Simulation"
3. Gray Mayer Analog circuit Design"
3EC312 Quality Assurance and Reliability

Teaching Scheme
Lect
Tuto.
Pract
Credit
Total
Theory
Examination Scheme
Theory
Tut.
&
Pra
Total
Practical
Total
Int.
Ass.
Ext.
Ass.
Total
Grand
Total
70
15
15
30
100
Sem End
Int.
Ass.
Marks
Hrs
25
45
COURSE CONTENTS
1. Basic Concepts, Quality and Reliability Assurance of Complex Equipment & Systems
1.1 Introduction
1.2 Basic Concepts
1.2.1 Reliability
1.2.2 Failure
1.2.3 Failure Rate
1.2.4 Maintenance, Maintainability
1.2.5 Logistic Support
1.2.6 Availability
1.2.7 Safety, Risk, and Risk Acceptance
1.2.8 Quality
1.2.9 Cost and System Effectiveness
1.2.10 Product Liability
1.2.11 Historical Development
1.3 Basic Tasks & Rules for Quality & Reliability Assurance of Complex Equip. &
Systems.
1.3.1 Quality and Reliability Assurance Tasks
1.3.2 Basic Quality and Reliability Assurance Rules
1.3.3 Elements of a Quality Assurance System
1.3.4 Motivation and Training
2. Reliability Analysis During the Design Phase (Nonrepairable Items up to System
Failure).
2.1 Introduction
2.2 Predicted Reliability of Equipment and Systems with Simple Structure
2.2.1 Required Function
2.2.2 Reliability Block Diagram
2.2.3 Operating Conditions at Component Level, Stress Factors
2.2.4 Failure Rate of Electronic Components
2.2.5 Reliability of One-Item Structure
2.2.6 Reliability of Series-Parallel Structures
Systems without Redundancy
Concept of Redundancy
Parallel Models
Series - Parallel Structures
Majority Redundancy
2.2.7 Part Count Method

2.3 Reliability of Systems with Complex Structure
2.3.1 Key Item Method
Bridge Structure
Rel. Block Diagram in which Elements Appear More than Once
2.3.2 Successful Path Method
2.3.3 State Space Method
2.3.4 Boolean Function Method
2.3.5 Parallel Models with Constant Failure Rates and Load Sharing
2.3.6 Elements with more than one Failure Mechanism or one Failure Mode
2.3.7 Basic Considerations on Fault Tolerant Structures
2.4 Reliability Allocation
2.5 Mechanical Reliability, Drift Failures
2.6 Failure Mode Analysis
2.7 Reliability Aspects in Design Reviews
3. Qualification Tests for Components and Assemblies
3.1 Basic Selection Criteria for Electronic Components
3.1.1 Environment
3.1.2 Performance Parameters
3.1.3 Technology
3.1.4 Manufacturing Quality
3.1.5 Long-Term Behavior of Performance Parameters
3.1.6 Reliability
3.2 Qualification Tests for Complex Electronic Components
3.2.1 Electrical Test of Complex ICs
3.2.2 Characterization of Complex ICs
3.2.3 Environmental and Special Tests of Complex ICs
3.2.4 Reliability Tests
3.3 Failure Modes, Failure Mechanisms, and Failure Analysis of Electronic
Components
3.3.1 Failure Modes of Electronic Components
3.3.2 Failure Mechanisms of Electronic Components
3.3.3 Failure Analysis of Electronic Components
3.3.4 Examples of VLSI Production-Related Reliability Problems
3.4 Qualification Tests for Electronic Assemblies
4. Maintainability Analysis
4.1 Maintenance, Maintainability
4.2 Maintenance Concept
4.2.1 Fault Recognition and Isolation
4.2.2 Equipment and System Partitioning
4.2.3 User Documentation
4.2.4 Training of Operating and Maintenance Personnel
4.2.5 User Logistic Support
4.3 Maintainability Aspects in Design Reviews
4.4 Predicted Maintainability
4.4.1 Calculation of MTTRS
4.4.2 Calculation of MTTPMS
4.5 Basic Models for Spare Parts Provisioning

4.5.1 Centralized Logistic Support, Nonrepairable Spare Parts
4.5.2 Decentralized Logistic Support, Nonrepairable Spare Parts
4.5.3 Repairable Spare Parts
4.6 Repair strategies
4.7 Cost Considerations
5. Design Guidelines for Reliability, Maintainability, and Software Quality
5.1 Design Guidelines for Reliability
5.1.1 Derating
5.1.2 Cooling
5.1.3 Moisture
5.1.4 Electromagnetic Compatibility, ESD Protection
5.1.5 Components and Assemblies
Component Selection
Component Use
PCB and Assembly Design
PCB and Assembly Manufacturing
Storage and Transportation
5.1.6 Particular Guidelines for IC Design and Manufacturing
5.2 Design Guidelines for Maintainability
5.2.1 General Guidelines
5.2.2 Testability
5.2.3 Accessibility, Exchangeability
5.2.4 Operation, Adjustment
5.3 Design Guidelines for Software Quality
5.3.1 Guidelines for Software Defect Prevention
5.3.2 Configuration Management
5.3.3 Guidelines for Software Testing
5.3.4 Software Quality Growth Models
REFERENCES BOOKS
1. Alessandro Birolini, Reliability Engineering: Theory and Practice, 5th Edition
3EC313 Dissertation Part-I

Teaching Scheme
Lect
Tuto.
Pract
16
Credit
Total
16
Theory
Examination Scheme
Theory
Tut.
&
Pra
Total
Practical
Total
Int.
Ass.
Ext.
Ass.
Total
Grand
Total
100
100
200
200
Sem End
Int.
Ass.
Marks
Hrs
Each student is required to carry out elaborated project work. The project may be
design/analysis /implementation work or a simulation of a problem/system. At the end of the
semester student will be required to submit a detailed report of literature survey, design
problem formulation, analysis, functional simulation/results, work plan and work done before
examiners.
GANPAT UNIVERSITY
DETAILED SYLLABUS
FOR
4TH SEMESTER

Ganpat Vidyanagar,
Phone: +91-2762-286805, +91-2762-286082
Fax: +91-2762-286650
SEMESTER 4
3EC411 Dissertation Part-II
Teaching Scheme
Lect
Tuto.
Pract
24
Credit
Total
24
Theory
Examination Scheme
Theory
Tut.
&
Pra
Total
12
12
Practical
Total
Int.
Ass.
Ext.
Ass.
Total
Grand
Total
200
200
400
400
Sem End
Int.
Ass.
Marks
Hrs
Each student is required to carry out elaborated project work. The project may be
design/analysis /implementation work or a simulation of a problem/system. At the end of the
semester student will be required to submit a detailed report of literature survey, design
problem formulation, analysis, functional simulation/results, work plan and work done before
examiners.

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GANPAT UNIVERSITY

U.V.PATEL COLLEGE OF ENGINEERING

U.V.Patel College OF Engineering

Digital VLSI Design

Soft skills- Presentation, Attitude and Technical writing

M. TECH. (ELECTRONICS & COMMUNICATION) VLSI & Embedded Systems

RTOS, Kernels and device drivers

Embedded System Design & Architecture

Hardware Board Designing with PCB Designing

Advanced VLSI Design

M. TECH. (ELECTRONICS & COMMUNICATION) VLSI & Embedded Systems

M. TECH. (ELECTRONICS & COMMUNICATION) VLSI & Embedded Systems

U.V.Patel College OF Engineering

3EC112 Operating Systems

LABORATORY WORKS (35HOURS):

3EC114 Digital Signal Processing

5. Digital processing of continuous-time signals (4 hours):

LABORATORY WORKS (34HOURS):

1. Discrete-Time Signal Processing by A. V. Oppenheim and R. W. Schafer, EEE, 2nd

3EC116 Mini Project I

U.V.Patel College OF Engineering

4. System and System on Chip architecture (9 hours):

6. Current Architectural survey (3 hours):

Digital design (undergraduate course)

3EC212 Data Interfaces & Protocols

COURSE GOALS AND OBJECTIVES

LABORATORY WORKS (35 hours)

COURSE GOALS AND OBJECTIVES

2. OS internals and Kernels (15 hours):

RTOS Fundamentals (15 hours):

4. Device drivers (9 hours):

Real Time linux

Measuring real-time behaviour

What happens in overloadconditions (when the schedulecannot be met)

5.3 Synchronization between threads:

5.4 Using POSIX timers:

Creating reliable periodic tasks

How kernel pre-emption helps

LABORATORY WORKS (28 hours)

3EC216 Verification Techniques

COURSE GOALS AND OBJECTIVES:

Advanced Verification using Verilog :

Way of Functional Verification(HDL and HVL) :

3. Introduction to System Verilog:

5. Verification Planning and Management:

3EC217 Network Programming

COURSE GOALS AND OBJECTIVES:

7. Synchronization between threads:

8. Using POSIX timers:

3EC218 Embedded System Design & Architecture

COURSE GOALS AND OBJECTIVES

Product documentation from ARM (KEIL), Cypress, Altera, Actel.

3EC219 Hardware Board Designing with PCB Designing

7. Basic Information on different protocols.(UART,Ethernet,USB, HDMI,LCD,I2C,SPI,

14. High Speed Design Basic

3EC220 Advanced VLSI Design

Levels of IC design - Recap (2 hours):

Design Flow - Recap (2 hours):

4. Netlist to GDSII flow (36 hours):

Study and implementation of DC Expert tool (4 hours).

METHODIC PROVISION OF THE COURSE

3EC213 SYSTEM LEVEL DESIGN LAB