Test Lab

DATA ACQUISITION

Multi-channel data
acquisition system
The paper aims to
establish a synergy for
achieving a high level of
analog performance,
while keeping system
complexity low. An 8channel system provides
several orders of magnitude of improvement
over a single channel
data acquisition system.

It is a challenging task for a deAdvances in analog and digital

signer to keep up with the technologifronts continue to drive data acquisical advances in both the analog and
tion systems to higher performance.
digital domains. By finding the right
However, a dramatic improvement in
combination of analog and digital
the analog components of a system
components, not only do you gain the
may be offset by the inability of
benefit of each of the components, but
the digital components to take
you also gain the benefit of the
advantage of this improvement. A
integration.
simple example would be a singleThe technology is capable of 20-bit
channel 1kHz 8-bit data acquisition
resolution at conversion rates better
system. For this system, we could
than 20kHz. Taking it a step further
use a standard 8051 microcontroller
and adding multiple channel inputs
core with a 1kHz 8-bit analog-towould surely put us well beyond the
digital (A/D) converter. Implementing this system would be a
relatively simple task.
If we wanted to improve the
analog performance to 12, 16, or
20 bits then the task would
become more challenging, but
would still be manageable. From
an interface perspective, the
amount of data transferred from
the A/D to the microcontroller

would increase by a factor of two

to three. This would still be well
within the capability of the
microcontroller.
The challenge would be in the
throughput of the microcontroller.
At a 1kHz sample rate, performing
linearization or calibration on 8bit data may require only 10
percent of the processing capability. However, performing the same
functions on 16-bit or 20-bit data
may consume up to 50 percent of
Figure 11: Recommended voltage reference circuit.
the processing capability.
N0S1250

0.1F

ADS1250

0.1F

ADS1250

0.1F

By Robert Schreiber
Strategic Marketing Engineer
Burr-Brown Corp.

ADS1250

SX52

DRDY
CS

0.1F

DSYNC

Analog
inputs

CLK

SCLK

ADS1250

0.1F

DOUT
8

RB
RB1
RB2

RB6
RC2

PORT A

G1,G0
16

PORTS D, E

ADS1250

0.1F

Note 1: DRDY, CS, DSYNC, CLK and

SCLK are tied together on all
ADS1250's

ADS1250

0.1F

ADS1250

0.1F

2 Electronics Engineer June 2000

Note 2: DOUT, G1 and G0 each run

separately to the SX52

Test Lab

Whats Online

DATA ACQUISITION

Deep acquisition memory

solves debug problems
the need for additional filtering in the
analog or digital sections.
From a digital perspective, the
amount of data processing required
almost precludes the use of low-cost
8-bit microcontrollers. Typically,
these data acquisition systems require
more processing power along the
lines of a high-end microcontroller or
DSP. In addition, due to the amount of
data transferred, a programmable
logic device might be used as the glue
logic between the A/D and the
processor. The programmable logic
can be used to convert the serial data
from the A/D converter to parallel
data, which may be more efficiently
read by the system processor.
It is also possible to add some
processing capability to the programmable logic. However, the use of
programmable logic, high-end
microcontrollers and DSPs is contrary
to our desire to keep system complexity low. Therefore, we will take a
harder look at 8-bit microcontrollers
to see if we can get the performance
we need from them.

digital-processing capability of the

system. A 20-bit, 8-channel and
20kHz data acquisition system
provides several orders of magnitude
of performance improvement over an
8-bit single channel, 1kHz data
acquisition system and can be realized
with only an incremental increase in
complexity.

Optimum technology
combination
Individual analysis of the main
system components enables us to
choose an option that provides the best
combination of technology. For the A/
D converter, the most popular architectures for these types of applications
are successive approximation register
(SAR) and delta-sigma A/Ds.
The SAR architecture can easily
meet the sampling rate requirement,
but the resolution is a limitation. The
SAR technology is currently limited
to 16-bit resolution. To get 20-bit
resolution would require external
circuitry and increase the system
complexity. On the contrary, the deltasigma architecture can easily meet the
resolution requirements, but the
sampling rate has traditionally been
the shortcoming. However, recent
improvements in the technology now
make it possible to run the architecture at up to 25kHz with 20-bit
resolution. The delta-sigma architecture also provides a side benefit; it has
inherent digital filtering. The inherent
digital filtering in the A/D eliminates

Multi-channel architecture
If we are looking at processing eight
channels of 20-bit data at a 20kHz
sampling rate, that translates to
3.2Mbps. This poses a daunting task.
Transferring that amount of data can
be easily accommodated with high
speed serial peripherals that are now
prevalent on many microcontrollers.
However, the problem lies in the fact

+ 5V

+ 5V

0.10F
7
4.99k
2
10k

OPA350

To VREF
Pin 5 of
the ADS1250

+
10F
10F

0.10F

LM404-4.1

Figure 2
2: PWM output for driving the system clock.

3 Electronics Engineer June 2000

0.1F

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that the A/D data is coming from
eight separate channels. We could
time multiplex the data to stagger the
reception of data, but this poses
another problem. In order to do that,
we must have a method of controlling
the flow of data into the serial port.
This essentially means adding external multiplexers, which increases the
complexity of the system.
In order to keep the system complexity low; we have eliminated DSPs,
high-end microcontroller, programmable logic and a hardware serial
interface. What we have left is an 8-bit
microcontroller with direct port control
or bit banging, to shift the data from
the A/D converter to the microcontroller. The two essential factors
that limit the data throughput via port
manipulation are the microcontroller
core and the speed at which it can run.
These two parameters translate
directly into MIPS performance.
Therefore, we must find a
microcontroller core that, first, is
efficient in its instruction execution
and second, can run at high speeds.
There are many 8-bit microcontroller
cores that run at a few MIPS, and a
handful that run up to about 10MIPS.
However, this is still not sufficient
performance to handle the task at
hand. We need a core that can run
about 50MIPS or better. There is a
RISC 8-bit core that can run up to
100MIPS, which will give us the

Test Lab
DATA ACQUISITION
mov
mov
mov
mov

W, #$1F
M, W
W, #$01
!RB, W

; prepare to write port data direction registers

mov
mov
mov
mov

W, #$1A
M, W
W, #$01
!RB, W

; prepare to write WKED_B for edge trigger

mov
mov
mov
mov

W, #$19
M, W
W, #$00
!RB, W

; prepare to access WKPND_B int pending register

mov
mov
mov
mov

W, #$1B
M, W
W, #$FF
!RB, W

; prepare to write WKEN_B (enable) register

; load W with the value 01h to configure RB0 as an input

; load W with the value 01h

; configure RB0 to sense falling edges

; clear W
; clear all wake-up pending flags

; load W with the value FFh to

; enable RB0-RB2 to operate as wake-up inputs

Table 11: Code to configure and enable data-ready interrupt input.

performance we need to greatly

reduce the complexity of the system.
The core system has some peripheral
features that help in further reducing
the system complexity.

4 Electronics Engineer June 2000

So now that we have the individual

analog and digital components chosen
for the system. How do these components give us a complete system? We
must look at how these parts function

from a top level to simplify the

integration (figure 1). First, the A/D
converter operation is relatively
straightforward. A system clock
controls the sample rate of the data
from the A/D converter. Once the
conversion is complete, the DRDY
(data ready) line goes low to indicate
that new data is available. The SCLK
(serial clock) shifts data out of the
DOUT (data output) line and is gated
by CS (chip select).
Some additional functions of the A/
D include DSYNC (data synchronization) that can be used to synchronize
multiple converters. In addition, signal
gain can also be used to control the
internal programmable gain amplifier
on-board the A/D converter. These
features eliminate the need for external
gain or control circuits. So essentially,
the analog signal of interest may only
need a simple RC buffer circuit
between the source and the A/D input.

Test Lab
DATA ACQUISITION
System configuration
We have already discussed the main
feature of the microcontroller, MIPS.
There are also some additional functions of the microcontroller, which
allow a further reduction in system
complexity. First is external interrupt
capability. Since a new data conversion
is signaled by the A/D converter by
taking DRDY low, the microcontroller
interrupt capability can be used to
commence data shifting (table 1).
Another important feature is the onboard pulse width modulator (PWM).
The PWM can be used to generate the
system clock for the A/D converter. In
addition, since the PWM frequency
and duty cycle is programmable, the
sample rate of the A/D converter can
be controlled from DC to 25kHz (the
maximum sample rate of the device)
by merely changing register values.
Next, the PWM should be configured to run the A/D system clock.

5 Electronics Engineer June 2000

Since the microcontroller clock is

running at 100MHz, the PWM period
will be multiples of 20ns (1/2 of the
100MHz period). It is important to
note that the duty cycle of the A/D
clock does not need to be 50 percent.
If we are running with a 120ns period,
we could configure the high time as
80ns and the low time as 40ns. This
allows additional flexibility in setting
the A/D system clock frequency.
In this application, we will use a 50
percent duty cycle, so the PWM
registers will be configured for clear

and set values of three cycles. This

means that at the beginning of a PWM
cycle, the output will be driven high
and after three PWM cycles, the
output will be driven low. At the end
of the PWM cycle, the output will be
driven high again. The waveform is
shown in figure 2.

Conversion, interrupt
operations
Now that the part is configured, we
are ready to start converting data. On
power-up, we drove DSYNC low and

Function

Cycles required

Data transfer (8 Channels)

1,310

Offset correction (8 Channels)

210

Gain correction (8 Channels)

2,250

Total

3,770

Table 2
2: Estimated number of instruction cycles to implement data transfer and calibration.

Test Lab
DATA ACQUISITION
this places the part in a hold state. When we drive DSYNC
high, the part is released from hold and starts performing
conversions. When a conversion completes, the DRDY line
goes low, which generates an interrupt on the microcontroller. The microcontroller vectors to the interrupt handler,
takes chip-select low, and then shifts the data in. The A/D
converter shifts most significant bit (MSB) first. Since all
the DOUTs from the A/D converters are brought in on one
port, the data is shifted in bit-by-bit, MSB to LSB.
It only takes one instruction cycle to read a bit from all
eight channels. The remainder of time is spent converting
the bit data into channel data. There are numerous techniques that can be used to shift the data into the
microcontroller, but the method used in this implementation
is very efficient in resource usage. Once the data is shifted
into RAM, chip-select is taken high and the interrupt handler
is exited. The microcontroller can spend the rest of the time
performing linearization or calibration on the data.
By running the microcontroller at its rated speed of
100MHz, the resolution of the PWM will let us run the
PWM at 8.333MHz. We could actually run the PWM at
50MHz, but this is well over the specified clock frequency
of 9.6MHz for the A/D. The 8.333MHz PWM frequency
translates into a sample rate of 22kHz for the A/D, which
allows approximately 46s between conversions.
For the microcontroller, 46s equate to 4,600 instruction
cycles between conversions at 100MHz. If all we wanted
to do was data averaging, we could dramatically reduce the
clock frequency of the microcontroller and still have
sufficient throughput to accomplish this. Data averaging
and data transfer could easily be accomplished in less than
half the time between conversions. However, if we want to
perform more intensive computations, such as full-data
calibration on all eight channels, then throughput could be
an issue.
Table 2 summarizes the number of instruction cycles
required to transfer the data from the A/D converter, and to
perform offset and gain corrections on the eight channels of
20-bit data. The table shows that it requires approximately
3,800 instruction cycles to perform all these tasks. This
means that we can clearly handle processing eight channels
of 20-bit A/D data at a 22kHz rate. Overall, we are using
about 86 percent of the A/D converters performance and 84
percent of the microcontrollers performance.
In conclusion, we used high performance analog and
digital technology to achieve a multi-channel, high resolution and high sample-rate data-acquisition. We achieved
this through a high level of integration while keeping
system complexity low.
You may e-mail Robert Schreiber at schreiber_robert@
burrbrown.com, or fax: 1-520-7467467.

6 Electronics Engineer June 2000