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Introduction
Chapter 2
Literature Review
Modugu.R,
Yong-Bin
Kim,
Minsu
Choi,Design
and
performance
Antti Hamalainen, Matti Tommiska, and Jorma Skytt, 6.78 Gigabits per
Second Implementation of the IDEA Cryptographic Algorithm, 2002
Springer-Verlag, pages 760-769.
IDEA (International Data Encryption Algorithm) is one of the strongest secret-key block
ciphers. The algorithm processes data in 16-bit sub blocks and can be fully pipelined. The
implementation of a fully pipelined IDEA algorithm achieves a clock rate of 105.9 MHz on
Xilinx XCV1000E-6BG560 FPGA of the Virtex-E device family. The implementation uses
18105 logic cells and achieves a throughput of 6.78 Gbps with a latency of 132clock cycles.
Chapter 3
Proposed Methodology
In the presented research, Improved Modulo (2n + 1) Multiplier with radix-8 Booth recoding
is applied to International Data Encryption Algorithm
The number of partial products generated in less than n/2 for n bit multiplication, thereby
reducing the number of intermediate addition operations.
Chapter 4
Platform Used
Altera Quartus
Altera Quartus is a programmable logic device design software from Altera. Its features
include:
Quartus II is a software tool produced by Altera for analysis and synthesis of HDL designs,
which enables the developer to compile their designs, perform timing analysis, examine RTL
diagrams, simulate a design's reaction to different stimuli, and configure the target device
with the programmer. The latest version (January 2011) is 10.1.
Chapter 5
Expected Output
less than n/2 for n bit multiplication, thereby reducing the number of intermediate
addition operations.
Chapter 6
References