Assignment 1

ECE 311
Computer Architecture and Organization
Fall 2014

Due date: Sept. 25, 2014 3:30 pm

Marks
Question
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
TOTAL

Note
You should justify your answers.

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Mark
4
3
7
6
9
8
4
4
45

Assignment 1
Q1 One challenge for architects is that the design created today will require several years of implementation,
verification, and testing before appearing on the market. This means that the architect must project what
technology will be like several years in advance. Sometimes, this is difficult to do.
(a) {2 mark} In recent years, capacity per Flash chip has increased by about 60% per year. At this rate, how
much increase in capacity per Flash chip we will see in a decade?
(b) {2 mark} Based on the above rate, in roughly how many years the capacity per Flash chip increases by
a factor of four?
Q2 Suppose we developed a new, simpler processor A that has 80% of the capacitive load of the more complex
older processor B. Further, assume that it has adjustable voltage so that it can reduce voltage 15% compared
to processor B, which results in a 15% shrink in frequency. What is the impact on dynamic power?
Q3 The reciprocal of MTTF is a rate of failures, generally reported as failures per billion hours of operation, or
109
FIT (for failures in time). For example, an MTTF of 1, 000, 000 hours equals 10
6 = 1000 FIT.
Availability is the most important consideration for designing servers, followed closely by scalability and
throughput.
(a) {1 mark} We have a single processor with a failures in time (FIT) of 100. What is the mean time to
failure (MTTF) for this system?
(b) {2 mark} If it takes 1 day to get the system running again, what is the availability of the system?
(c) {4 mark} Imagine that the government, to cut costs, is going to build a supercomputer out of inexpensive computers rather than expensive, reliable computers. What is the MTTF for a system with 1000
processors? Assume that if one fails, they all fail. Also, use the simplifying assumptions that lifetimes
are exponentially distributed and that failures are independent.
Q4 Assume that we make an enhancement to a computer that improves some mode of execution by a factor of 10.
Enhanced mode is used 50% of the time, measured as a percentage of the execution time when the enhanced
mode is in use. Recall that Amdahs law depends on the fraction of the original, unenhanced execution time
that could make use of enhanced mode. Thus, we cannot directly use this 50% measurement to compute
speedup with Amdahls law.
(a) {3 mark} What is the speedup we have obtained from fast mode?
(b) {3 mark} What percentage of the original execution time has been converted to fast mode?
Q5 When making changes to optimize part of a processor, it is often the case that speeding up on type of instruction
comes at the cost of slowing down something else. For example, if we put in a complicated fast floating point
unit, that takes space, and something might have to be moved farther away from the middle to accommodate it,
adding an extra cycle in delay to reach that unit. The basic Amdahls law question does not take into account
this trade-off.
(a) {2 mark} If the new fast floating-point unit speeds up floating-point operations by, on average, 2, and
floating-point operations take 20% of the original programs execution time, what is the overall speedup
(ignoring the penalty to any other instructions)?
(b) {4 mark} Now assume that speeding up the floating-point unit slowed down data cache accesses, resulting in a 1.5 slowdown (or 23 speedup). Data cache accesses consume 10% of the execution time. What
is the overall speedup now?
(c) {3 mark} After implementing the new floating-point operations, what percentage of execution time is
spent on floating-point operations? What percentage is spent on data cache accesses?

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Assignment 1
Q6 Consider a 16-bit floating-point representation based on the IEEE floating-point format (the format we discussed in the class), with one sign bit, seven exponent bits (k = 7), and eight fraction bits (n = 8). The
exponent bias is then 271 1 = 63.
(a) {2 mark} What is the largest denormalized number that can be encoded in this format?
(b) {3 mark} What is the smallest value > 7 that can be encoded in this format?
(c) {3 mark} What is the number with hex representation 80C0? (i.e., decode 80C0, where 80C0 represents
a floating point)
Your answers to the above questions should be of the form x 2y , where x and y are integers.
Q7 Sort the following numbers from lowest to highest. The numbers are represented as 8-bit floating-point representation based on the IEEE floating-point format. Note that for sorting you do not need to know the size of
the exponent or the size of the significand!
a) 10110000, b) 01011111, c) 01101101, d) 10101111, and e) 01101011
Q8 Show how the following binary fractional values would be rounded to the nearest half (1 bit to the right of the
binary point), according to the round-to-even rule.
(a) (10.010)2
(b) (10.011)2
(c) (10.110)2
(d) (11.001)2

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