Electronic Devices

KEEE 2224
Lecture 7
Metal-Oxide-Semiconductor
Field Effect Transistor
Dr. Ghafour Amouzad Mahdiraji
November 2012

Basic MOSFET Operation

The current in a MOSFET is due to the flow of charge in the inversion layer or
channel region adjacent to the oxide-semiconductor interface.

Basic MOSFET Operation

m < s
Ec
s

m
EFm

Ec
EFi
Metal

EF

Ec

Ec
EFi
-+
-+
Metal - +Oxide-

Ev

p-type

Ev

EF

EF

Oxide

Ev

p-type

Ev

EFs

Ec

s
+Metal +
+

+
+
+

Oxide

--

Ec
EFi
p-type

Ev

Ev

EF

Basic MOSFET Operation

What VG need to be applied to make

depletion region ON? Positive
m > s

p-type

+VG

What VG need to be applied to make

depletion region OFF? Negative
m < s

-VG

p-type

How we can let the current flow in this device?

Basic MOSFET Operation

m > s

VG = 0

p-type

m < s

VG = 0

p-type

++++-

+
+
+
+
-

+
+
+
+

-+
-+
-+
-+

MOSFET Structures
There are four basic MOSFET device types:
n-channel enhancement mode MOSFET
n-channel depletion mode MOSFET
p-channel enhancement mode MOSFET
p-channel depletion mode MOSFET

n-Channel MOSFETs

Enhancement-type MOSFET:
The device is OFF at zero gate voltage.

Depletion-type MOSFET:
The device is ON at zero gate voltage.

A +tive gate voltage induces the electron

inversion layer, which then connects the
n-type source to drain regions.

Electron inversion layer exist at 0 V and

can be off with -tive voltage.

The source terminal is the source of carriers that flow through the channel to drain.
In n-channel device, electrons flow from the source to the drain through the channel,
thus, the current directed from drain to source.

p-Channel MOSFET

p-channel enhancement mode MOSFET

p-channel depletion mode MOSFET.

A -tive gate voltage must be applied to

create an inversion layer of holes that
will connect the p-type source to drain
regions.

Electron inversion layer exist at 0 V and

can be off with +tive voltage.

In p-channel device, holes flow from the source to the drain through the channel,
thus, the current directed from source to drain.

Current-Voltage Relationship
Considering a n-channel enhancement mode MOSFET with a gate-tosource (or gate-to-semiconductor) voltage that is less than the threshold
voltage and with only a very small drain-to-source voltage.
The source and substrate terminals are held at ground potential.
With this bias configuration, there is no electron inversion layer, the
drain-to-substrate pn junction is reverse biased, and the drain current is
zero (regardless of pn junction leakage current).

Current-Voltage Relationship
n-channel enhancement mode MOSFET with an applied gate voltage VGS >
VT.
An electron inversion layer has been created so that when a small drain
voltage is applied, the electrons in the inversion layer will flow from the
source to the positive drain terminal. Thus the current is from drain to source.

Field Effect on Transistor Current

For small VDS values, the channel region has
the characteristics of a resistor, so

I D g dVDS
where gd is the channel conductance in the limit
as VDS 0.
The channel conductance is given by

gd

W
n Q 'n
L

where n is the mobility of the electrons in the

inversion layer and |Q'n| is the magnitude of the
inversion layer charge per unit area.
The inversion layer charge is a function of the gate voltage; thus, the basic MOS
transistor action is the modulation of the channel conductance by the gate voltage.
If VGS < VT no inversion layer ID = 0
If VGS > VT channel inversion charge density increases channel conductance
increase larger ID.

Voltage (VDS) Effect on Current

(a): VGS > VT and VDS is small
The thickness of the inversion channel
layer in the Fig qualitatively indicates
the relative charge density, which is
constant along the entire channel .

(b): VGS > VT and VDS is larger than case (a)

As the drain voltage increases, the
voltage drop across the oxide near the
drain terminal, which means the induced
inversion charge density near the drain
also decreases.
Channel conductance at the drain
decreases, which means the slop of the
ID versus VDS curve will decrease.

Voltage (VDS) Effect on Current

(c): VGS > VT and VDS = VDS(sat)
When VDS increases to the point
where the potential drop across the
oxide (at the drain terminal voltage is
equal to VT), the induced inversion
charge density get zero at the drain
terminal.
At this point, the incremental
conductance at the drain is zero, which
means that the slope of the ID versus
VDS curve is zero.

VGS VDS (sat ) VT

VDS (sat ) VGS VT

where VDS(sat) is the drain-to-source voltage producing zero inversion charge density
at the drain terminal.

Voltage (VDS) Effect on Current

(d): VGS > VT and VDS > VDS(sat)is larger
than case (a)
When VDS becomes larger than
VDS(sat), the point in the channel at
which the inversion charge is just zero
moves toward the source terminal.
In this case, electrons enter the channel at the source, travel through the channel
toward the drain, and then, at the point where the charge goes to zero, the electrons
are injected into the space charge region where they are swept by the E-field to the
drain contact.
If assuming the change in channel length L is small, then the drain current will be a
constant for VDS > VDS(sat). This region is referred as the saturation region.

Family of ID versus VDS

Now, if VGS changes, the ID versus VDS
curve will change.
Considering following equation, where
VDS(sat) is a function of VGS.

VDS (sat ) VGS VT

A family of curves can be generated for this
n-channel enhancement mode MOSFET.

ID Vrs VDS in n-Channel Depletion Mode MOSFET

In n-channel depletion mode MOSFET, an induced electron inversion layer exist at zero
gate voltage.
The current-voltage characteristics in depletion-type is exactly the same as the
enhancement-type MOSFET, except that VT is a negative quantity.
In depletion-type, a -tive gate voltage required to reduce the thickness of the n-channel
region and also the drain current.
One basic requirement for this device is that the channel thickness tc must be less than
the maximum induced space charge width in order to be able to turn the device off.

MOSFET Transistor Current

The operation of a p-channel device is the same as that of the n-channel, except the charge
carrier is the hole and the conventional current direction & voltage polarities are reversed.

n-channel MOSFET
In the nonsaturation region

p-channel MOSFET

W nCox
2(VGS VT )VDS VDS2
ID
2L
or

I D K n 2(VGS VT )VDS V

2
DS

W pCox
2(VGS VT )VDS VDS2
ID
2L

I D K p 2(VGS VT )VDS VDS2

or

where Kn = (WnCox)/2L is called the

conduction parameter for the n-channel
MOSFET with units of A/V2.
When the transistor is biased in the
saturation region, the ideal currentvoltage relation is given by:

I D (sat )
or

W nCox
(VGS VT ) 2
2L

I D (sat ) K n (VGS VT ) 2

W pCox
I D (sat )
(VGS VT ) 2
2L
or

I D (sat ) K p (VGS VT ) 2

Example
Design the width of a MOSFET such that a specified current is induced for a given
applied bias.
Consider an ideal n-channel MOSFET with parameters L = 1.25 m, n = 650 cm2/Vs, Cox = 6.9 10-8 F/cm2, and VT = 0.65 V. Design the channel width W such that
ID(sat) = 4 mA for VGS = 5 V.

Complementary MOS (or CMOS) Devices

We have discussed both n-channel and p-channel enhancement MOSFETs.
When both devices are used in a circuit, they form a Complementary MOS
(or CMOS).
CMOS inverter is one of the basis of CMOS digital logic circuits.
The dc power dissipation in a digital circuit can be reduced to very low
levels by using a complementary p-channel and n-channel pair.
Usually, such devices fabricated in one cheep using integrated circuit. It is
necessary to form electrically isolated p- and n-substrate regions in an
integrated circuit to accommodate the n- and p-channel transistors.

Example of CMOS Structures

CMOS Inverter
For small values of the input voltage, VIN, the nMOS transistor is switched off,
whereas the pMOS transistor is switched on and connects the output mode to VDD.
For large values of the input voltage, VIN, the pMOS transistor is switched off,
whereas the nMOS transistor is switched on and connects the output mode to GND
= 0V.