Electronic Devices

KEEE 2224
Lecture 8
Complementary Metal-OxideSemiconductor (CMOS)
Dr. Ghafour Amouzad Mahdiraji
November 2012

n-Channel MOSFETs

Enhancement-type MOSFET:
The device is OFF at zero gate voltage.

Depletion-type MOSFET:
The device is ON at zero gate voltage.

A +tive gate voltage induces the electron

inversion layer, which then connects the
n-type source to drain regions.

Electron inversion layer exist at 0 V and

can be off with -tive voltage.

p-Channel MOSFET

p-channel enhancement mode MOSFET

p-channel depletion mode MOSFET.

A -tive gate voltage must be applied to

create an inversion layer of holes that
will connect the p-type source to drain
regions.

Electron inversion layer exist at 0 V and

can be off with +tive voltage.

Complementary MOS (or CMOS) Devices

We have discussed both n-channel and p-channel enhancement MOSFETs.
When both devices are used in a circuit, they form a Complementary MOS
(or CMOS).
CMOS inverter is one of the basis of CMOS digital logic circuits.
The dc power dissipation in a digital circuit can be reduced to very low
levels by using a complementary p-channel and n-channel pair.
Usually, such devices fabricated in one cheep using integrated circuit. It is
necessary to form electrically isolated p- and n-substrate regions in an
integrated circuit to accommodate the n- and p-channel transistors.

p- and n-Channel MOSFETs in Enhancement Mode

before applying +ve & -ve gate voltage

p- and n-Channel MOSFETs in Enhancement Mode

after applying +ve & -ve gate voltage

p- & n-Channel MOSFET: Complementary MOS Inverter

VDD

VDD

Output = High

n
S
GND

Substrate

-------------

D
Gate

Substrate

n
GND

Substrate

Output = Low

n
S
GND

p
---------

p
D

Input
=
High

Output

Gate

Substrate

Input
=
Low

Gate

Input

Gate

+++++++++

VDD

CMOS Inverter
For small values of the input voltage, VIN, the nMOS transistor is switched off,
whereas the pMOS transistor is switched on and connects the output mode to VDD.
For large values of the input voltage, VIN, the pMOS transistor is switched off,
whereas the nMOS transistor is switched on and connects the output mode to GND
= 0V.

CMOS Inverter Circuits

VDD

VDD

S
p channel

p channel

D
Input

Output

D
Input

Output

D
n channel

n channel

S
GND
Enhancement mode

S
GND
Depletion mode

Note that when the input voltage increase from 0V to 5V the output voltage decreases
from 5V to 0V.
In region 3 VOUT = 0V and ID = 0.
In region 1 VOUT = VDD and ID = 0.
In region 2 the transistor remains only
for a short period of time, when the
input voltage switches between VL
and VH.
In this region there is non-zero current
flowing between VDD and GND, and
some power dissipation, which is
converted into heat.
Note that the same current flows
through the pMOS and nMOS
transistors, that is, IDp = IDn.
The fact that in regions 1 and 3 NO
current flows between VDD and GND,
is very attractive because there is no
power dissipation at this stages. This
very fact is the reason that all digital
circuitry is now build in the CMOS
technology.

Example of CMOS Structures