IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS,VOL. 28, NO.

5, SEPTEMBER/ OCTOBER 1992

1023

A Novel Control Scheme of a Parallel

Current-Controlled PWM Inverter
Satoshi Ogasawara, Member, IEEE, Jin Takagaki, Hirofumi M a g i , Member, IEEE,
and Akira Nabae, Fellow, IEEE
Abstract-A novel parallel technique for current-controlled
PWM inverters is described. Two voltage source inverters, the
output terminals of which are connected in parallel through
current balancers, are used as a main circuit. In this scheme,
excellent characteristics both in steady states and in transient
states are obtained, keeping the average values of the cross
current and zero sequence current at zero level. This current
control scheme is applicable to large-capacity GTO inverters
because good performance is attained even if the switching
frequency is only a few hundred Hertz, as shown in the experimental results.

transient states and a low harmonic current content in

steady states. However, these two requirements contradict
each other, that is, the switching mode that yields a high
current derivative must be chosen to pioduce the quick
current response, whereas the switching mode that yields
a low current derivative must be chosen 13 suppress the
current harmonic content. To solve the problem, the
authors already proposed a novel current control scheme
of a single-bridge voltage source inverter, in which the
switching mode that yields a low current derivative is
changed to the switching mode that yields a high current
I. INTRODUC~ON
derivative when a large current deviation appears [ll].
Nowadays, attention is paid to the parallel technique
URRENT-CONTROLLED PWM inverters play the
for
current-controlled PWM inverters that may meet the
ost important role in a high-performance ac servo
system and a reactive power compensating system. Con- required properties (i.e., large output power, low harventional current controllers utilizing a voltage source monic current content, and/or low switching frequency).
In this paper, a novel current control scheme of parallel
inverter can be classified as follows:
current-controlled PWM inverters is discussed. This curDirect type-The switching pattern is directly deter- rent controller pertains to the direct type above menmined from the current deviation vector. The hystere- tioned. Two bridge inverters, the output terminals of
sis-type current controllers [SI, [lo], [121, [131, the which are connected in parallel through the current balpredictive current controllers [9], [13], [141, and the ancers, are used as the main circuit. The harmonic curcurrent controller previously proposed by the authors rent content and switching frequency are reduced consid[ l l ] are included.
erably because a different switching pattern is given to
Indirect type [12]-[22]-The average voltage reference each inverter. In general, a cross current and a zero
vector during a very small interval of time is deter- sequence current, however, flow between the two invertmined to force the actual current to follow its refer- ers. This proposed scheme makes it possible to keep the
ence. The switching pattern and sequence are deter- average values of these currents at zero level all the time,
mined by the voltage reference vector. The ramp thus giving excellent characteristics both in steady and in
comparison current controllers and the minimal time transient states.
control of the current vector [12]-[14] are included.
11. PRINCIPLE OF CONTROL STRATEGY
In the direct-type current controller, there is basically no
Fig. 1 shows an equivalent load circuit of a voltage
phase lag, but the switching frequency is not constant. On
source inverter. The voltage-current vector equation is
the other hand, in the indirect-type current controller, the
expressed as follows:
switching frequency is constant, but some phase lag arises.
di
Some papers on phase lag compensation based on feedU = L- + Ri + e ,
dt
back and feedforward control have already been pubwhere the inverter output voltage vector U, the current
lished [151-[211.
The characteristics required from the current-con- vector i, and the inner induced voltage vector e , are givexi
trolled PWM inverter are a quick current response in bY

cm

U = [VdVqIT = C [ V a V b V , I T ,

Paper IPCSD 91-126, approved by the Industrial Drives Committee of

the IEEE Industry Applications Society for presentation at the 1987
Industry Applications Society Annual Meeting, Atlanta, GA, October
18-23. Manuscript released for publication September 1, 1991.
The authors are with the Department of Electrical Engineering,
Nagaoka University of Technology, Nagaoka, Niigata, Japan.
IEEE Log Number 9108231.
0093-9994/92$03.00

0 1992 IEEE

[idiqlT= c [ i a i b i C l T ,

IEEE TRANSACTIONS O N INDUSTRY APPLICATIONS, VOL. 28, NO. 5, SEPTEMBER / OCTOBER 1992

1024

be chosen to attain quick current response, whereas the

voltage vector that yields a low d Ai/dt should be chosen
to reduce the switching frequency. In the following sections, the way to choose the voltage vector and switching
pattern is described.
Fig. 1. Load of a voltage source inverter.

111. ANALYSIS
OF PARALLEL
INVERTERS

The current deviation vector Ai is defined as

Ai = i* - i

(2)
where i* is the current reference vector. Substituting (2)
into (1) produces
dAi
L-+RAi=
dt

L-+Ri*+e,

Generally, RAi can be neglected compared with

Ld Ai/dt. Expressing the parentheses on the right hand
of (3) as e gives the following equations
d Ai
L-=e-U
dt
di *
e =L+ Ri*
dt

(4)

+ e,

(5)

Fig. 2 shows the main circuit of the parallel currentcontrolled PWM inverter described in this paper. Two
voltage source inverters are connected in parallel through
the current balancers. The inverter output voltage vector
U and the inverter output current vector i are expressed
as follows:
1
U = -(U1 + u 2 )
(6)
2
i

where

i,

+ i,

U1 = c [ u a l u b l u c l l r

= ECISalSblSclIT,

u 2 = C[uaZub2uc21T

= EC[SaZSb2Sc21T~

i,

(7)

C[ialibliCllT,

i2 = c [ i a Z i b 2 i c 2 l T .

In Fig. 2, one or zero of switching functions sal, sbl, scI,

where e means a load counter EMF vector at the inverter sa2,sb2,sc2 corresponds to the mode in which the upperoutput terminals under the condition that the current side device or the lower side device is on state, respecvectar i ideally equals the reference i*, that is, e is the tively. The parallel voltage source inverter can produce 19
voltage vector that lets the load carry the current i* different voltage vectors that have a number k from 0 to
without any current deviation. In other words, if the 18 as shown in Fig. 3. Table I shows the relationships
voltage source inverter can always output the same volt- between the switching pattern and the number of the
age as e, no current deviation vector Ai appears. How- output voltage vector k . Hereinafter, the inverter output
ever, the inverter can output only one voltage vector out voltage vector will be expressed as d k ) . Compared with a
of the discrete set of voltage vectors corresponding to the single bridge inverter, the number of output voltage vecswitching patterns. The instantaneous value of the current tors increases from 7 to 19. This means that the harmonic
deviation cannot be made zero all the time.
current content and the switching frequency can be reTherefore, a tolerance of the deviation vector is set up. duced considerably.
If the deviation vector Ai is in the permissible region, the
Note that a cross current flows between the two invertactual current vector i is judged to follow the reference ers through the current balancers because the different
vector i*; therefore, the output voltage vector is not switching patterns are given to each inverter. The
altered. If Ai is outside the permissible region, i is judged voltage-current vector equation of the cross current cirnot to follow i*; therefore, another voltage vector that cuit is expressed as follows:
can make the deviation vector Ai smaller is chosen. Note
d
that the d A i / d t of the output voltage vector has a
u 1 - uz = l - ( i l - i 2 )
dt
direction component opposite that of Ai. By repeating the
above-mentioned process, the current deviation vector Ai where 1 is an inductance of a current balancer measured
between the output terminals of the two inverters. Table
is kept within the permissible region at all times.
Equation (4)shows that the derivative of the deviation I1 shows the relationships between the switching pattern
vector d Ai/dt is determined by the choice of an inverter and the cross current vector i, - i , . In this table, a plus
output voltage vector U out of the discrete set of voltage or minus sign indicates increasing or decreasing, and the
vectors. If a voltage vector is chosen so that the deviation last letter (a, 6, c, x, y , z ) shows the axis and the direction
derivative is large and i:egative, the current deviation in which the cross current vector is increasing or decreasvector Ai would rapidly become smaller but then would ing. Here, the x, y , and z axes are defined as in Fig. 4.
exceed the permissible region again. If a voltage vector is For example, + a means that the cross current vector
*
is increasing to the a-axis direction by
chosen so that the deviation derivative is small and negaand - a y means that i, - i , is detive, Ai would decrease more slowly, and the time until i i&;/IIA/sl,
exceeds the permissible region would be longer. There- creasing in the y-axis direction by f i E / l [ A / s l .
fore, the voltage vector that yields a high d Ai/dt should
If the dc input terminals of the two inverters are

1025

OGASAWARA et al.: NOVEL CONTROL SCHEME OF A PWM INVERTER

ubl

lbl

E ,

Fig. 2. Parallel voltage source inverter (dual voltage sources).

Fig. 4. Definition of axes.

connected in parallel and the two inverters are fed by a

single voltage source as shown in Fig. 5, the zero sequence
current, in addition to the cross current, flows through the
current balancers. The voltage-current equation of the
zero sequence circuit is expressed as follows:

d
U01

- U02 = y

1 -

io,)

(9)

where
=
u02 = (.a2

Fig. 3. Output voltage vectors of the parallel inverter.

TABLE I
RELATIONSHIPS
BETWEEN
SWITCHING
PATTERN
AND K
011

001

101

111

14
7
2

15
14

16

17
18

8
0

3
9
16

13
14

13
14
15
16
17
18

15

18
12
13
0
17
11
6
18

100

110

000

100
110

13
14
15
16
17
18

13
1
7
14
0
18
12
13

010
011
001
101
111

( s a 2 sb2 sc2)

010

000

(s,lsbls,I)

15

0
15
9
4
10
17
16

0
16
10
5
11
17

TABLE I1
RELATIONSHIPS
BETWEEN
SWITCHING
PATTERN
AND CROSS
CURRENT
VECTOR

(s,Isbls,l) 000
000
100
110
010
011
001
101
111

100

0
-a
+a
0
-c
+b
+b + 6 Y
-a
-2a
+c - 6 X
-b
+C
0
-a

(s.2 Sb2 S C Z )

110

010

+C

-b
-6 Y
+a

-b
0
-a
- fix
- 2c

+ fiz
+C

011

001

101

111

+a

-C

+b

0
+a

+ 2a + i 5 X
+ fix - 2c

--c
-6

- 6 2 +2b
+C
0
+b
+f i Y
+ !fTz -b
-a
0
-2b
+a
0
-6 Y
-b
--c
+b
+a
--c

-C

f b
-a
+C

-b
0

+ ucl)/fi

+ 'bl + ' c l ) / f i ?

+ ub2 + u c 2 ) / f i

+ 'b2 + ' c Z ) / a ,

io,

= (id

io,

(ia,

+ i,, + ic1)/G,

+ ib2 + icz>/a.

Table I11 shows the relationships between the switching

pattern and the zero sequence current io, - io,. In this
table, a plus or minus sign indicates increasing or decreasing. For example, + 2 means that the zero sequence
current io, - io, is increasing by 2 E / ( f i I ) [ A / s ] .
The cross current and the zero sequence current should
be controlled to zero. The instantaneous values of these
currents cannot be made zero all the time. Therefore, two
tolerances are set up for the cross current vector and zero
sequence current so that these currents are controlled
within the tolerances in the same way that as is the
current deviation vector, that is, the average values of
these currents can be controlled to zero.
This control scheme is suitable for large-capacity variable frequency supplies in which more than two bridges
are required. In a conventional parallel-connected inverter in which similar switching patterns is given to each
inverter, neither cross current nor zero sequence current
flows, theoretically. However, the parallel inverter needs
three current balancers because the output current balance between two inverters is affected by a difference in
switching time and forward voltage drop [25].Two isolated
dc power supplies as shown in Fig. 2 are required. Assuming that diode rectifiers are used as the dc power supplies,

I
IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 28, NO. 5 , SEPTEMBER / OCTOBER 1992

1026

i.
t

Inv.1

(ii)

Fig. 5. Case of single voltage source.

TABLE 111
RELATIONSHIPS
BETWEEN
SWITCHING
PAITERNAND ZEROSEQUENCE

CURRENT
( s s s )
(S,,Sh,S,,)

000
100
1 3
010
011
001
101
111

000

100

110

ol$

0
+1
+2
+1
+2
+1
+2
+3

-1
0
+1
0
+1
0
+1
+2

-2
-1
0
-1
0
-1
0
+l

-1
0
+1
0
+1
0
+1
+2

b2i?1

001

101

111

-2
-1
0
-1

-1
0
+1
0

0
-1
0
+1

fl

-2
-1
0
-1
0
-1
0
+1

-3
-2
-1
-2
-1

0
+1
+2

Fig. 6. Selection of voltage vector ( k l ,k , , k3): (a) Voltage plane; (b)

deviation current plane.
d

-2
-1
0

the fifth and seventh ac-side harmonic currents are eliminated by using multiphase transformers.
I v . SELECTION OF A SWITCHING MODETO SUPPRESS
HARMONIC
CURRENT
A. Selection of a Voltage Vector v(k)

Fig. 7. Selection of voltage vector ( k 4 ,k,, k6): (a) Voltage phase; (b)
deviation current plane.

To suppress the harmonic current and to reduce the

switching frequency, a voltage vector u ( k ) is chosen to
give small d A i / d t as expressed in Section 11. Therefore,
the voltage vector is one of three vertices of the triangle
including e , as shown in Fig. 6(a). A relationship between
the voltage vector and the current deviation vector is
expressed as the following equation:

line-to-line rms value of the maximum sinusoidal inverter

output voltage is E / fi.However, there exists a tradeoff
between the drive's bus utilization capability and the
current controllability in transient states because the current controllability is determined by the difference between e and u ( k ) as expressed by (10).

B. Selection of a Switching Pattem

The procedure explained in Section IV-A can determine a voltage vector out of the 19 vectors, but a switchIn Fig. 6(a), u ( k , ) can increase Ai to the y-axis direc- ing pattern cannot be determined because the switching
tion, whereas u(kJ and u(k,) can increase Ai to the z pattern that outputs the voltage vector is not unique.
Utilizing the degree of freedom, the cross current vecand x axis directions, respectively. To construct the Ai
detection circuit simply, the A i plane is divided into four tor i , - i , and the zero sequence current io, - io, are
regions as shown in Fig. 6(b). If the deviation vector Ai is controlled. The cross current plane is divided into seven
in the hexagon, i is judged to follow i*; therefore, u ( k )is regions as shown in Fig. 8, and the zero sequence current
the voltage vector is detected by a window comparator. When the cross
not altered. If A i is in region
current vector is within the hexagon, the cross current is
u ( k , ) should be chosen. If Ai is in region @ or 0,
judged to not flow. In addition, when the zero sequence
u ( k , ) or u ( k , ) should be chosen, respectively.
current is within the window, the zero sequence current is
Similarly, if e is in the triangle shown in Fig. 7(a), and judged not to flow. According to the following conditions,
Ai is in region @,
or @ as shown in Fig. 7(b), a switching pattern is chosen:
u(k,), u(k,), or u ( k , ) should be chosen, respectively. If
1) The voltage vector selected from Section IV-A is
Ai is in the hexagon shown in Fig. 7(b), u ( k ) is not
output.
altered.
2)
The
cross-current vector is reduced.
If e is in the triangle shown in Fig. 6(a) or Fig. 7(a), the
3)
The
zero sequence current is reduced.
current deviation vector Ai is always controlled into the
4) The number of switching times is minimal.
hexagon by the above-mentioned method. If e is outside
5 ) The switching frequencies of the two inverters are
of the hexagon, Ai cannot be controlled any longer.
balanced.
Therefore, this control scheme is applicable to the load of
which e is within the largest hexagon shown in Fig. 3. The Here, the conditions are in order of priority. In the case
d Ai
L- dt = e

u(k).

0,

0,

(10)

1027

OGASAWARA et al.: NOVEL CONTROL SCHEME OF A PWM INVERTER

Fig. 8. Cross-current plane.

of dual voltage sources, condition 3) is excluded because

the zero sequence current will not exist. If the cross-curent
vector is in the hexagon shown in Fig. 8, condition 2) is
excluded. If the zero sequence current is in the window,
condition 3) is excluded. The inverter output current
vector i , the cross current vector i , - i,, and the zero
sequence current io, - io, are controlled by selection of
the switching pattern.

Fig. 9. Detection of e.

TABLE IV
DETECTION
OF e

C. Detection of the Region to which e Belongs

It is possible to keep Ai within the hexagon of Fig. 6(b)
and Fig. 7(b) by the procedure shown in Section IV-A.
However, to determine the output voltage vector, it is
necessary to detect to which triangular region e belongs.
VI. SYSTEM
CON~GURATION
A relationship between the voltage vector u(k) and the
Fig. 10 shows the current controller to suppress the
current deviation vector Ai is expressed by (10).
harmonic
current. As mentioned in Section IV-A, the
d Ai
u(k) is selected according to the current
voltage
vector
L= e - u(k).
(10)
dt
deviation vector Ai and to where triangular region e
Therefore, the triangular region to which e belongs is belongs. Where triangular region e belongs is determined
detected as follows. if the x-axis component of d Ai/dt is from the derivative of the current deviation vector d Ai/dt
positive, it indicates that e is in the upper half plane to and the voltage vector dk), as mentioned in Section
the b-axis shown in Fig. 9. If the y-axis component of IV-C. The switching pattern of the two inverters is sed Ai/dt is positive, e is in the lower half plane to the c lected from the cross-current vector i , - i , , the zero
axis. If the z-axis component of d Ai/dt is positive, e is in sequence current io, - io,, the difference between the
the left half plane to the a axis. Therefore, a triangular switching frequencies of the two inverters f, - f,, and the
region is determined by u ( k ) and the x , y , z axes compo- present switching pattern, as shown in Section IV-B. In
nents of d A i / d t as shown in Table IV because the case of dual voltage sources, it is unnecessary to input the
voltage vector expressed in Section IV-A is always se- zero sequence current iol - io,. The switching pattern
lected.
selected by this current controller has a low derivative of
the deviation vector d Ai/dt, and the average values of
v. SWITCHOVER TO QUICK CURRENT RESPONSE
the cross current and zero sequence current are conCONTROL
SCHEME
trolled to zero. In this controller, about 64 kB ROMs and
If Ai becomes larger in transient states, it is necessary 22 comparators are used.
to switch over to the quick response current control
Fig. 11 shows the system configuration of the proposed
system. A voltage vector is chosen in which the d Ai/dt current controller. The upper block is the low harmonic
has the largest opposite direction component to Ai, as current controller shown in Fig. 10. As shown in Section
mentioned in Section 11. Therefore, the voltage vector is V, a conventional hysteresis-type current controller is
same as that of the hysteresis-type current controller. used as the quick current response current control system.
Another tolerance of Ai whose width is larger than that The amplitude of the deviation vector is checked by the
of the former tolerance shown in Fig. 6(b) and Fig. 7(b) is amplitude comparator. If Ai becomes large in transient
set up. Although the current deviation vector Ai exceeds states, the switching pattern is switched over from that of
the tolerance, the voltage vector selected by the quick the low harmonic current controller to that of the quick
current response current control system is output.
response current controller. Therefore, the same quick

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 28, NO. 5, SEPTEMBER / OCTOBER 1992

1028

il - i2
Detection
of e
(Sec. 4.3)

201

- 202

fl - f 2

PY

f,,=lkHz

Ai
region of e

Fig. 10. Current controller to suppress harmonic current.

~i

TiI

Current Controller
to Suppress
HXIIIO&
Current
(Fig.10)

,
~

to drive
circuit

Conventional

f,,=ZOOHz
Fig. 11. System configuration of proposed current controller.

(c)
Fig. 13. Experimental waveforms in steady states: (a) Hysteresis-type
current controller; (b) single-bridge current controller; (c) parallel current controller.

Servo

speed

lOms

Fig. 12. Configuration of experimental system.

current response as the hysteresis-type current controller

is obtained in transient states. In this case, it is not
necessary to control the cross-current vector and the zero
sequence current because the switching patterns of the
two inverters are same, and these currents do not change,
as shown in Tables I1 and 111. The delay time of the
control circuit is about 2 ps.
Fig. 12 shows the experimental 1.5-kW permanent magnet synchronous motor servo system. 1nv.l and Inv.2 are
both single-bridge voltage source inverters each having six
switching devices, respectively. The output terminals are
connected through the current balancers 1. The current
controller can be operated as one of four controllers, i.e.,
a hysteresis-type current controller, the previously proposed current controller for a single bridge, and the
parallel current controller proposed here with either dual
voltage sources or a single voltage source. The motor
ratings are given in Table V.

Fig. 14. Waveform of line-to-line output voltage.

TABLE V
RATINGOF PERMANENT
MAGNETSYNCHRONOUS
MOTOR
Rated output
Rated speed
Rated current
Number of poles
Armature resistance
Armature inductance
Armature linkage flux due to
permanent magnet
Moment of inertia

1.5 kW
1200 r/min
12.6 A (crest value)
4
0.75 t2
5.8 mH

0.35 Wb
50.1 kg . cmz

1029

OGASAWARA et al.: NOVEL CONTROL SCHEME OF A PWM INVERTER

VII. EXPERIMENTAL
RESULTS

f s w = 1.5kH z

A. Steady States
Fig. 13 shows the experimental waveforms in steady
states. Here, Fig. 13(a) is a waveform of the hysteresis-type
current controller, (b) is that of a single-bridge current
controller, and (c) is that of the parallel current controller
with dual voltage sources. The average switching frequencies of the switching devices in the three waveforms are 1
kHz, 600 Hz, and 200 Hz, respectively. Comparing the
hysteresis-type current controller with the parallel current
controller, the average switching frequency of (c) is one
fifth of (a), whereas the magnitude of current ripple of (c)
is smaller than that of (a). Comparing the single-bridge
current controller with the parallel current controller, the
average switching frequency of (c) is one third of (b),
giving the same width of the current ripples.
Fig. 14 shows a waveform of the line-to-line output
voltage in case of the here-proposed parallel current
controller. It is shown that the parallel current-controlled
PWM inverter outputs half of the dc link voltage. From
this waveform, it is easily understood that the switching
frequency or the harmonic current content is reduced
considerably.

B. Transient States
Fig. 15 shows some transient characteristics of the
hysteresis-type current controller, the single-bridge current controller, and the parallel current controller with
both dual and single voltage sources. The average switching frequencies are 1.9 kHz, 1.5 kHz, 420 Hz, and 840 Hz,
respectively. The same quick current responses are obtained. The average values of the cross current and zero
sequence current are regulated to zero.
VIII. CONCLUSION
The authors have proposed a novel current control
scheme for a parallel current-controlled PWM inverter.
The proposed current control scheme was applied to a
1.5-kW PM motor servo system. It was verified experimentally that the switching frequency of the switching devices
and the harmonic current content were reduced considerably in steady states, and the same quick response as the
hysteresis-type current controller was obtained in transient states. The average switching frequency using dual
voltage sources was one half of that when using a single
voltage source. Therefore, dual voltage sources should be
used to attain high performance.
The features of the proposed control scheme are summarized as follows: 1) The switching frequency and harmonic current content are reduced considerably. 2) Highspeed current response is attained in transient states. 3)
The average values of the cross current and zero sequence
current are regulated to zero. 4) The control scheme is
independent ofthe load constants. 5) The use of comparators and ROMs makes the control circuit simple.
This current control scheme is suitable for large-capacity GTO inverters because high performance is attained

(4

(C)

Fig. 15. Transient responses: (a) Hysteresis-type current controller; (b)

single-bridge current controller; (c) parallel current controller (dual
voltage sources); (d) parallel current controller (single voltage source).

even when the switching frequency is limited to a few

hundred Hertz, as shown in the experimental results.
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[l] K. R. Jardan, S. B. Dewan, and G. R. Slemon, General analysis of
three-phase inverters, IEEE Trans. ZGA, vol. IGA-5, no. 6, pp.
672-678, 1969.

IEEE TRANSACTIONSON INDUSTRY APPLICATIONS, VOL. 28, NO. 5, SEPTEMBER / OCTOBER 1992

1030

[2] V. K. Heintze, H. Tappeiner, and M. Weibelzahl, Pulswechselrichter zur Drehzahlsteuerung von Asynchronmachinen, Siemens
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[3] A. Schonung and D. Stemmler, Static frequency changers with
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-1

Satoshi Ogasawara (M87) was bom in Kagawa

Prefecture, Japan, on July 27, 1958. He received
the B.S., M.S., and Dr.Eng. degrees in electrical
engineering from the Nagaoka University of
Technology, Niigata, Japan, in 1981, 1983 and
1990, respectively.
Since 1983, he has been a Research Associate
at the Nagaoka University of Technology. He is
engaged in research on ac motor drives.
Dr. Ogasawara is a member of the Institute of
Electrical Engineers of Japan.

Jin Takagaki was bom in Tochigi Prefecture,

Japan, on December 1, 1962. He received the
B.S. and M.S. degrees in electrical engheering
from the Nagaoka University of Technology,
Niigata, Japan, in 1984 and 1986, respectively.
Since 1986, he has been with Mitsui Petrochemical Industries, Ltd.
Mr. Takagaki is a member of the Institute of
Electrical Engineers of Japan.

Hirofumi Akagi (M87) was bom in Okayama

Prefecture, Japan, on August 19, 1951. He received the B.S. degree from the Nagoya Institute
of Technology, Nagoya, Japan, in 1974 and the
M.S. and Ph.D. degrees from the Tokyo Institute of Technology, Tokyo, Japan, in 1976 and
1979, respectively, all in electrical engineering.
From 1979 to 1991, he was Assistant and then
Associate Professor in the electrical engineering
department at Nagaoka University of Technolow. In 1987. he was a visiting scientist at the
Massachusetts Institute 2 Technolo& for ten month;. Since 1991, he
has been Professor in the electrical and electronic engineering department at Okayama University. He is engaged in research on ac motor
drives, active power filters, and high-frequency inverters.
Dr. Akagi is a member of the Institute of Electrical Engineering of
Japan. He was a recipient of the IEEE/IAS Committee Prize Paper
Awards in 1980, 1983, and 1990, and the IEEE/IAS Best Prize Transactions Paper Award in 1991.

Akira Nabae (F90)was bom in Ehime, Japan,

in 1924. He received the B.E. degree from the
University of Tokyo and the Dr. of Eng. degree
from Waseda University.
He joined Toshiba Corporation in 1951. From
1951 to 1970, he was engaged in the research
and development of converter and inverter technology at Tsurumi Works Engineering Department. From 1970 to 1978, he was involved in the
research and development of power electronics,
especially ac drive systems, at the Heavy Apparatus Engineering Laboratory. From 1978 to 1990, he was a Professor at
the Nagaoka University of Technology. Since 1990, he has been a
Professor Emerius of the university and a Professor at the Tokyo
Institute of Polytechnics.
Dr. Nabae received IEEE/IAS Static Power Converter Committee
Prize Paper Awards in 1980 and 1983, the IEE of Japan Transaction
Paper Award, and the Fukuda Award in 1985.