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SA1,1
VDC
SA1,1
SA2,1
VDC
Vo,1
Io
2nd H bridge
SA1,2
SA2,2
SA1,2
SA2,2
+
-
Vo,2
mth H bridge
VDC
SA1,m
SA2,m
SA1,m
SA2,m
+
-
Vo,m
1988
SA2,1
SA1,k
SA2,k
Vo,k
1
1
0
0
1
0
1
0
VDC
0
0
-VDC
-1
where
SA1,k, SA2,k = 1 means that SA1,k, SA2,k are turned on.
SA1,k, SA2,k = 0 means that SA1,k, SA2,k are turned on.
(k=1, m)
Io
Van
1 2
2 1
2
2
1
3 3 1 2 3 3 2 1
3 3 1
Pattern I
H1
H2
III
II
II
III
H3
III
II
Pattern II
H1
H2
H3
(1)
th
(2)
Io = Ipk sin ( t + )
(3)
PDC , k =
1
T'
/ 2
/ 4
3/4
0
1 2 3 3 2 1 1 2 3 3 2 1
H2
IV
H3
T'
Vo, k I in, k dt
H1
(4)
1989
IV
This can be seen from Fig. 3 and Fig. 4 where the shaded
areas with the same roman number (i.e. I, II ) indicate
equal dc power. For example, the area II in Fig. 3 appears
on both H2 and H3, and both area II begin to commutate at
1 and terminate at 3 with 180 degree apart. In
addition, the area II in H2 is positive quantity, whereas the
one in H3 is negative quantity. Thus, when one recalls
equation (3), it is apparent that both areas II are the same.
From this observation, one can see H2 and H3 provide the
same dc power, and thus, dc power balance can be
achieved within one cycle by choosing the conduction
angles that allow dc power of H1 and H2 (or H3) to be
equal. That is to say,
PDC, 2 + PDC, 3 = 2 PDC, 1
(5)
st
Pbus =
=
vdc
2 '
vdc Ipk
I pk sin( ) d
(6)
(cos( 2 + ) + cos( 2 ))
Pbus
2 = cos 1
2 vdc Ipk cos
(7)
+1
vdc Ipk
2
0
+ 3 '
Pbus =
vdc Ipk
sin( )d
+1 '
(8)
(9)
or
3 = cos
(2 cos 2 cos 1 )
H1
H2
VI
V
VII
H3
V
H4
VI
VII
(11)
PDC, 2 = PDC, 4
(12)
(13)
or specifically,
Pbus,2 =
I pk vdc
2
I pk vdc
2
{A cos + B sin }
(14)
{A cos B sin }
(15)
T / 4
T / 2
3 T / 4
T
1 2 3 4 4 3 2 1 1 2 3 4 4 3 2 1
Pbus,1 =
sin( )d + K
sin( )d +
(10)
1990
Pbus,1 = Pbus, 2
(16)
B sin = 0
(17)
vdc Ipk
A cos
2
(18)
area I = area IV
800
400
0
-400
-800
4.17
8.33
12.5
800
400
0
400
800
16.67
4.17
8.33
Time [ms]
Time (ms)
12.5
16.67
1000
3
1 .10
100
10
1
0.1
60
300
540
780
1260
1020
100
10
1
0.1
0.01
Frequency [Hz]
60
300
540
780
Frequency [Hz]
1020
1260
0.5 cycle
639.0
1087
1269
0.5 cycle
999.8
1273
726.8
1 cycle
954.8
863.6
1176
1 cycle
999.8
1000
1000
1.5 cycle
998.0
998.4
998.4
1991
500
0
500
1000
1000
1000
4.17
8.33
Time (ms)
12.5
500
0
500
1000
16.67
4.17
8.33
Time [ms]
12.5
16.67
1000
1000
100
10
1
0.1
60
300
540
780
1020
1260
100
10
1
0.1
0.01
Frequency [Hz]
60
300
540
780
1020
1260
Frequency [Hz]
th
0.5 cycle
1 Hbridge
1264
1 cycle
1236
1072
768.9
1.5 cycle
1139
916.6
935.3
1023
2 cycle
1002
1002
1002
1002
# of cycle
st
4 Hbridge
594.4
0.5 cycle
1 Hbridge
1273
1 cycle
1000
# of cycle
930.5
1001
th
4 Hbridge
727.6
1000
V. CONCLUSION
ACKNOWLEDGMENT
1992
REFERENCES
[1] L. M. Tolbert, F. Z. Peng and T. G. Habetler,
Multilevel Converters for Large Electric Drives,
IEEE Transactions on Industry Applications, Vol. 35
[2]
[3]
[4]
[5]
[6]
1993
[7]
[8]
[9]
[10]