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end func;
--*===================================== END Data Latch
--Before we define the master-slave D-flipflop, we must
--first define an inverter entity; as we will need
--inverters to build the structural core D-flipflop.
library ieee;
use ieee.std_logic_1164.all;
entity notGate is
port( inPort : in std_logic;
outPort : out std_logic);
end notGate;
-architecture func of notGate is
begin
outPort <= not inPort;
end func;
--*===================================== END NOT Gate
--Finally we define the Master-Slave Data flipflop circuit.
--After this we are done as it is the top-level of our design
library ieee;
use ieee.std_logic_1164.all;
entity ms_Data_ff is
port( clk, D : in std_logic;
Q, notQ : out std_logic);
end ms_Data_ff;
-architecture func of ms_Data_ff is
--import the inverter entity as a component
component notGate is
port( inPort : in std_logic;
outPort : out std_logic);
end component;
--import the D-latch entity as a component
component D_latch is
port(clk, D : in std_logic;
Q, notQ : out std_logic);
end component;
--interconnecting wires carrying signals to the components
--we define a dummy signal because all ports must be wired
signal invOut1, invOut2, Dout, dummy : std_logic;
begin
G1: notGate port map(clk, invOut1);
G2: notGate port map(invOut1, invOut2);
G3: D_latch port map(invOut1, D, Dout, dummy);
G4: D_latch port map(invOut2, Dout, Q, notQ);
end func;
----------------------------------------------------------END
----------------------------------------------------------END