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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 6, JUNE 2009

Single-Stage AC/DC BoostForward Converter

With High Power Factor and Regulated Bus
and Output Voltages
Dylan Dah-Chuan Lu, Member, IEEE, Herbert Ho-Ching Iu, Senior Member, IEEE, and Velibor Pjevalica

AbstractUnlike existing single-stage ac/dc converters with

uncontrolled intermediate bus voltage, a new single-stage ac/dc
converter achieving power factor correction (PFC), intermediate
bus voltage output regulation, and output voltage regulation is
proposed. The single-power-stage circuit is formed by integrating
a boost PFC converter with a two-switch-clamped forward converter. The current stress of the main power switches is reduced
due to separated conduction period of the two source currents
flowing through the power switch. A dual-loop peak-current-mode
controller is proposed to achieve PFC and ensure independent
bus voltage and output voltage regulations. Experimental results
on a 24-V/100-W hardware prototype are given to confirm the
theoretical analysis and performance of the proposed converter.
The converter has conversion efficiency ranging from 86% to 92%
at full-load condition.
Index TermsAC/DC converter, power factor correction (PFC),
single-stage.

I. I NTRODUCTION
INGLE-STAGE power-factor-corrected (S2 PFC) ac/dc
converters, which combine a power factor correction (PFC)
circuit and a dc/dc regulator circuit and share a common set of
active power switches, have been introduced [1][7]. The aims
are to reduce the converter size, control circuitry, and, thus,
cost. Three critical problems are found in S2 PFC converters:
1) extra current stress on the switch, as it has to handle currents
from the line input voltage and the bus voltage simultaneously,
hence lowering conversion efficiency; 2) high voltage stress on
power semiconductor devices due to uncontrolled intermediate
bus voltage; and 3) voltage spike on the main switch caused
by the leakage energy for transformer-isolated rear dc/dc stage.
Therefore, the S2 PFC approach is only attractive for low-power
applications.
Various approaches have been introduced to solve partly
the aforementioned problems [8][24]. Variable switching frequency [8], [9] limits the input power pumping to the bus
capacitor by increasing the switching frequency at decreasing

Manuscript received January 14, 2008; revised January 13, 2009. First
published February 6, 2009; current version published June 3, 2009.
D. D.-C. Lu is with the School of Electrical and Information Engineering,
The University of Sydney, Sydney, NSW 2006, Australia (e-mail: dylan.lu@
ee.usyd.edu.au).
H. H.-C. Iu is with the School of Electrical, Electronic and Computer
Engineering, The University of Western Australia, Perth, WA 6009, Australia.
V. Pjevalica is with JP Srbijagas, 21000 Novi Sad, Serbia.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2009.2014304

load and vice versa. Bulk capacitor voltage feedback [10][12]

can effectively reduce the voltage stress by reducing the charging current in the boost inductor when the load is decreasing.
However, dead angle of input current occurs, resulting in poor
power factor and reduced available power from the line. By
adding a parallel PFC converter with the diodecapacitor filter,
the bus voltage is clamped at the peak input voltage, and input
current can be designed to comply with the IEC 61000-3-2
requirement [13]. However, the bus voltage still varies largely
with the input voltage. Therefore, capacitance has to be large
enough for the hold-up time requirement at low-line condition.
The load current feedback technique is introduced [14] in which
the load information is brought forward to the input stage,
controlling the input current directly. At any time, the switch
handles current from either the line input voltage or the storage
capacitor. However, the high-input-current harmonics problem
and large variation of the bus voltage against the line voltage
still exist. Operating both stages in discontinuous conduction
mode (DCM) may reduce the voltage stress, but it may not
favor high-output-current/power applications [11], [15], [16].
Direct power transfer is introduced [11], [17][23] to place
an auxiliary coupled winding in series with the charging path
of boost inductor, stealing energy to output directly after
the first power process. The voltage stress is reduced rapidly
while maintaining high power factor. Conversion efficiency is
also improved. However, there is no control of the bus voltage
against the line voltage. The authors in [5] and [24] attempted to
control the bus voltage and output voltage in S2 PFC converters,
but due to the integrated structure, the currents from both input
sources (ac mains and storage capacitor) cannot be separated.
Hence, the current stress issue remains. Moreover, since the
duty cycle varies largely for universal input applications, an
extra range switch is needed.
In this paper, a new S2 PFC converter derived from novel integration of boost converter and two-transistor-clamped forward
converter is proposed. In summary, the proposed converter has
the following advantages.
1) The proposed S2 PFC converter gives simultaneous PFC,
bus voltage regulation, and fast output regulation, which
are not possible in existing S2 PFC converters.
2) No additional switches, such as a range switch, are
needed to implement universal input range applications.
3) The current stress of the two power switches is lower
than that of the single-switch (or multiple-switch) S2 PFC
converter circuits.

0278-0046/$25.00 2009 IEEE

LU et al.: CONVERTER WITH HIGH POWER FACTOR AND REGULATED BUS AND OUTPUT VOLTAGES

Fig.1.

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Proposed boostforward S2 PFC ac/dc converter.

4) High power factor, as there is no deadband of input

current around the zero crossing of the line input voltage.
5) Standby mode is possible, which saves power.
II. P ROPOSED C IRCUIT AND I TS O PERATION
A. Circuit Description
The proposed boostforward S2 PFC converter is shown in
Fig. 1. It consists of an input inductor L1 , a two-transistorclamped (S1 and S2) forward converter with transformer T1,
and a storage capacitor CB . The boost inductor L1 is used to
shape the input current for PFC and to feed CB . Transformer
T1 with turns ratio of N :1 is used to transfer energy from CB
to the output load at transistor turn-on period. Bus capacitor CB
serves as a storage element to absorb power imbalance between
the input and the output and maintain the output voltage to be
constant. Diodes D1 and D2 are used to recycle the leakage
energy in T1 back to CB , provide a path for T1 reset, and clamp
the drain-to-source voltages of S2 and S1 to bus voltage VB . D3
is a bypass diode for charging of CB to provide the necessary
housekeeping power at startup. Once VB rises above the peak
input voltage, D3 is reverse biased.
B. Circuit Operation
To simplify the analysis of operation, it is assumed that all
semiconductor devices are ideal. The capacitances of CB and
Co are so large that the ripple voltage on them is negligible;
VB and Vo are constant dc voltage sources. The rectified input
voltage |vin | is essentially constant within each switching cycle,
as the switching frequency fs (= 1/Ts ) is much higher than
the line frequency. Finally, the boost inductor L1 works in
DCM, whereas the primary inductance of forward transformer
Lp operates in continuous conduction mode. The modes of
operation are explained as follows.
Mode 1 (T0 T1 ): Both switches S1 and S2 are closed. As
the intermediate bus voltage VB is higher than the rectified input
voltage |vin | at all times, the bridge diodes are reverse biased in
this mode. Therefore, inductor L1 is not charged, and iL1 = 0.
Capacitor CB is discharged through S2 Lp S1. Energy is
being transferred to the output through T1. A voltage (VB /N
Vo ) is applied on Lo , and it is charged up linearly. This period
is for regulation of Vo .

Mode 2 (T1 T2 ): Mode 2 is initiated by turning off S2

while S1 remains in ON state. The parallel capacitance of S2
is charged up so that the drain-to-source voltage of S2, vDS2 ,
rises toward VB until it is clamped by VB . Because ip cannot
sustain a sudden change of current direction, D1 is turned on
to maintain the current flow in T1. The voltage applied across
the primary winding of T1 is thus zero (assuming that D1
has zero forward voltage drop). Namely, T1 is freewheeling
within this interval, and the rate of change of ip is zero. The
secondary winding of T1 is also at 0 V. Therefore, D4 is reverse
biased, and D5 conducts to carry the discharge current of Lo .
Meanwhile, a voltage |vin | is applied on L1 , and it is charged
up linearly. This period is for PFC and regulation of VB .
In contrast to existing S2 PFC converters, the proposed converter has separate operation modes (modes 1 and 2) to separate
currents from input line voltage and bus capacitor. This reduces
current stress on the power switches, as illustrated in [19].
Mode 3 (T2 T3 ): Mode 3 begins when S1 is also turned
off. The parallel capacitance of S1 is charged by ip . The drainto-source voltage of S1, vDS1 , rises toward VB . When vDS1
rises slightly above VB , D2 is forward biased. vDS1 is clamped
at VB , and vDS2 is reduced to VB |vin |. Diode D2 provides
the path to maintain the discharge current of L1 , and the energy
in L1 is dumped to CB through Lp and D2 . T1 is reset through
the same path. Lo continues to discharge, and Co assists to
sustain Vo . This period is for T1 reset and energy transfer to
storage elements.
After some time, S1 and S2 turn on again to begin the next
switching cycle, and the operation described earlier will repeat.
III. C ONTROL
Fig. 2 shows the simplified schematic of the proposed dualloop current mode control for the proposed converter. Both
loops are triggered by the same clock (CLK) to have synchronized ON pulse. When a clock pulse is generated, both S1 and
S2 go to high state, and CB delivers energy to the output load.
The first loop (with E/A 1 and PWM 1) is used for output
voltage regulation. The output voltage Vo is sensed by the
inverting input of the error amplifier E/A 1 with compensation
network, and an error control voltage vc1 is generated. vc1 is
compared to the switch current of S1 by comparator PWM 1
to produce the desired off duty cycle for S2 through the D-type
flip-flop (FF1). The second loop (with E/A 2 and PWM 2) is

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Fig. 2. Dual-loop current-mode controller for the proposed converter.

Because of peak-current-mode control, the peak input currents

at different input voltages are the same, so
|vin,H |
|vin,L |
D1a =
D2a .
2L1
2L1

(3)

Applying voltagesecond on L1 in both conditions, we obtain

Fig. 3. PFC capability under peak-current-mode control.

used for PFC and bus voltage regulation. The bus voltage VB
is detected by the inverting input of the error amplifier E/A 2
with compensation network, and an error control voltage vc2
is generated. vc2 is summed with the inductor L1 current and
compared to ground by comparator PWM 2 to produce the
desired off duty cycle for S1 through the D-type flip-flop (FF2).
Duration of S1 is longer than that of S2 (Fig. 3). When current
flowing through R2 (in Fig. 1), which represents peak inductor
current iL1 , is reached, point B is pulled to negative, and S1 is
turned off. The converter then enters mode 3.
In the design of the controller, on the one hand, the compensation network by E/A 2 is of slow response, which has a
cutoff frequency of around 1020 Hz, to avoid the 100-Hz ac
ripple from the bus capacitor being amplified and cause input
current distortion eventually. On the other hand, E/A 1 is of fast
response to provide tight output regulation.
IV. PFC C APABILITY
Let the input line voltages near zero crossing and near the
peak value be |vin,L | and |vin,H |, respectively. The instantaneous average input currents, as shown in Fig. 3, at low and
high line voltages are given, respectively, by
iin,L =

|vin,L |
D1a T (D1a + D1b )
2L1

(1)

iin,H =

|vin,H |
D2a T (D2a + D2b ).
2L1

(2)

D1b = D1a

L1 + Lp
|vin,L |

VB |vin,L |
L1

(4)

D2b = D2a

L1 + Lp
|vin,H |

.
VB |vin,H |
L1

(5)

Substituting (3) and (4) into (1), we have



L
VB + |vin,L | Lp1
|vin,H |
.
iin,L =
D2a T
2L1
VB |vin,L |

(6)

Similarly, we have the input current for higher line voltage



L
VB + |vin,H | Lp1
|vin,H |
iin,H =
D2a T
.
(7)
2L1
VB |vin,H |
As |vin,H | > |vin,L |, comparing (6) and (7), we can conclude
that iin,H > iin,L . As the instantaneous average input current
follows the input line voltage, the converter achieves PFC
automatically under peak-current-mode control.
V. E XPERIMENTAL V ERIFICATION
To verify the feasibility of the proposed boostforward
S2 PFC ac/dc converter, a laboratory prototype with the
following specifications has been implemented and tested:
|vin | = 100240 Vac, Vo = 24 Vdc, Po = 100 W, and fs =
1/T = 50 kHz. The key circuit parameters are listed as follows: L1 = 400 H, Lp = 750 H, N = 4, Lo = 800 H,
CB = 470 F/450 V, Co = 4700 F/35 V, S1-IRF830, S2IRF840, D1 = D2 UF5407, D3 1N4007(optional); D4 =
D5 BYW29, R1 = 22 /2 W, and R2 = 47 /2 W.
Fig. 4 shows the switching waveforms of inductor current
iL1 (upper) and diode D1 current iD1 (lower). The input voltage

LU et al.: CONVERTER WITH HIGH POWER FACTOR AND REGULATED BUS AND OUTPUT VOLTAGES

Fig. 4. Switching waveforms of (upper) iL1 and (lower) iD1 . Scale: 4 A/div;
4 A/div.

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Fig. 6. Input voltage vin and filtered input current iin at 100 V(rms) and full
load. Scale: 70 V/div; 0.33 A/div.

Fig. 7. Measured power factor and conversion efficiency of the proposed

converter at full load.

Fig. 5. Input voltage vin and filtered input current iin at 240 V(rms) and full
load. Scale: 190 V/div; 0.25 A/div.

and filtered input current of the converter at 240- and 100-V line
voltages and at full-load condition are shown in Figs. 5 and 6,
respectively. The measured power factor is above 0.96, and
efficiency of the converter is above 86% at full-load condition,
with maximum efficiency of 92%, as shown in Fig. 7. The
converter regulates at VB = 400 V (through mode 2) and Vo =
24 V (through mode 1) for the entire line and load conditions.
Finally, Fig. 8 shows that the standby mode feature is made
possible in the proposed converter by keeping S2 closed and
allowing the current from CB to regulate Vo through switching
of S1. Once VB is below 350 V, S2 is open to allow input current
to supply energy to CB .
VI. C ONCLUSION
This paper has presented, with verifications of experimental
results, the single-stage PFC (S2 PFC) converter conceptPFC
and regulation of bus and output voltages at the same time.

Fig. 8. Standby mode feature of the proposed converter.

The key idea is to construct the power circuit so that the

current from two input sources (ac mains and bus capacitor)
can be separately controlled. Therefore, although the two power
processing stages share the same power switches, only one of
the two currents passes through the switches at a time within
each switching period. Current stress on power switches is

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also reduced as a result. Moreover, by deliberately restricting

the current from ac mains, the converter can work at standby
mode with energy saving, which can hardly be implemented in
existing S2 PFC converters.
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Dylan Dah-Chuan Lu (S00M04) received the

B.Eng.(Hons.) and Ph.D. degrees in electronic and
information engineering from The Hong Kong Polytechnic University, Kowloon, Hong Kong, in 1999
and 2004, respectively.
In 2003, he was with PowerELab Ltd., a spinoff company at The University of Hong Kong, as a
Senior Engineer. His major responsibilities included
project development and management, circuit design, and contribution of research in the area of
power electronics. He is currently a Lecturer with the
School of Electrical and Information Engineering, The University of Sydney,
Sydney, Australia. He has published a number of international conference and
journal papers on the analysis and design of power electronic circuits. He is the
holder of one U.S. patent. His research interests include modeling, synthesis,
and computer-aided design of power converters, dcdc converters for VRM
applications, electronic ballast, controls, power-factor-correction circuits, softswitching techniques, and renewable electrical energy systems.

Herbert Ho-Ching Iu (S98M00SM06) received the B.Eng.(Hons.) degree in electrical and

electronic engineering from the University of
Hong Kong, Hong Kong, in 1997, and the Ph.D.
degree from the Hong Kong Polytechnic University,
Hong Kong, in 2000.
Since 2002, he has been with the School of Electrical, Electronic and Computer Engineering, University of Western Australia, Perth, Australia, where
he was initially a Lecturer and is currently an Associate Professor. He was a Visiting Lecturer with
the University of Reims Champagne-Ardenne, Reims, France, in 2004, and
a Visiting Assistant Professor with the Hong Kong Polytechnic University
in 2006. He is the author of more than 90 published papers. He currently
serves as an Editorial Board Member for the Australian Journal of Electrical
and Electronics Engineering and a Guest Editor for Circuits, Systems and
Signal Processing. He is a Coeditor of Control of Chaos in Nonlinear Circuits
and Systems (World Scientific, 2009). His research interests include power
electronics, renewable energy, nonlinear dynamics, current sensing techniques,
TCP dynamics, and computational intelligence.
Dr. Iu is an Associate Editor for the IEEE Circuits and Systems Society
Newsletter.

Velibor Pjevalica was born in Novi Sad, Serbia, in

1969. He received the M.Phil. and Ph.D. degrees
from the University of Technical Sciences, Novi Sad,
in 1999 and 2008 respectively.
He was with the Hong Kong Polytechnic University, where he worked with Prof. M. Tse. He is
currently with JP Srbijagas, Novi Sad, Serbia. His
research interests include power converters, control,
chaos, and bifurcations.