IncorrectQuestion

Ll thRISC has the following features except

for

A. Main Memory

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Pentium processors employs how many
types of pipelines?

B. Make good use of registers

C. Cache
B. 14
D. Instructions reequire multiple clock
cycles to execute

Question 3
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D. 5

This helps identify possible interruptions to

C. Utilize the compiler extensively

the normal flow of instructions through U

and V pipelines.
A. 20

A. Reduce accesses to main memory

D. Cache
C. 2

Question 2
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This is examined first whenever the

A. Pentium

processor tries to read data from the main

Question 5

memory.

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B. Brand Prediction

What type of dependency exists between

these two instructions?

B. Instructions

SUB DX, CX
ADD BX, DX
C. Pipelining

D. Registers

B. write after read

A. read after write

A. No bus cycle requested

D. Ti

C. write after write

IncorrectQuestion

C. TD

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This bus state indicates that no bus cycle
is currently running.
D. read after read

B. T12

D. Ti
IncorrectQuestion

A. T1

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Which of the following is not part of the

B. T12

transitions between bus cycle states?

IncorrectQuestion

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B. Go back to T1 if a new request is

A. T1

This bus cycles require additional decoding

and use the byte enable outputs for

pending

selection.
C. TD
C. Valid adddress is output on the address

C. Burst Cycle

lines

Question 8
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D. Begin second bys cycle

The bus will enter this state when a second

bus cycle is started before the first one
completes.

A. Bus Cycle States

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D. Special Cycle

<p>These are extra clock cycles

generated when BDRY is not low
during T2 state.</p>
B. Single Transfer Cycle

These are extra clock cycles generated

when BDRY is not low during T2 state.

IncorrectQuestion

10

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D. Special Cycle

A. Single Transfer Cycle

B. Wait states
C. Bus Cycle State

This cycle transfers bytes that are noncacheable between the processor and
memory.

A. Idle States

IncorrectQuestion

13

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C. Bus Cycle State
C. Dead states

D. Special Cycle
D. Bus cycle states

<p>During this operation, no

other devices may take over
control of the processsor
buses.</p>
During this operation, no other devices
may take over control of the processsor
buses.

A. Single Transfer Cycle

Question 12
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C. Atomic Operation

This cycle is used by the cache for line

B. Burst Cycle

loads and writebacks.

D. Branch Prediction

IncorrectQuestion

11

B. Burst Cycle

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A. Locked Operation

This put its buses into a high-impedance

state, beginning with the next clock cycle.
B. BOFF
B. Bus Snooping
D. Bus Hold
C. Shutdown

Question 14
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B. BOFF

This is a special type of counter variable

Question 17

that must be read, updated, stored in one

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single, uninterruptable operation.

C. Shutdown

This cycle is run when the processor

encounters the HLT instruction.

D. Semaphor
A. HLT

C. Shutdown

Question 16

A. HLT

B. Atomic Access

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A. Locked Operation

This completes the current bus cycle and

then tri-states its buses.
B. BOFF

C. Atomic Operation

D. Bus Hold
D. Bus Hold

IncorrectQuestion

15

A. HLT

IncorrectQuestion

18

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D. Pentium IV
B. Bus Snooping

This cycle is run if the Pentium detects an

internal parity error.

Question 21
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A. Inquire Cycles

Which among the choices is not one of the

D. Bus Hold

restrictions placed on a pair of integer

instructions attempting parallel execution?
D. Cache Coherency
C. Shutdown
D. Neither instruction may contain both
IncorrectQuestion

20

immediate data and a displacement value

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A. HLT

Under special circumstances, this is

capable of executing two integer or two

B. No data dependencies may exist

floating-point instructions simultaneously.

between them

B. BOFF
C. Pentium III
IncorrectQuestion

A. Both must be simple instructions

19

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In this cycle the Pentium processor is able

B. Pentium II

to watch the system bus in a

C. Postfixed instructions may only execute

multiprocessor system.

in the U pipeline
A. Pentium

C. Pipelined Cycles

IncorrectQuestion

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22

<p>This data dependency exists

if the second instruction reads
an operand written to it by the
first instruction.</p>

B. write after write

C. D2

C. write after read

IncorrectQuestion

This data dependency exists if the second

instruction reads an operand written to it by
the first instruction.

25

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<p>

B. write after write

Pentium uses this scheme to avoid

A. read after read

bubbles in the pipeline, where no work is

done as the pipeline stages are reloaded.

C. write after read

Question 24
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D. branch instruction

<p>

A. read after read

This stage in pipelining is used to write the

results of the completed instruction and

B. branch target buffer

verify conditional branch instruction

predictions.

D. read after write

A. branch prediction
B. D1
IncorrectQuestion

23

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C. dynamic branch prediction

This data dependecy exists if both

instruction write to the same operand

D. read after write

D. EX

IncorrectQuestion

A. WB

26

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B. 10

<p>

C. access time

The history bits are initially set to 01, what

will be the history bits after this sequence;
Taken->Taken->Not Taken->Not Taken-

C. 11

Question 29

>Not Taken->Taken?

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D. 01

C. 11

This cache organization uses larger tags

and does not select an entry based on
index bits.

A. 00

A. 00

B. set associative cache

Question 28

B. 10

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C. direct-mapped cache

This specifies the percentage of hits to

total cache accesses.
D. 01

D. single-mapped cache
D. hit ratio

IncorrectQuestion

27

A. fully associative cache

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The history bits are initially set to 10, what

A. hit

will be the history bits after this sequence;

Question 30

Taken->Taken->Not Taken->Not Taken>Not Taken->Taken?

B. miss

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This cache organization uses a portion of

D. Invalid

the incoming physical address to select an

IncorrectQuestion

entry.

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33

This is the FPU pipeline stage were

B. Exclusive

memory data are converted into floating-

C. direct-mapped cache

point format and write the operand to

floating-point file.
C. Shared

D. single-mapped cache

C. X2
IncorrectQuestion

A. fully associative cache

32

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This state of cache line may invalidate the

D. WF

copies in the other cache of the current line

during once a write occur.
B. set associative cache

A. EX
D. Invalid

Question 31

B. X1

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C. Shared
This state of cache line has been modified

IncorrectQuestion

and is only available in a single cache.

34

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A. Modified
A. Modified

What is the average access time for a

system that contains 15ns cache and 75ns
RAM if the hit ration is 0.89?

B. Exclusive

A. 276.9ns
B. 19.56ns

A. Bus Snooping

B. 12103.11ns
IncorrectQuestion

36

C. MESI

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D. 1211.4ns

This translate linear addresses into

physical addresses.
B. Cache Coherency

C. 23.25ns

D. TLT
D. Translation lookaside buffer

Question 35

B. TLS

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IncorrectQuestion

What is the average access time for a

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system that contains 18ns cache and 78ns

RAM if the hit ration is 0.98?

38

What happens during a cache miss?

A. TLB

A. a copy is sent to the pipeline very

A. 1695.36ns

C. TLC

C. 84.35

IncorrectQuestion

quickly, usally within one clock cycle.

37

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This is a Pentium's mechanism that is used
D. 1825.36.4ns

to maintain cache coherency in its data

cache.

D. a copy of the instruction or data from

main memory is read to the cache

C. an external cache is examined next

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D. Speculative Loading

This is used to detect and correct single bit

errors on the data bus and detect bit errors
on the address bus and control signals.
B. the processor will not be forced to go to

A. Dynamic Execution

external memory
A. Error Detection
B. Pipelining

Question 39
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B. Parity Check

All of these are the reasons why Pentium

IncorrectQuestion

Pro outperformed Pentium except for:

42

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C. Register Renaming

This unit is used to determine which

original 1A-32 register must be updated in

A. superpipeline

program order.
D. Error Checking and Correction
B. internal level-2 cache

A. Fetch-Decode Unit

Question 41
D. dual independent bus

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C. Dispatch-Execute Unit

This technology is used to keep instruction

pipeline busy.
C. five additional address lines

B. Retire Unit
C. Speculative Execution

Question 40

D. MMX execution Unit

A. SIMD
IncorrectQuestion

43

A. Data Prefetch Logic

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In this unit the reservation station controls

IncorrectQuestion

the flow of data through the integer,

floating-point, MMX, and load/store unit

C. Streaming SIMD Extensions

46

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This allows the use of minimal logic in each
stage and a higher clock speed for the
pipeline.

D. MMX execution Unit

B. Speculative Execution

B. Superpipeline
A. Fetch-Decode Unit

IncorrectQuestion

45

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This technology enables one instructions to
B. Retire Unit

D. FPU Pipelining

perform its work on multiple operands

simultaneously.
C. Hyper-Pipelined

C. Dispatch-Execute Unit

D. Streaming SIMD Extensions

A. Pipelining
IncorrectQuestion

44

C. Superscalar Machines

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This is used to preload the data cache with

Question 47

data the application is expected to need.

B. SSE

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This is used to save decoding time if the

D. Speculative Loading

same instruction is fetched in the future.

A. MMX Technology

A. Pentium

C. Predication

D. Rapid Execution Engine

Question 49

A. Brand Prediction

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This processor allows true simultaneous
execution of two threads at the same time
C. Dual Independent Bus

D. Looping technique

D. Xeon
B. Exectution Trace Cache

B. Loop Unrolling

B. Itanium

Question 48

Question 51

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1 / 1 pts

This processor supports hyperthreading.

C. Celeron

In this technique data is preloaded before it

is needed.

D. Penitum IV
A. Pentium

C. Streaming SIMD Extensions

Question 50

B. Speculative Execution

C. Pentium III

1 / 1 pts
This is used to duplicate the instructions
B. Pentium II

found within a loop.

A. Data Prefetch Logic

A. 60

C. Floating point

D. Speculative Loading
IncorrectQuestion
IncorrectQuestion

52

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Compute for the number of clock cycles of
the following instructions in UV pipelining.
MOV AX, 02

53

D. DMA

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Compute for the number of clock cycles of
15 instructions in a 4-stage pipelining.
B. Cache

B. 60

MOV BX, 03

A. Instruction Cache

MOV CX, 04
ADD AX, CX
INC BX

D. 10

SUB BX, AX

IncorrectQuestion

MOV CX, BX

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DEC CX

C. 19

55

This is the FPU pipeline state were result

are rounded and written to floating-point
register file.

C. 12
A. 18
D. WF
B. 10

Question 54
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D. 9

To reduce the number of accesses to main

memory in RISC,one of the following has
been added to its design.

B. X1

C. X2

What is the Hit Ratio for a system that

contains 10ns cache and 80ns RAM with
14ns average access time?
X0

A. EX
0.96
ER
IncorrectQuestion

56

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0.94

Compute for the number of clock cycles of

IncorrectQuestion

15 instructions in non-pipelining.

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Which of the following is not one of the

0.95

cache instructions?

C. 17

0.97

INVD

B. 60

IncorrectQuestion

58

WBINVD

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A. 10

Which of the following is not part of the

floating point pipeline?
INVDTLB
D. 45
EX
INVLPG
IncorrectQuestion

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59

57
WF

IncorrectQuestion

60

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In this technique, the true and false
sections of the code are both executed,
along with the condition testing code in

two for the operand and one for the

Load Unit

destination

order to keep the pipeline busy.

Question 63
two for the operand and one for the opcode
dynamic execution

What is true about SSE?

two for the opcode and one for the

predication

speculation

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Cache management instructions

destination

Question 62

Set of 1028-bit XMM registers

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loop unrolling

Question 61

The following are parts of the dispatch-

Capable of storing five 32-bit floating point

execute unit of the Pentium III, except for?

numbers

Reservation Unit
Seven additional MMX instructions

1 / 1 pts
Which of the following is the division of the
micro-ops?
Store Unit

IncorrectQuestion

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two for the source operand and one for the
destination

Instruction Cache

64

Given the following instructions, compute

This architecture allows parallel instruction

for the number of clock cycles using hyperpipeline.

execution of multiple instructions.

MOV AX 01

Superscalar machines

MOV BX, 02
ADD AX, BX
super-pipeline

INC AX
INC BX
HLT

Pipelining

64
hyper-pipeline

23

17

40

IncorrectQuestion

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65