Where We Are in This Course Right Now

ECE 152

So far:

Introduction to Computer Architecture

We know what a computer architecture is

We know what kinds of instructions it might execute
We know how to perform arithmetic and logic in an ALU

Processor Design: Datapath and Control

Copyright 2005 Daniel J. Sorin
Duke University

Now:
We learn how to design a processor in which the ALU is just one
component
Processor must be able to fetch instructions, decode them, and
execute them
There are many ways to do this, even for a given ISA

Slides are derived from work by

Amir Roth (Penn)
Spring 2005

Next:
We learn how the processor interacts with memory

2005 Daniel J. Sorin

from Roth

This Unit: Processor Design

Application
Compiler
CPU

Firmware
I/O

Memory
Digital Circuits
Gates & Transistors

2005 Daniel J. Sorin

from Roth

Readings
Patterson and Hennessy

Datapath components and timing

OS

ECE152

Chapter 5

Registers and register files

Memories (RAMs)
Clocking strategies

Read this chapter carefully

It has many more examples than I can cover in class

Mapping an ISA to a datapath

Control
Single-cycle control
RAM/PLA
Multi-cycle control
RAM/PLA
Micro-programmed control
Implementing exceptions using control

ECE152

2005 Daniel J. Sorin

from Roth

ECE152

So You Have an ALU

Datapath and Control

datapath

A processor is just a big finite state machine (FSM) that

interprets some ISA

fetch

Start with one instruction

PC

add $3,$2,$4
ALU performs just a small part of execution of instruction
You have to read and write registers
You have have to fetch the instruction to begin with

Need some sort of memory interface

What about branches?

Need some hardware for that, too
ECE152

Building a Processor for an ISA

Data
Memory

Datapath: registers, memories, ALUs (computation)

Control: which registers read/write, which ALU operation
Fetch: get instruction, translate into control
Fetch Decode Execute cycle

2005 Daniel J. Sorin

from Roth

ECE152

Datapath for MIPS ISA

[material in class]

2005 Daniel J. Sorin

from Roth

Register
File

control

What about loads and stores?

2005 Daniel J. Sorin

from Roth

Insn
memory

[material in class]

ECE152

2005 Daniel J. Sorin

from Roth

ECE152

ECE 151 Review: Register

Uses of Registers
datapath

Q0

D0
DFF
D1

fetch

Q1

DFF
DN-1
WE
CLK

PC

Insn
memory

Register
File

Data
Memory

QN-1
DFF

control

WE

Register: DFF array with shared clock, write-enable (WE)

Notice: both a clock and a WE (DFFWE = clock & registerWE)
Convention I: clock represented by wedge
Convention II: if no WE, DFF is written on every clock
2005 Daniel J. Sorin
from Roth

ECE152

What About the ISA Registers?

A single register is good for some things

PC: program counter
Other things which arent the ISA registers
Think about some examples from within the ALU
2005 Daniel J. Sorin
from Roth

ECE152

10

A Register File With Four Registers

RS1VAL

RDVAL
Register File

RS2VAL
RD = dest reg

WE

RD RS1 RS2

RS = source reg

Register file: the ISA (architectural, visible) registers

Two read ports + one write port
Maximum number of reads/writes in single instruction (R-type)

Port: wires for accessing an array of data

Data bus: width of data element (MIPS: 32 bits)

Address bus: width of log2 number of elements (MIPS: 5 bits)
Write enable: if its a write port
M ports = M parallel and independent accesses

2005 Daniel J. Sorin

from Roth

ECE152

11

2005 Daniel J. Sorin

from Roth

ECE152

12

Add a Read Port for RS1

Add Another Read Port for RS2

RS2VAL

RS1VAL

RS1VAL

RS1

RS2 RS1

Output of each register into 4to1 mux (RS1VAL)

Output of each register into another 4to1 mux (RS2VAL)

RS1 is select input of RS1VAL mux

2005 Daniel J. Sorin

from Roth

RS2 is select input of RS2VAL mux

ECE152

13

Add a Write Port for RD

2005 Daniel J. Sorin

from Roth

ECE152

14

Another Read Port Implementation

[material in class]

RDVAL
RS2VAL

RS1VAL

WE

RS2 RS1

RD

Input RDVAL into each register

Enable only one registers WE: (Decoded RD) & (WE)

What if we needed two write ports?

2005 Daniel J. Sorin
from Roth

ECE152

15

2005 Daniel J. Sorin

from Roth

ECE152

16

Register File With Tri-State Read Ports

Clocking Methodology
A single register (e.g., PC)

RDVAL
RS1VAL

Written on clock edge

Read continuously (new value available after write occurs)

What about a register file?

RS2VAL

WE

RD

2005 Daniel J. Sorin

from Roth

RS1

ECE152

Written on clock edge

Read on clock edge
On non-writing clock edge (otherwise races would occur)
Dont worry about why this is for now

RS2

17

2005 Daniel J. Sorin

from Roth

ECE152

18