www.ietdl.

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Published in IET Circuits, Devices & Systems
Received on 9th December 2010
Revised on 18th March 2011
doi: 10.1049/iet-cds.2010.0431

ISSN 1751-858X

Output-capacitorless low-dropout regulator

using a cascoded flipped voltage follower
G. Blakiewicz
Department of Microelectronic Systems, Gdansk University of Technology, Narutowicza 11/12, PL 80-233 Gdansk, Poland
E-mail: blak@eti.pg.gda.pl

Abstract: An improved ipped voltage follower (FVF) and its application to a low-dropout (LDO) voltage regulator are
presented. The proposed FVF improves most weaknesses of the classical one, namely its poor time response to the output
current change from low to high value and poor stability for large capacitive load. The most important parameters of the
modied FVF are analysed and described by analytical expressions. The parameters of the classical FVF and the improved
one are compared and discussed. LDO regulator using the improved FVF is designed and implemented in AMS CMOS
0.35 mm technology. The measurement results of a test circuit show its relatively high current efciency of 74 and 99.93%
for output current 100 mA and 50 mA, respectively. The output voltage overshoot and undershoot are below 46 and 75 mV
for output current change from 0.1 to 50 mA with the rise and fall times equal to 0.3 ms, and load capacitance 0 100 pF.

Introduction

In modern systems on a chip (SoC) there is a strong need for

on-chip integration of voltage regulators providing necessary
supply voltages and enabling power management of
component subsystems. The high-efciency, fast-response
and low-dropout (LDO) voltage regulators become critical
for successive implementation of effective SoC supplying.
There are two main approaches to integrated LDO voltage
regulators design. The regulators with a relatively big output
capacitor, typically located off-chip as a discrete component,
are designed to have the dominant pole located at the
regulator output [1 9]. Big output capacitance helps to
achieve the dominant pole at low frequencies, well
separated from the remaining non-dominant poles, which
guaranties stable operation. Such a conguration is very
favourable from the point of view of electrical parameters,
because big output capacitance reduces overshoots and
undershoots caused by rapid changes of output current, and
it additionally improves the power supply rejection (PSR) at
high frequencies. On the other hand, the need for
connecting the external capacitor complicates SoC layout
and restricts the number, and possible locations of the
regulators on a chip, because each of them needs a
dedicated terminal for the external capacitor connection.
The other solution of LDO regulators is based on very
small on-chip capacitance connected to its output, mainly
resulting from parasitic capacitance of an on-chip supply
network [10 17]. The small output capacitance makes the
design of such on-chip regulators extremely difcult,
because in this case the dominant pole has to be realised
inside a negative regulation loop. Such a location of the
dominant pole degrades most of electrical parameters.
The dominant pole located inside the regulation loop
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signicantly reduces its speed. Because there is small

capacitance at the regulator output, its output impedance
becomes large at higher frequencies resulting in two
additional serious disadvantages, poor PSR at high
frequencies and lack of charge reservoir at the output. The
small output capacitance is typically insufcient to provide
electrical charge, which could compensate for output
voltage spikes caused by rapid change of load current.
Several solutions were proposed to overcome the outlined
difculties. The single-transistor-control conguration [10,
11] using ipped voltage follower (FVF) [18], shown in
Fig. 1, is utilised to form a regulator able to operate stable
with no output capacitance. The circuit presented in [11],
working also with any value of output capacitance, reveals
good characteristics especially when the output capacitor
has capacitance of 1 10 mF and equivalent series resistance
(ESR) greater than zero. The improved version of that
conguration with reduced response time is achieved by
applying voltage-spike detection mechanisms [12 14]. The
regulators detect output voltage spikes and dynamically
increase biasing currents, which increase their speed. All
the mentioned regulators are based on similar idea of using
the output stage with very low output resistance achieved as
a result of a local negative feedback. As discussed in [11],
such a stage has two main poles in the frequency response
of the negative regulation loop
p1 =

gds2 + gbias
Cgs1 + (1 + gm1 /(gds1 + gm2 ))Cgd1

(1a)

gm2 + gds1
Cout

(1b)

p2 =

where gm1 and gm2 are the transconductances, and gds1 , gds2
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Fig. 1 Classical FVF

are the drain source conductance of M1 and M2, whereas

gbias is the internal conductance of the current source. Cgs1
and Cgd1 are the gate source and gate drain capacitances
of M1. Cout is the total output capacitance.
The equations (1a) and (1b) are valid under the assumption
that the load capacitance Cout has zero ESR and is relatively
small, which directly corresponds to the case where the
regulator is loaded with parasitic capacitance of a small onchip supply network. The second pole (1b) is typically
located at frequencies greater than the unity gain frequency
[11], which means that the regulator has almost a singlepole frequency characteristic in this frequency range, and
consequently the phase margin close to 908.
The output stage composed of FVF is well suited to fully
on-chip integrated regulators, because its low output
resistance limits the lowest magnitude of the non-dominant
pole when Cout increases. This assures large separation of
the dominant and non-dominant poles and guarantees stable
operation. The regulators using the classical FVF presented
in [10 14] have also limitations. The stable operation of a
typical on-chip FVF is only possible for output capacitance
Cout limited to 20 30 pF when RESR 0 or for larger
capacitances but with RESR . 0 [11]. For greater loads,
caused, for example, by large on-chip supply networks,
FVF has to be stabilised by connecting additional
capacitance to node X, shown in Fig. 1 [18]. Unfortunately,
the additional capacitance degrades speed of the regulator
and increases output voltage spikes. Another problem
results from limited current which can be applied to
discharge the parasitic capacitance CX associated with node X.
The maximum discharge current is restricted by the

current source to Ibias , and in most cases cannot effectively

compensate a rapid change from low to high value of the
output current. A better situation is with FVF reaction to
output current change from high to low value. In this case, the
charging current is generated by transistor M2, which is able
to source much greater current. Typically for this circuit, the
output voltage undershoot is greater than overshoot, and may
reach over 150 mV in magnitude for rapid current change
from 0 to 50 mA [11].
In this paper LDO regulator with an improved FVF is
presented. The proposed circuit reveals better frequency and
time responses with only a little increase of its complexity.
The rest of the paper is divided to Section 2 that discusses
the improved FVF conguration. Section 3 presents design
trade-offs and discusses the circuit optimisation. The
measurement results of a prototype regulator using the
improved FVF are provided in Section 4. The nal section
includes conclusions.

Improved FVF

The schematic of the proposed improved FVF is depicted in

Fig. 2. The capacitors CX and Cout represent the parasitic
capacitances associated with X and the output nodes,
respectively. The additional transistor M3 plays 2-fold role.
Firstly, it increases the equivalent resistance seen at node X
at lower frequencies by cascoding the current source.
Secondly, M3 increases voltage gain of the common gate
stage, formed of M2, at higher frequencies. At higher
frequencies both transistors M2 and M3 work together with
the equivalent transconductance increased to gmS gm2 + gm3 ,
where gm2 , gm3 are their transconductances. As a result, the
presented FVF has the dominant pole, associated with node X,
shifted to lower frequencies without increasing the node
parasitic capacitance. Because CX is almost unchanged, and the
dominant pole is more separated from the non-dominant one,
the phase margin of the regulation loop is improved without
any penalty in speed of its time response. However, the most
important advantage of this conguration is the increased
current discharging CX . In this circuit, transistor M2 generates
charging Ichr , whereas M3 discharging Idis current. Both
transistors form a class-AB amplier with the quiescent biasing
current dened by the current source Ibias . During transients of
the output current, the drain current of one of M2 or M3
increases without limitation to Ibias , as was the case for the
classical FVF shown in Fig. 1. Such a operation enables fast
reaction to output current changes, under relatively small

Fig. 2 Improved FVF

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biasing current Ibias. This permits a low-power operation and
high-efciency of supplying.
The magnitude of discharging Idis and charging Ichar
currents owing through the capacitance CX can be
approximated by

DVout
DVout

+ Ibias Cf
for DVGS3 DVout
(2a)
Idis  Cf
t1
t1
+
+
+
Ichr  gm2 DVout
Ibias gm2 DVout
for VGS2 DVout
(2b)

where t1 is the fall time of the output voltage, as shown in

Fig. 2. The biasing current Ibias is omitted in (2a) and (2b)
because of its relatively small value. The above equations
were derived assuming that each transistor is working in the
saturation region while sourcing or sinking its drain current.
+(2)
For properly designed circuit, the output spikes DVout
are
strongly limited in magnitude, which entitles using the
small-signal approach ( gm2 in 2b). The approximation (2a)
is valid when change of the gate source voltage DVGS3 is

smaller than the magnitude of the output spike DVout

,
resulting in the following condition:
DVGS3

Cf
1
1
DVout

idis
Cf
. DVout
gm3 .
(3)
t1
t1
gm3
gm3

and undershoot DVout

The output voltage overshoot DVout
will be of similar magnitude if Idis Ichr , which leads to

gm2

Ichr
Idis
1
+ =
+
+
DVout
DVout
DVout

DVout
DVout
Cf DVout

t1

Cf
t1

(4)

The minimal biasing current Ibias is limited by the minimal

required transconductance of transistors M2 and M3,
expressed by (3) and (4). For low-power application the
biasing current Ibias can be reduced, to some extend, by
making the transistors wide. Unfortunately, wide transistors
increase the parasitic capacitance CX and consequently
reduce the speed of FVF. The selection of Ibias , width of
M2 and M3 requires nding a satisfactory trade-off between
the speed and power consumption.
A simple approximation of the output spikes can be
achieved using the circuit shown in Fig. 3, which represents
a simplied model of the output node of FVF from Fig. 2
during an initial time interval denoted by t1 . As it will be
pointed out later, this small-signal model is only valid for
relatively small Cout for which the gate source voltage of
M1 does not change much, and gm1 can be regarded as a
constant. During the interval t1 , the change of the gate
source voltage DVgs1 follows the change of output voltage
DVout . In this interval the gain of the stage composed of M2
and M3 is hardly limited to value close to unity, because
the parasitic capacitance CX is reloaded by the limited

Fig. 3 Simplied model of FVF output node during an initial

period t1 of output transient
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discharging current dened by (2a), which results in

DVgs1 = DVX =

Cf
t1
t
DVout
Idis 1 Cf
=
V
CX
CX
t1
CX out

(5)

By making Cf . CX , one can achieve the voltage gain greater

than unity during the considered transient, and consequently
more effective reduction of FVF output voltage undershoot.
Similar conclusion can also be formulated for the process
of charging capacitance CX . Using the model from Fig. 3
one can easily see, that the change of output current DIout
is compensated by the controlled current source and
capacitance Cout
DIout =

Cf
DV

gm1 DVout
+ Cout out
CX
t1

(6)

The output voltage changes rapidly until the moment when

the drain current of M1 becomes equal to the current
owing through capacitance Cout . Once this happens, the
rate of DVout change starts to decrease rapidly, because the
current generated by M1 due to its high gain increases
much faster than current owing through Cout . This
moment can be approximately regarded as the moment of
the output voltage undershoot occurrence. The time interval
t1 after which both currents become equal can be estimated
from [compare (6)]
Cf
DV

gm1 DVout
= Cout out
CX
t1

(7)

The simplied approximation of the output voltage

undershoot DVout
is derived by substitution of t1 , achieved
from (7), into
Cf
t1
DV

DIout =
gm1 DVout
+ Cout out
Dt
CX
t1

(8)

where the left side of the equation represents the fraction of

the output current change DIout after the period t1 . Finally,
the undershoot is

DVout

 2
1 CX Cout DIout

2
Dt
2 Cf gm1

(9)

where gm1 is approximately equal to M1 transconductance

calculated for Id1 Ibias + (Iout)min . The approximation (9)

is only valid for Cout Cf + CX , where DVout

is relatively
small and gm1 can be regarded as a constant. The output
voltage overshoot can also be estimated from (9), because
the sequence of events is similar, but they happen in the
reverse order. During the initial period (denoted by t2 in
Fig. 2) of output current change from high to low value, the
drain current of M1 is greater than the current through Cout
owing to its high gain. When both currents become equal,
+
the rate of DVout
change starts to decrease rapidly, and the
overshoot occurs. The approximation (9) can be directly
+
used for DVout
calculation under the assumption that
Idis Ichr , which requires the condition (4) to be fullled.
The expression (9) shows that increasing the output
+()
capacitance Cout does not reduce the output spikes DVout
,
whereas the most important factor for its reduction is M1
transconductance. For typical circuit parameters, the
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Table 1

Comparison of important parameters of the classical and improved FVFs

Parameter

Classical FVF
from Fig. 1

the dominant pole p1

the maximal charging
current Ichr
the maximal discharging
current Idis
PSR at low frequenciesc
PSR at medium frequenciesd

Improved FVF
from Fig. 2

gds2 + gbias
Cgs1 + (1 + gm1 /(gds1 + gm2 ))Cgd1
+
gm2 DVout
Ibias

1
gm1
gm2 gm1
1+
gds1
(gds2 + gbias )gds1

1
gm1
gm2 gm1
1+
gds1
(gds2 + gbias )gds1

gds2 + gbias gds3 /gm3

Cgs1 + (1 + gm1 /(gds1 + gm2 ))Cgd1
+ a
gm2 DVout
Cf2 gm1
a
DVout
Cout CX

1
gm1
gm1 gm2
1+
gds1
(gds2 + (gbias gds3 /gm3 ))gds1


gm1
g (g + gm3 ) 1
1 + m1 m2
(gds2 + gds3 )gds1
gds1

Approximated
improvement factor
1+

gbias
2
gds2

Cf2 gm1 DVout

= 5.5b
Cout CX Ibias

1+

gbias
2
gds2

1+

gm3
2
gm2

achieved assuming small signal approximation, valid for DV+(2)

out VT
calculated from (2a) and (7) assuming Cx 8 pF, Cf 10 pF, Cout 20 pF, gm1 3.5 mS, Ibias 20 mA, DV2
out 52 mV
c
achieved from (10) for AFB gm2/( gds2 + gds3gbias/gm3)
d
achieved from (10) for AFB ( gm2 + gm3/( gds2 + gds3)
a

magnitude of the spikes calculated from (9), is

+()
DVout
52 mV assuming: DIout 100 mA, Cx 8 pF,
Cf 10 pF, Cout 20 pF, gm1 3.5 mS, Dt 1 ms.
The PSR of FVF, shown in Fig. 2, at low frequencies
strongly depends on the voltage gain AFB of the feedback
amplier composed of M2. At low frequencies, M3 forms a
cascode stage and does not provide voltage gain. The noise
at FVF output is reduced by [11]
DVout
(gm1 /gds1 )
=
DVin
1 + (AFB gm1 /gds1 )

(10)

which means that the improved FVF provides a better noise

attenuation than the classical one (Fig. 1), because of its
greater gain AFB achieved owing to the increased resistance
of node X. At medium-frequency range, the improved FVF
also reveals better performance, because at this range both
transistors M2 and M3 form a push pull amplier with
increased gain.

Design trade-offs and circuit optimisation

The most important parameters of the classical and improved

FVFs are compared in Table 1. The last column presents
approximated expressions for an improvement factor
showing how much improvement can be gained for circuit
in Fig. 2. All the presented parameters are derived based on
the small-signal approach, which is only valid for small
+()
output spikes DVout
and small Cout . For larger values, the
equations may not be precise enough.
As (9) shows, the minimisation of the output spikes
requires maximisation of M1 transconductance gm1 and
minimisation of CX . The best results for the spikes
optimisation can be achieved by adjusting Ibias for minimal
possible width (W1) and length (L1) of M1, designed to
satisfy the assumed maximal output current (Iout)max . The
increasing of the transistor width results
in enlarging
CX ,


because: CX / Cgs1 / W1 , and gm1 / W1 /L1 , which in
turn diminishes the primary goal. The output voltage
undershoot can also be improved by enlarging Cf , but this
requires that (3) and (4) are satised, leading to increasing
of Ibias or increasing of M2 and M3 aspect ratios W2/L2 and
W3/L3 . From the power efciency point of view, only the
IET Circuits Devices Syst., 2011, Vol. 5, Iss. 5, pp. 418 423
doi: 10.1049/iet-cds.2010.0431

aspect rations enlargement is advantageous, which means

that length of both transistors L1 and L2 has to be
minimised. In the other case, the parasitic capacitances of
M2 and M3 increase CX , and as a result reduce speed of the
negative loop.
The maximal output capacitance Cout for stable operation
of the improved FVF is limited by the allowable location of
the non-dominant pole. The pole can be approximated by
p2 =

gm2 + gm3 + ggd1

Cout

(11)

The phase characteristic of the local negative feedback is

determined by two poles [the dominant (Table 1) and the
non-dominant (11)] and an additional pole-zero pair
introduced by Cf in series with the resistance seen form the
source of M3. The simplied approximation of the upper
limit of Cout for a non-zero phase margin can be evaluated
assuming that |p2| GB, where GB is the unity gain
bandwidth of the negative loop, which leads to the condition
Cout gm2 + gm3 + gds1

CX
gm1

(12)

In practical circuit realisations, the approximation (12) gives

a much underestimated limit, because it omits the inuence
of the pole-zero pair, typically located close to GB. The

Fig. 4 Implemented LDO regulator

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Table 2

Parameters of the implemented LDO regulator

M1: 5000 mm/0.35 mm

M4: 80 mm/0.8 mm
M9: 7 mm/0.8 mm
R2 134 kV
Cc 3 pF

M2: 300 mm/

0.35 mm
M5, M6: 20 mm/
1 mm
M10: 1.8 mm/
0.8 mm
R3 120 kV
Cb 3 pF

M3: 100 mm/

0.35 mm
M7, M8: 5 mm/
1 mm
R1 66 kV
Cf 20 pF
Ibias 1 mA, Vref 0.8 V

simulations of the phase characteristic and the measurements

results of a prototype circuit show that the limit (12) can be
practically enlarged 10 20 times.

LDO regulator with the improved FVF

The test LDO regulator, shown in Fig. 4, has been implemented

in AMS 0.35 mm CMOS technology. The circuit was designed
to provide 1.2 V output voltage at 50 mA output current for input
voltage greater than 1.4 V. The circuit consists of the discussed
FVF (M1 M4 and Cf ) optimised for low-power operation.
The local negative feedback (M2, M3 and Cf ) enclosing the
last stage guaranties high attenuation of output voltage spikes
and stable operation for big output capacitances. The very
slow additional error amplier composed of M5M10
stabilises DC component of output voltage, and additionally
improves PSR at very low frequencies (,50 kHz). The main
parameters of the circuit are listed in Table 2.

Fig. 5 Time responses of the implemented regulator for output current changes
a and b Cout 15 pF
c and d Cout 100 pF

Fig. 6 Time responses of the implemented regulator for input voltage changes
a
b
c
d

Cout 15 pF, Iout 1 mA

Cout 100 pF, Iout 1 mA
Cout 15 pF, Iout 50 mA
Cout 100 pF, Iout 50 mA

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Table 3

Performance comparison of selected output-capacitorless LDO regulators

Parameter

[11]

[12]

[14]

This work

line regulation
load regulation
PSR at low freq. and (Iout)max

CMOS 0.35 mm
50 mA
1.0 V
95 mA
any
0 pF
0.045 mm2
130 mV/160 mV for
DIout 0 50 mA
and the rise/fall
times
300 ns/300 ns
18 mV/V
0.28 V/A
N/A

CMOS 0.35 mm
100 mA
0.71.2 V
43 mA
any
6 pF
0.358 mm2
70 mV/70 mV for
DIout 1 100 mA
and the rise/fall
times
1 ms/1 ms
N/A
N/A
N/A

PSR at high freq. and (Iout)max

N/A

CMOS 0.09 mm
100 mA
0.51 V
8 mA
.10 pF
7 pF
0.019 mm2
114 mV/73 mV for
DIout 3 100 mA
and the rise/fall
times
100 ns/100 ns
3.78 mV/V
0.1 V/A
50 dB for freq.
,200 Hz
0 for freq.
.1 MHz

CMOS 0.35 mm
50 mA
1.2 V
34.6 mA
0 200 pF
26 pF
0.08 mm2
46 mV/75 mV for
DIout 0.150 mA
and the rise/fall
times
300 ns/300 ns
8.8 mV/V
0.003 V/A
40 dB for freq.
,50 kHz
6 dB for freq.
.19 MHz

technology
(Iout)max
Vout
Iin for Iout 0
Cout
on-chip capacitance
cip area
+

output voltage spikes DVout

/DVout
for output current change

The regulator time responses for the output current change

DIout/Dt 50 mA/0.3 ms are presented in Fig. 5 for
Cout 15 pF and 100 pF. The output voltage overshoot and

+
undershoot are DVout
44 mV and DVout
= 73 mV for
+

Cout 15 pF, whereas DVout = 46 mV and DVout

= 75 mV
for Cout 100 pF. The output voltage responses for the
input voltage change from 1.4 to 1.6 V with the rise/fall
times DVin/Dt 200 mV/0.3 ms are presented in Fig. 6 for
Cout 15 pF, Cout 100 pF and two output current values
Iout 1 mA and Iout 50 mA. The biggest output voltage
+

spikes DVout
= 22 mV and DVout
= 27 mV were observed
for Iout 50 mA. The spikes magnitude did not practically
depend on the load capacitance as long as Cout , 200 pF.
Table 3 compares important parameters of selected outputcapacitorless LDO regulators reported in the literature with
the regulator presented in this paper.

Conclusions

A useful modication of FVF having good time and frequency

responses is presented in this paper. The proposed FVF
improves most weaknesses of the classical one, namely its
poor time response to the output current change from low to
high value and poor stability for large capacitive load. The
complexity of the improved FVF is only little increased,
because it requires additional single transistor and capacitor.
The designed and implemented LDO regulator using the
improved FVF reveals very good characteristics.

Acknowledgments

This work was supported by the Polish Ministry of Science

and Higher Education, in part from grant N N515 423034,
and O R00 0046 09.

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