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ECAD &VLSI LAB REPORT
VERILOG Programs
Department of ECE(VCET)
Page 1
1. BASIC LOGIC GATES

Aim: To write a verilog program for all gates and verifying its functionality by using test bench.
Tools: Xilinx 9.1i
1)simulation: ISE simulator

2)synthesis: XST tool
Truth table:
A
B
0
0
0
1
1
0
1
1
Y_NOT
1
1
0
0
Y_OR
0
1
1
1
Y_AND
0
0
0
1
Y_NOR
1
0
0
0
Y_NAND
1
1
1
0
Y_XOR
0
1
1
0
Y_XNOR
1
0
0
1
Program for all gates:

module all_gate(a,b, y_not, y_or, y_and, y_nor, y_nand, y_xor,y_xnor);
input a;
input b;
output Y_not, y_or, y_and, y_nor, y_nand, y_xor,y_xnor;
assign y_or = a | b;
assign y_and = a & b;
assign Y_not = ~ a;
assign y_nand = ~( a & b ) ;
assign y_nor = ~ (a | b);
assign y_xor = a ^ b ;
assign y_xnor = ~ (a ^ b);
endmodule
Page 2

RTL schematic view:
Input test bench waveform:
Output simulation waveform:
Conclusion/Result: Program for all gates is designed and it functionality is verified.
Page 3
2. 8:1 MULTIPLEXER
Aim : To design a 8:1 multiplexer using behavioral model and verifying its functionality using
test bench
Tools : Xilinx 9.1i
Truth table :
SEL 1
SEL 2
SEL 0
MUX_OUT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
A
B
C
D
E
F
G
H
Program for 8x1 multiplexer( behavioral code) :

module mux (a, b, c, d, e, f, g, h, sel, y);
input a;
input b;
input c;
input d;
input e;
input f;
input g;
input h;
input [2:0] sel;
Page 4

output y;
reg y;
always@(sel,a,b,c,d,e,f,g,h)
begin
case(sel)
3'd0:y=a;
3'd1:y=b;
3'd2:y=c;
3'd3:y=d;
3'd4:y=e;
3'd5:y=f;
3'd6:y=g;
3'd7:y=h;
Endcase
end
endmodule
Rtl schematic:
Page 5

Input test bench waveform :
Output simulation waveform :
Conclusion/result :
8:1 multiplexer is designed by using behavioral model and verified its functionality using test
bench
Page 6
3. 1x8 DE MULTIPLEXER
Aim : To design a 1:8 demultiplexer and verify its functionality and check its simulation report
Tools : 1) simulation : 9.2i ISE simulator
2) synthesis :9.2i XST
Truth table :
S2
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
Y[0]
din
0
0
0
0
0
0
0
Y[1]
0
din
0
0
0
0
0
0
Y[2]
0
0
Din
0
0
0
0
0
Y[3]
0
0
0
din
0
0
0
0
Y[4]
0
0
0
0
din
0
0
0
Y[5]
0
0
0
0
0
din
0
0
Y[6]
0
0
0
0
0
0
din
0
Y[7]
0
0
0
0
0
0
0
Din
Program for 1:8 demultiplexer:

module demux1_8v(din, sel, y);
input din;
input [0:2] sel;
output [0:7] y;
wire din;
wire [0:2] sel;
reg [0:7]y;
always@(sel,din)
begin
case (sel)
3'b000:y=8'b10000000;
3'b001:y=8'b01000000;
3'b010:y=8'b00100000;
3'b011:y=8'b00010000;
3'b100:y=8'b00001000;
3'b101:y=8'b00000100;
3'b110:y=8'b00000010;
3'b111:y=8'b00000001;
Page 7

default:y=8'b11111111;
endcase
end
endmodule
Rtl schematic :
Input testbench wavwform:
Page 8
Conclusion/result:1:8 demultiplexer is designed by using behavioral model and verified its
functionality using test bench.

Page 9
4. 2 to 4 DECODER
Aim:To write a program for 2 to 4 decoder by using behavioral model and verifying its
functionality using testbench
Tools: xilinx 9.1i
1. Simulation: IES simulator
2. Synthesis: XST tool
Truth table:
Enable
1
0
0
0
0
Din1
X
0
0
1
1
Din0
X
0
1
0
1
Dout3
0
0
0
1
0
Dout2
0
0
0
1
0
Dout1
0
0
1
0
0
Dout0
0
1
0
0
0
Verilog code:
Module decoder 2_4(enable,din,dout);
Input enable;
Input[1:0]din;
Output[3:0]dout;
Reg[3:0]dout;
always@(enable,din)
begin
if(enable==1b1)
begin
dout=4b0000;
end
else
Page 10

begin
case(din)
2b00:dout=4b0001;
2b01:dout=4b0010;
2b10:dout=4b0100;
2b11:dout=4b1000;
Endcase
End
Endmodule
Rtl schematic view:
Input testbench waveform:
Page 11

Conclusion/Result:
2 to 4 decoder is designed by using behavioral model and its functionality is verified by using
testbench.
Page 12
5. 8-3 ENCODER WITH PARITY AND WITHOUT PARITY

Aim: To write a program for 8-3 encoder with priority using behavioral model and verify its
functionality using testbench.
Tools : Xilinx 9.1i

Truth table:
ENABLE
1
0
0
0
0
0
0
0
0
DIN7
X
X
X
X
X
X
X
X
1
DIN6
X
X
X
X
X
X
X
1
0
DIN5
X
X
X
X
X
X
1
0
0
DIN4
X
X
X
X
X
1
0
0
0
DIN3
X
X
X
X
1
0
0
0
0
DIN2
X
X
X
1
0
0
0
0
0
DIN1
X
X
1
0
0
0
0
0
0
DIN0
X
1
0
0
0
0
0
0
0
DOUT2 DOUT1 DOUT0

0
0
0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Program for 8-3 encoder with priority:

module encoder2(din, dout, enable);
input [7:0] din;
output [2:0] dout;
input enable;
reg [2:0] dout;
always@(din,enable)
begin
if(enable==1'b1)
dout=3'b000;
else
begin
Page 13

casex(din)
8'bxxxxxxx1:dout=3'b000;
8'bxxxxxx10:dout=3'b001;
8'bxxxxx100:dout=3'b010;
8'bxxxx1000:dout=3'b011;
8'bxxx10000:dout=3'b100;
8'bxx100000:dout=3'b101;
8'bx1000000:dout=3'b110;
8'b10000000:dout=3'b111;
default:dout=3'b000;
endcase
end
end
endmodule
Rtl schematic view:
Page 14

Conclusion/Result:
8-3 encoder with priority is desgined using behavioral model and its functionality is verified using
testbench.
Page 15
8-3 ENCODER WITHOUT PARITY:

Aim : To write a program for 8to3 encoder without priority using behavioral model and verify its
functionality using testbench
Tools : Xilinx 9.1i

Truth table:
ENABLE DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 DOUT2 DOUT1 DOUT0
1
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
0
1
0
0
0
0
0
0
1
1
0
0
1
0
0
0
0
0
0
0
1
1
1
Program for 8 -3 encoder without priority:
module encoder(din, enable, dout);
input [7:0] din;
input enable;
output [2:0] dout;
reg[2:0] dout;
always@(din,enable)
begin
if(enable==1'b1)
dout=3'b000;
else
begin
Page 16

case(din)
8'b00000001:dout=3'b000;
8'b00000010:dout=3'b001;
8'b00000100:dout=3'b010;
8'b00001000:dout=3'b011;
8'b00010000:dout=3'b100;
8'b00100000:dout=3'b101;
8'b01000000:dout=3'b110;
8'b10000000:dout=3'b111;
default:dout=3'b000;
endcase
end
end
endmodule
Rtl schematic view:
Page 17

Conclusion/Result:
8-3 encoder is designed by using behavioral model and verified its functionality using test bench
Page 18
6. 4 BIT COMPARATOR
Aim: To write a program for 4 bit comparator using behavioral code and verifying its functionality using
test bench.
Tools: Xilinx 9.1i

Truth table:
ENABLE
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
B
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
aeb
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
alb
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
agb
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
Program for 4 bit comparator:

module prgm(a, b, en, aeb, agb, alb);
input [3:0] a;
input [3:0] b;
input en;
output aeb;
output agb;
Page 19

output alb;
reg aeb,agb,alb;
always@(a,b,en)
begin
if(en==1)
if(a==b)
begin
aeb=1;
agb=0;
alb=0;
end
else if(a>b)
begin
aeb=0;
agb=1;
alb=0;
end
else
begin
aeb=0;
agb=0;
alb=1;
end
Page 20

else
begin
aeb=0;
agb=0;
alb=0;
end
end
endmodule
Rtl schematic view:
Page 21

Conclusion/Result:
4 bit comparator is designed using behavioral model and its functionality is verified using testbench
Page 22
7. Code converters
Aim:
To design a code converter by using behavioral model and verifying its functionality using test bench.
Tools: xilinx9.1i
1.simulation: ISE simulator
2.Synthesis : XST tool
For conversion of binary to gray code:
Truth table:
Binary
Inputs
B3 B2 B1 B0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Program for binary to gray converter:
Gray
Outputs
G3 G2 G1 G0
0000
0001
0011
0010
0110
0111
0101
0100
1100
1101
1111
1110
1010
1011
1001
1000
Verilog code:
module converter(b, g);
input [3:0] b;
output [3:0] g;
reg [3:0]g;
always@(b)
Page 23

begin
g[3]=b[3];
g[2]=b[3]^b[2];
g[1]=b[2]^b[1];
g[0]=b[1]^b[0];
end
endmodule
Rtl schematic view:
Page 24

For conversion of gray to binary:

Gray
inputs
G3 G2 G1 G0
0000
0001
0011
0010
0110
0111
0101
0100
1100
1101
1111
1110
1010
1011
1001
1000
Binary
outputs
B3 B2 B1 B0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Program for gray to binary converter:

Verilog code:
module code(g, b);
Page 25

input [3:0] g;
output [3:0] b;
reg [3:0]b;
always@(g)
begin
b[3]=g[3];
b[2]=g[3]^g[2];
b[1]=g[3]^g[2]^g[1];
b[0]=g[3]^g[2]^g[1]^g[0];
end
endmodule
Rtl schematic view:
Page 26

Conclusion/result: a code converter by using behavioral model and verifying its functionality using test
bench is verified.
Page 27
8. FULL ADDER USING THREE MODELING STYLES

Aim: To write a HDL program for full adder using three modeling styles and verifying its functionality by
using test bench.
Tools: Xilinx 9.1i

Verilog program for full adder:
Data flow discription:
module fulladder_3(a, b, cin, sum, cout);
input a;
input b;
input cin;
output sum;
output cout;
assign sum = a ^ b ^ cin ;
assign cout = (a & b) | (b & cin) | (cin & a);
endmodule
Behavioral model:
module fulladd (a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
reg sum,cout;
always@(a,b,cin)
begin
if(a==1'b0 & b==1'b0 & cin==1'b0)
begin
Page 28

sum=1'b0;
cout=1'b0;
end
else if(a==1'b0 & b==1'b0 & cin==1'b1)
begin
sum=1'b1;
cout=1'b0;
end
else if(a==1'b0 & b==1'b1 & cin==1'b0)
begin
sum=1'b1;
cout=1'b0;
end
else if(a==1'b0 & b==1'b1 & cin==1'b1)
begin
sum=1'b0;
cout=1'b1;
end
else if(a==1'b1 & b==1'b0 & cin==1'b0)
begin
sum=1'b1;
cout=1'b0;
end
else if(a==1'b1 & b==1'b0 & cin==1'b1)
begin
Page 29

sum=1'b0;
cout=1'b1;
end
else if(a==1'b1 & b==1'b1 & cin==1'b0)
begin
sum=1'b0;
cout=1'b1;
end
else if(a==1'b1 & b==1'b1 & cin==1'b1)
begin
sum=1'b1;
cout=1'b1;
end
end
endmodule
Structural model:
module FA(a,b,cin,sum,cout);
input a;
input b;
input cin;
output sum;
output cout;
HA H1 (a,b,s0,c0);
Page 30

HA H2 (cin,s0,sum,c1);
or_gate O1 (c0, c1, cout);
endmodule
module HA(a,b,s,c);
input a,b;
output s,c;
xor (s,a,b);
and (c,a,b);
endmodule
module or_gate(a,b,y);
input a;
inpu t b;
output y;
assign y = a | b;
endmodule
Rtl schematic view:
Page 31

Conclusion/result:
A HDL program for full adder is designed by using three modeling styles and its functionality is verified
by test bench.
Page 32
VHDL Programs
Page 33
1. BASIC LOGIC GATES

Aim: To write a VHDL program for all gates by using behavioral model and verifying its functionality by
test bench
Tools: Xilinx 9.1i

Truth table:
A
B
Y_NOT
0
0
1
0
1
1
1
0
0
1
1
0
Vhdl program for all gates:
Y_OR
0
1
1
1
Y_AND
0
0
0
1
Y_NOR
1
0
0
0
Y_NAND
1
1
1
0
Y_XOR
0
1
1
0
Y_XNOR
1
0
0
1
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allgates is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y_or : out STD_LOGIC;
y_nor : out STD_LOGIC;
y_and : out STD_LOGIC;
y_not : out STD_LOGIC;
y_nand : out STD_LOGIC;
y_xor : out STD_LOGIC;
y_xnor : out STD_LOGIC);
Page 34

end allgates;
architecture Behavioral of allgates is
begin
y_not <= not a;
y_or <= a or b;
y_and <= a and b;
y_nor <= a nor b;
y_nand <= a nand b;
y_xor <= a xor b;
y_xnor <= a xnor b;
end Behavioral;
Page 35

Rtl schematic view:
Page 36

Output simulation wave form:
CONCLUSION/RESULT:
A VHDL program for all gates by using behavioral model is designed and its functionality is verified by
test bench
Page 37
2.8x1 MULTIPLEXER
Aim: To write a VHDL program for 8:1 multiplexer by using behavioral model and verifying its
functionality by using test bench.
Tools: XILINX 9.1i

Truth table:
SEL3
0
0
0
0
1
1
1
1
Vhdl program for 8:1 mux:
SEL2
0
0
1
1
0
0
1
1
SEL1
0
1
0
1
0
1
0
1
Y_OUT
A
B
C
D
E
F
G
H
library IEEE;
entity mux8_1 is
Port ( y_out : out STD_LOGIC;
A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
E : in STD_LOGIC;
F : in STD_LOGIC;
Page 38

G : in STD_LOGIC;
H : in STD_LOGIC;
sel : in STD_LOGIC_VECTOR (2 downto 0));
end mux8_1;
architecture Behavioral of mux8_1 is
begin
process (SEL,A,B,C,D,E,F,G,H)
begin
case SEL is
when "000" => y_OUT <= A;
when "001" => y_OUT <= B;
when "010" => y_OUT <= C;
when "011" => y_OUT <= D;
when "100" => y_OUT <= E;
when "101" => y_OUT <= F;
when "110" => y_OUT <= G;
when "111" => y_OUT <= H;
when others => null;
end case;
end process;
end Behavioral;
Rtl schematic view:
Page 39
Page 40
Conclusion/result:
A VHDL program for 8:1 multiplexer is designed by using behavioral model and its functionality is
verified by test bench.
Page 41
3. 2 to 4 DECODER
Aim: To design a 2-4 decoder using behavioral model and verify its functionality using test
bench
Tools: Xilinx 9.1i
Truth table:
Enable
1
0
0
0
0
Din1
X
0
0
1
1
Din0
X
0
1
0
1
Dout3
0
0
0
1
0
Dout2
0
0
0
1
0
Dout1
0
0
1
0
0
Dout0
0
1
0
0
0
Vhdl program for 2-4 decoder:

library IEEE;
entity decoder is
Port ( enable : in STD_LOGIC;
din : in STD_LOGIC_VECTOR (1 downto 0);
dout : out STD_LOGIC_VECTOR (3 downto 0));
end decoder;
architecture Behavioral of decoder is
begin
process (enable,din)
begin
Page 42

if(enable = '1')then
dout <= "0000";
else
case din is
when "00" => dout <= "0001" ;
when "01" => dout <= "0010" ;
when "10" => dout <= "0100" ;
when "11" => dout <= "1000" ;
when others => dout <= "0000";
end case;
end if;
end process;
end Behavioral;
Rtl schematic view:
Page 43

Conclusion/Result:
A VHDL program for 2-4 decoder is designed by using behavioral model and its functionality is verified
by testbench.
Page 44
4. 1x8 Demultiplexer
Aim: To design a 2-4 decoder using behavioral model and verify its functionality using test
bench
Tools: Xilinx 9.1i
Truth Table:-
S2
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
Y[0]
din
0
0
0
0
0
0
0
Y[1]
0
din
0
0
0
0
0
0
Y[2]
0
0
Din
0
0
0
0
0
Y[3]
0
0
0
din
0
0
0
0
Y[4]
0
0
0
0
din
0
0
0
Y[5]
0
0
0
0
0
din
0
0
Y[6]
0
0
0
0
0
0
din
0
Y[7]
0
0
0
0
0
0
0
Din
Vhdl program for 1x8 Demultiplexer:

library IEEE;
-------------------------------------------------entity demux is
port(i:in std_logic;
sel:in std_logic_vector(2 downto 0);
o:out std_logic_vector(0 to 7));
end demux;
Page 45

-------------------------------------------------architecture Behavioral of demux is
begin
process(sel)
begin
o<="00000000";
case sel is
when "000"=>o(0)<=i;
when "001"=>o(1)<=i;
when "010"=>o(2)<=i;
when "011"=>o(3)<=i;
when "100"=>o(4)<=i;
when "101"=>o(5)<=i;
when "110"=>o(6)<=i;
when "111"=>o(7)<=i;
when others=> o<="ZZZZZZZZ";
end case;
end process;
end Behavioral;
RTL Schematic:
Page 46
Input Test Bench waveform:
Page 47

Output Simulation Waveform:
Conclusion/Result:A VHDL program for 1x8 Demultiplexer is designed by using behavioral model and its functionality is
verified by testbench.
Page 48
5.HALF ADDER
Aim: To write a VHDL program for half adder by bahavioral model and verifying its functionlity by using
testbench
Tools: Xilinx 9.1i

Truth table:
A
0
0
1
1
B
0
1
0
1
S
0
1
1
0
C
0
0
0
1
Vhdl program for half adder:

library IEEE;
entity halfadder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end halfadder;
architecture Behavioral of halfadder is
begin
s <= a XOR b;
c <= a AND b;
Page 49

end Behavioral;
Rtl schematic view:
Conclusion/result:
A VHDL program for hall adder is designed by using behavioral model and its functionality is verified by
using testbench.
Page 50

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ECAD &VLSI LAB REPORT

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1. BASIC LOGIC GATES

1)simulation: ISE simulator

Program for all gates:

ECAD &VLSI LAB REPORT

Input test bench waveform:

Output simulation waveform:

Conclusion/Result: Program for all gates is designed and it functionality is verified.

ECAD &VLSI LAB REPORT

Program for 8x1 multiplexer( behavioral code) :

ECAD &VLSI LAB REPORT

ECAD &VLSI LAB REPORT

Output simulation waveform :

ECAD &VLSI LAB REPORT

Program for 1:8 demultiplexer:

ECAD &VLSI LAB REPORT

Input testbench wavwform:

ECAD &VLSI LAB REPORT

Output simulation waveform:

Conclusion/result:1:8 demultiplexer is designed by using behavioral model and verified its

functionality using test bench.

ECAD &VLSI LAB REPORT

ECAD &VLSI LAB REPORT

Input testbench waveform:

ECAD &VLSI LAB REPORT

ECAD &VLSI LAB REPORT

5. 8-3 ENCODER WITH PARITY AND WITHOUT PARITY

Tools : Xilinx 9.1i

DOUT2 DOUT1 DOUT0

Program for 8-3 encoder with priority:

ECAD &VLSI LAB REPORT

ECAD &VLSI LAB REPORT

Output simulation waveform:

ECAD &VLSI LAB REPORT

8-3 ENCODER WITHOUT PARITY:

Tools : Xilinx 9.1i

ECAD &VLSI LAB REPORT

ECAD &VLSI LAB REPORT

Output simulation waveform:

ECAD &VLSI LAB REPORT

1)simulation: ISE simulator

Program for 4 bit comparator:

ECAD &VLSI LAB REPORT

ECAD &VLSI LAB REPORT

Input test bench waveform:

ECAD &VLSI LAB REPORT

ECAD &VLSI LAB REPORT

ECAD &VLSI LAB REPORT

Input test bench waveform:

ECAD &VLSI LAB REPORT

For conversion of gray to binary:

Program for gray to binary converter:

ECAD &VLSI LAB REPORT

ECAD &VLSI LAB REPORT

Output simulation waveform:

ECAD &VLSI LAB REPORT

8. FULL ADDER USING THREE MODELING STYLES

1)simulation: ISE simulator

ECAD &VLSI LAB REPORT

ECAD &VLSI LAB REPORT

ECAD &VLSI LAB REPORT

ECAD &VLSI LAB REPORT

Output simulation waveform: