Circuit and PD Challenges at the 14nm Technology Node

James Warnock
IBM Systems and Technology Group, T.J. Watson Research Center
P.O. Box 218, Yorktown Heights, NY 10598
(914) 945-2620, jwarnock@us.ibm.com

ABSTRACT

Classical Dennard
Scaling Regime
High-performance voltage

Voltage (V)

As traditional CMOS scaling comes to an end, the industry is

moving towards new 3D finFET multigate structures as device
engineers stand the silicon transistors up on their sides. Digital
circuit designers working in the 14nm technology node will face
significant new challenges from additional design constraints and
new sources of variability associated with this non-planar
transistor structure. In addition, computational lithography and the
need for double patterning at the 14nm node will drive up the
complexity and difficulty of the physical design implementation,
pushing designs towards more uniform and regular structures,
even as wire RC and reliability issues drive increasing demand for
uniquely customized solutions. New design tools and
methodologies will therefore be needed to meet these circuit and
PD challenges at the 14nm node.

Voltage
gap

Scaled voltage

14nm
Regime

0.1
0.01

0.1

Feature pitch (microns)

Figure 1. Typical supply voltage scaling trend.

Categories and Subject Descriptors

In addition the growing voltage gap, or the difference between

the actual chip voltage and the ideally scaled voltage, will mean
that tough reliability issues are likely to be encountered when
implementing high-performance designs.

B.7.1 [Integrated Circuits]: Types and Design Styles advanced

technologies, microprocessors and microcomputers, VLSI. B.7.2
[Integrated Circuits]: Design Aids layout, placement and
routing. B.8.0 [Performance and Reliability]: General

Finally, as if the added complexity associated with multi-gate

finFET devices were not enough, 14nm lithography is expected to
rely heavily on double patterning lithography (DPL), as shown in
figure 2, due to the fact that feature size is generally scaling faster
than the wavelength of light used for imaging.

General Terms
Performance, Design, Reliability

Keywords
14nm; CMOS; scaling; digital circuit design; finFET; trigate;
double patterning; CMOS physical design; PD.

1
Rayleigh Factor (k1)

Conventional lithography

1. SCALING CHALLENGES
As technology scaling pushes towards the 14nm node and then
beyond, it is generally expected that the industry will move away
from the planar FET structures which have served the industry so
well for the past 40 years or so[1]. The classical CMOS scaling
paradigm, described by Dennard[2], and used to predict CMOS
circuit power and performance over a period of several decades
has already run up against some practical limits, and as various
parameters reach their practical scaling limits, circuit designers
must be prepared to cope with various problems associated with
this lack of scaling. Figure 1 shows how supply voltage scaling
has broken down in recent technology generations.

OPC, OAI,
Computational
Lithography

k1 = (resolution)*NA

Double patterning
14nm
Regime
0.1
0.01

0.1

Feature pitch (microns)

Figure 2. Increasing lithographic complexity

The cumulative impacts of finFET device structures, performance
requirements and wire RC, design for reliability and manufacturability, and DPL, will pose considerable challenges for the
implementation of efficient design solutions.

The breakdown of scaling, and the need for ever more exotic
techniques to provide increased transistor performance and
density will lead the industry into the multi-gate regime[3],
creating new challenges for circuit and physical design engineers.

2. FINFET MULTIGATE DEVICES

Multi-gate finFETs, (figure 3), have already appeared at the 22nm
node[4], and are expected to be in use more widely across the
industry by the 14nm node. It is expected that variability due to
Random Dopant Fluctuations (RDF) will be improved[5,6]. Also,

Copyright is held by the author/owner(s).

ISPD13, March 2427, 2013, Stateline, Nevada, USA.
ACM 978-1-4503-1954-6/13/03.
.

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sub-threshold slopes are expected to improve, helping to allow

lower device threshold voltages which in turn will facilitate lower
voltage operation. However variability from gate line edge
roughness will still be present, along with new sources of
variability from fin thickness or height variations.

Metal Pitch

Gate Electrode

Fin Pitch

Metal Pitch

FinFET dual-gate cross section

Gate Pitch
Figure 5. Sample library cell image
FinFET tri-gate cross section

New PD and CAD issues[8] will also arise as DPL is used widely
for patterning at the 14nm node. The design process may rely on
post-layout decomposition, or CAD tools may be color-aware,
aiming to produce color-correct designs by construction. The
former may require a complicated rule set to guarantee error-free
decomposition, whereas the latter will require new infrastructure
and sophisticated algorithms to ensure efficient implementation.
The need for many non-minimum-width wires, and multiple vias
for performance and reliability further increases the difficulty of
creating DPL-compatible designs.

Gate Electrode

Figure 3. Multigate finFETs.

Device Strength (arb Units)

Another fundamental aspect of a finFET technology is the

resulting quantization of device width, since all devices must
contain an integral number of fins, as illustrated in figure 4.

Lower VT
(more perf.)
Tough
Quantization
Issues

0.8
0.6

Layout-based design analysis and extraction tools will also need

enhancements to be able to handle DPL process variability.
Correlated or anti-correlated effects due to mis-alignment
between colors may result in color-dependent systematic shifts in
line-to-line capacitance, for example. Color-aware methodologies
will give designers the ability to predict and control these effects.

finFET
Devices
Planar
Devices

Lower VT
(more perf.)

0.4
0.2

4. CONCLUSIONS
As both device technology and lithography run up against scaling
limits, the 14nm technology generation will see disruptive
changes in both transistor structure and in lithographic patterning
techniques. The impacts of these changes, along with
performance, reliability, and yield considerations will create
many new challenges for circuit engineers working on the next
generation of high-speed designs.

Higher VT
Higher VT
(less leakage)(less leakage)

0
0

Device
Width(ratio
(Units to
of Min
device)
Device
Width
minwidth
width
device)

Figure 4. FinFET quantization.

5. ACKNOWLEDGMENTS

This is likely to be more of a problem for small-width devices.

SRAM array cells and perhaps register file cells will require
careful design/technology co-optimzation to ensure the required
window of functionality[7]. Also, if the technology uses undoped
fins, in order to reduce the impact of random dopant fluctuations,
then designers may lose another degree of flexibility, ie the ability
to select higher or lower VT devices, or they may have to face a
higher variability for high-VT devices with doped fins.

The author would like to thank L. Liebmann for comments and

material on optical lithography, and L. Sigal for a critical reading
of the manuscript.

6. REFERENCES
[1] M. Bohr, IEDM Tech. Dig., p. 1 (2011)
[2] R.H. Dennard et al, IEEE J. Sol.-St. Circ. SC-9, p. 256 (1974).
[3] E. Nowak et al, IEEE Circ. & Devices Mag. 20, p. 20 (2004).
[4] C. Auth et al, 2012 Symp. on VLSI Tech. Digest p. 131.
[5] C. Shin et al, IEEE Trans. On Elect. Dev. 56, p. 1538 (2009).
[6] X. Wang et al, ESSDERC Tech. Dig., p. 113 (2012).
[7] V.S. Basker et al, 2010 Symp. on VLSI Tech. Digest, p. 19.
[8] D.Z. Pan et al, ICICDT Tech. Dig. p. 122 (2010).

3. 14nm PD ISSUES
The introduction of finFETs imposes some new restrictions on the
physical design. In order to minimize the impact of width
quantization and provide maximum current drive per unit area, a
very fine fin pitch is desirable, leading to a sea of fins approach.
In this case library cells need to be designed so that cell heights
are matched to both the fin and metal pitches, as shown in figure
5, in addition to the constraint imposed by gate and metal pitches.
This means that the set of possible cell images is defined with the
basic fin and metal pitches, and cannot be easily changed later.

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