Documente Academic
Documente Profesional
Documente Cultură
2010/5/3
(II)
Ron-Yi Liu
Tel : (O) 03-4245950,
Email: ryliu@cht.com.tw
Outline
2010/5/3
Introduction
of Wireless
Communication System
Analog Filter Design
Switched Capacitor Filter Design
Digital to Analog Circuit Design
S/H Circuit Design
Analog to Digital Circuit Design
Appendix
1-2
1-3
2010/5/3
Data Converter
2010/5/3
Accuracy.
Design Flexibility.
Reliability.
Programmability.
Reproducibility.
Cost and Chip size Down (Portable).
Immunity to Process Variation, and Temperature and Voltage Drift.
1-4
1-5
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Nyquist-Rate
Converters:.
DAC Structure
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1-6
1-7
latch
S/H
Filter
Amplifier
Analog
output
LSB
Bin = b1 2 1 + b2 2 2 + ...... + bN 2 N
Vout = Vref (b1 2 1 + b2 2 2 + ...... + bN 2 N ) = Vref Bin
VLSB =
Vref
2N
, 1 LSB =
1
2N
1-8
Overloaded in Converter:
The magnitude of the quantization
error is larger than VLSB/2.
Quantization Error:
a range of valid input
values that produce the
same digital output word.
1-9
VQ = V1 Vin , V1 = Vin + VQ
T
2
T
2
VQ2 dt
T / 2
T /2
1/ 2
1
=
T
2
VLSB
(
t 2
) dt
T
1/ 2
1/ 2
VLSB
12
1-10
V / 12
Q ( rms )
LSB
( )
V / 12
Q ( rms )
LSB
ENOB =
SNRactual 1.76
6.02
1-11
Gain error:
the change in the slope of the transfer characteristic (due to the
inaccuracy of the scale factor or reference voltage).
1-12
INL
DNL
1-13
DNL/INL Testing
2010/5/3
INL
Ramp the DAC input from 00000000~111111111, so we can get the DAC output
from black level to white level.
LSB = (White Black)/511
INL = MAX{DAC(i) LSB x i } , i=0~511
DNL :
Use the same DAC(i) output step voltage measurements for INL to calculate the
DNL :
DNL = MAX{DAC(i) DAC(i-1) - LSB} , i=0~511
DNL = (
Vcx Vs
V
) 100% = ( cx 1) LSBs
Vs
Vs
1-14
Vi ,OUT = V REF
k =1
2n
k =1
Resistor-String DAC
1-15
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Buffer amplifier:
Low-impedance
output to prevent
loading. (Offset
compensated
SC amplifier)
1-16
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1-17
Resistor-String DAC
2010/5/3
Advantages :
9 Inherently Monotonic.
9 Small area for resolution < 8 bits.
Disadvantages :
9 Large area for resolution < 8 bits.
9 Susceptible to Process Gradients.
9 Susceptible to Contact Resistance.
9 Susceptible to Voltage Coefficient.
DNL depends on local matching of
neighboring Rs.
INL depends on global matching of
Rs.
1-18
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Digital Input
word
VREF
I0
I1
I2
Current Scaling
DAC
IN-1
1-19
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1-20
Advantages :
9 Inherent high speed.
9 Easy to generate Nonlinear data transfer.
9 Easy to segment.
9 Easy to Self-Calibration.
Disadvantages :
9 Large glitches due to timing skews.
9 INL depends on different transistor Matching.
9 Critically dependent on Rout of current source device.
1-21
Reduced-Resistance-Ratio Ladder
1-22
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1-23
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I r=
Vref/2R.
Widely varying current
levels.
N
bi I r
R
= Vref F
i 1
R
i =1 2
Vout = RF
bi
2
i =1
i 1
1-24
1-25
Q=CV
Common-terminal:
Vout
Common-terminal poly-plate:
N 1
VOUT = Dk 2 k N VREF
k =0
C2=C1
C3=2C1
C4=4C1
C5=8C1
45o for corner.
C5
C5
C4
C5
C4
C3
C2
C5
C5
C1
C3
C4
C5
C4
C5
C5
1-26
7
C
7
b
=
2
C
2i bi
i
7i
i =0
i =0 2
Ct =
Vref
1-27
1-28
Vout = Vref
b 2
i =1
Offset cancellation
Op Amp
1-29
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SC offset-canceling amplifier :
insensitive to Op Amp inputoffset voltage, 1/f and finite
Gain.
Be careful in the clock
generator design.
C2: as a deglitching
capacitor for reducing the
clock feed through.
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4i
Thermometer-code
Charge Scaling DAC
1-30
1-31
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Vref/4R
Vref/8R Vref/16R Vref/32R
1-32
Vout = Vref bi 2 i
i =1
C-2C DAC
SALLEN-KEY FILTER
1-33
322.7um
275.1um
DAC
33 Filter
1-34
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z Giving
Pre-sim.
Post-sim.
34
1-35
Output of DAC
Output of Filter
1-36
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1-37
Sample
and
Hold
Anti-aliasing
Analog Active-RC filter
Input (6th~10th order)
Volt
fs : Sampling Frequency
fb : Signal Bandwidth
time
Volt
fs =2fb
Analog
to Digital
Converter
time f
Digital
output
word
=2fb
1-38
Sampler
TSample
1-39
Sampling : CH is charged by
Vin-Vos and Vout=-Vos
Hold mode:
Vout= (Vin-Vos)-(-Vos)=Vin
1-40
f 3dB
1 C1
fCLK
2 C2
1-41
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1-42
1-43
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FFT simulation in
65536 pt. @ 1.35 MHz
1-44
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1-45
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Transient Simulation
The output swing of this Op
Amp circuit could able to swing
to 1Vp-p, but not distortion.
1-46
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1-47
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Vin
Vref
Ramp
Generator
Reset
nT
nT
t
VT
output
counter
VT
Vin
Interval
Counter
Clock
1-48
Precision Comparator
VDAC
VREF
N-bit
N-bitDAC
DAC
Converter
Converter
N-bit
N-bit
Output
Output
Register
Register
.
.
Shift
register
.
Digital
output
Conditional
Gates
clock
1-49
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VREF
0.75VREF
0.5VREF
0.25VREF
z
0 1
2
3
4T
Successive-Approximation
Register (SAR) ADC :
1-50
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S/H CLK
2N-1 to N
Thermometer
Encoder
+Vref
R/2
+
VrN-1
Vin
Input Voltage
VrN-2
....
...
Vr2
Vr1
N digital
output
0011
z
+
z
+
GND R/2
Advantages :
Disadvantages :
9 Need 2N 1 resistors and
comparators in parallel Large
area and power.
CMOS inverter for small clocked
Comparator.
1-51
Quantized Feedford
(Subranging) Architectures :
N-bits
S/H
Coarse
Coarse
ADC
ADC
N-bits
N-bits
+
DAC
AMP
Fine
Fine
ADC
ADC
N-bits
N-bits
Decoder
0.8
Amplifier
Coarse
Comparator
offset
Offset and
DAC and
Gain
Subtractor
accuracy Residue 0.01875
Analog output
1-52
1-53
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iterative ADC:
Operation:
Each stage multiplies its input by 2 and adds or subtracts VREF depending
V o .i
V
upon the sign of the input (like iterative ADC).
= 2 ( o .i 1 ) bi
V
V REF
REF
i-th stage :
1-54
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Cascade of low
resolution stages for
higher conversion speed
Stages operate
concurrently- trades latency
Sampling rate :
50 MHz - 200 MHz
Resolution : 8b - 15b.
Low power consumption
and small chip area.
1-55
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1-56
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Passband=0~10MHz
10bits
Fs=80MHz
Fs=20MS/s
No sample-and-Hold circuit.
Switched-Capacitor Filter
1-57
Capacitor Table
1-58
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Cap. Spread=
Cmax/Cmin=31
1-59
SC-CMFB circuit
Bias circuit
Pre-Simulation
Power Supply(Volts)
-0.9~0.9
-0.9
60
90.83
75
452.5
Phase Margin()
60
62.77
Output Swing(Volts)
1.67
VOS(Volts)
Minimum
1.523
ICMR(Volts)
-1~2
0.6179
CMRR(dB)
Maximum
111.8
PSRR(dB)
Maximum
109.8 / 88.92
Rise Time(ns)
10
Fall Time(ns)
10
0.59
10
212.43
10
1085.25
Minimum
27n
Minimum
6n
Minimum
4.28*10-6
Minimum
2.573*10-7
Minimum
8.043*10-10
Minimum
4.56
Power Dissipation(mW)
Minimum
5.3
1-60
1-61
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1-62
1-63
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60
10
59
ENOB
SNDR
9
58
8
57
56
10
7
12
1-64
1-65
Floor Plan
SCF
ADC
Clk
Output Code
1-66
1-67
1-68
1-69
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