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Received 2 July 2005; received in revised form 15 August 2005; accepted 18 August 2005
Available online 7 September 2005
Abstract
We describe an eld-programmable gate arrays based (FPGA), 96-channel, Time-to-Digital converter (TDC) and
trigger logic board intended for use with the Central Outer Tracker (COT) [T. Affolder et al., Nucl. Instr. and Meth.
A 526 (2004) 249] in the CDF Experiment [The CDF-II detector is described in the CDF Technical Design Report
(TDR), FERMILAB-Pub-96/390-E. The TDC described here is intended as a further upgrade beyond that described in
the TDR] at the Fermilab Tevatron. The COT system is digitized and read out by 315 TDC cards, each serving 96 wires
of the chamber. The TDC is physically congured as a 9U VME card. The functionality is almost entirely programmed
in rmware in two Altera Stratix FPGAs. The special capabilities of this device are the availability of 840 MHz LVDS
inputs, multiple phase-locked clock modules, and abundant memory. The TDC system operates with an input
resolution of 1.2 ns, a minimum input pulse width of 4.8 ns and a minimum separation of 4.8 ns between pulses. Each
input can accept up to 7 hits per collision. The time-to-digital conversion is done by rst sampling each of the 96 inputs
in 1.2-ns bins and lling a circular memory; the memory addresses of logical transitions (edges) in the input data are
then translated into the time of arrival and width of the COT pulses. Memory pipelines with a depth of 5:5 ms allow
deadtime-less operation in the rst-level trigger; the data are multiple-buffered to diminish deadtime in the second-level
trigger. The complete process of edge-detection and lling of buffers for readout takes 12 ms. The TDC VME interface
allows a 64-bit Chain Block Transfer of multiple boards in a crate with transfer-rates up to 47 Mbytes/s. The TDC
module also produces prompt trigger data every Tevatron crossing via a deadtimeless fast logic path that can be easily
reprogrammed. The trigger bits are clocked onto the P3 VME backplane connector with a 22-ns clock for transmission
to the trigger. The full TDC design and multi-card test results are described. There is no measurable cross-talk between
Corresponding author. Tel.: +1 773 7027479; fax: +1 773 8345959.
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channels; linearity is limited by the least-count time bin. The physical simplicity ensures low-maintenance; the
functionality being in rmware allows reprogramming for other applications.
r 2005 Elsevier B.V. All rights reserved.
PACS: 29.40.Gx; 07.50.E; 29.40.+r
Keywords: TDC; FPGA; Pipelined; Multi-hit; Fast trigger processer
1. Introduction
The Collider Detector at Fermilab (CDF), is a
large (5000-ton) detector of particles produced in
protonantiproton collisions at 1.96 TeV at the
Fermilab Tevatron [2]. The detector consists of a
solenoidal magnetic spectrometer surrounded by
systems of segmented calorimeters and muon
chambers. Inside the solenoid, precision tracking
systems measure the trajectories of particles; the
particle momenta are measured from the curvature
in the magnetic eld and the energy deposited in
the calorimeters. The tracking systems consist of a
silicon-strip system with 4750,000 channels
around the beam-pipe, followed by the Central
Outer Tracker (COT), a large cylindrical drift
chamber with 30,240 sense wires arranged in 96
layers divided into 8 superlayers of 12 wires
each [1]. Four of the layers have the wires parallel
to the beam axis; the remaining four are tilted by
2 to provide small-angle stereo for 3D reconstruction of tracks. The maximum drift time of the
COT is 200 ns; the maximum drift length is
0.88 cm.
During the present Run II, which started in
2001, the peak luminosity of the Tevatron has
grown to over 1032 cm2 s1 , a factor of more than
ve higher than in Run I. The Tevatron operates
with a time between beam crossings of 396 ns, with
the result that the occupancy (hits/channel) in the
COT increases with luminosity as the average
number of protonantiproton collisions per bunch
crossing is now substantially greater than one.
A broad range of efforts are underway to upgrade
the readout bandwidth to allow operation at
luminosities up to 3 1032 cm2 s1 .
The COT is used to provide a precise measurement in the magnetic spectrometer of the trajectories of the particles produced in the high-energy
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Fig. 1. The CDF-II TDC board. The two large chips with silver
heat sinks are the TDC FPGAs; the large black objects are DCto-DC converters (the layout allows addition DC-to-DC
converters, not needed and hence not stuffed on this board).
The FPGA for the VME interface can be seen in the upper lefthand corner. Connector headers and dip switches near the
center of the board allow debugging with a logic analyzer.
2. TDC Specications
A summary of the TDC physical and operational characteristics is given in Table 1. The
schematics of the board are available at [11].
Details of how the TDC operates are given in the
text below.
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Table 1
The physical and operational characteristics of the CDF-II TDC
Characteristic
Values
Comment
96
1.2 ns
p7 hits
4.8 ns
304.8 ns
4.8 ns
304.8 ns
o200 ps
p1 count
o100 ps
512 words=6:144 ms
512 words=6:144 ms
p64 words/768 ns
12 ms after L2A
12 ms
48/FPGA
6
6 ns
11/wire
80 ns after BC
32 bits/ 22 ns
43 pins
Readout characteristics
VME interface
VME readout modes
CBLT64 transfer rate
Test modes
VME64
A32/D32, A32/D64
47 MBytes/s
Data generator
Implemented in FPGA
D64 in CBLT mode only
Burst speed
Internal 8192 wordmemory
Physical characteristics
Physical format
Power requirements (V/A)
Input connectors
Input levels
Front panel LEDs
Trigger output connector
9U VME
5 V=15 A; 5 V=2 A
68-pin
LVDS
1 Triple LED/FPGA
VME P3
TTL, on VME P3
Mini-D Ribbon
CDF uses quasi-LVDS [12]
Congurable in rmware
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Leading edge
Trailing edge
0ns
Input pulse
12ns clock
bit 9
bit 8
bit 7
OUTPUT
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Word 0
Word 1 Word 2
Word 3
Word 4
Word 5
Word 6
Fig. 2. An example serial-to-parallel conversion of one of the 96 input channels into a 10-bit-wide parallel data stream as seen in the
Quartus II [14] simulation window. The top two traces are one input line from the tracking chamber and the locally-generated 12-ns
clock. The next 10 traces are the 10 bits of parallel data from the serial-to-parallel conversion, output as one word every 12 ns. The
parallel data, shown at the bottom of the gure, are then examined two words at a time for transitions that signify a leading or trailing
edge of a hit in the COT.
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TDC Chip_1
VME
STRATIX
EP20K100QC240-3V
FP Conn3
68 pin LVDS
From COT
Receiver
EP1S30F780C6
CDF_CLK_DEL
FP Conn2
68 pin LVDS
449
VME
P
2
CDF Control
VME
Receiver
2 x 3D3418-0.25S
VME Buffer
VME Buffer
FP Conn4
68 pin LVDS
Receiver
M. Bogdan et al. / Nuclear Instruments and Methods in Physics Research A 554 (2005) 444457
TDC Chip_0
Buffer
FP Conn1
68 pin LVDS
Receiver
STRATIX
EP1S30F780C6
P
to XFT
3
Fig. 3. The physical layout of the TDC board. The four input connectors, each with 24 LVDS channels, are on the left; the VME
backplane connectors are on the right. The elements are described in turn in the text.
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L2 Buffers
Inputs from COT
00
The Pipeline
SERDES
MUX
IN
MASK*
01
RAM*
512 words
10
write
r ead
RAM*
64 words
Edge
Detector*
11
TEST-DATA RAM*
L2A
To VME
Interface
VME
Decoder
L1A
VME
Access(*)
XFT
Block*
CDF CLOCK
XFT-DAQ*
To P3
PLL
Delayed
Tx Pulse
12ns , 22ns , 66ns
clocks
RAM*
512 words
SERDES
OUT
Tx Out Pulse
to front panel
Fig. 4. The functional block diagram of the TDC FPGA (TDC Chip). All processing is determined by programming in rmware. Each
Chip handles 48 LVDS channels (shown as coming into the SERDES block in the upper left). The prompt trigger ags for the XFT
trigger processor are output through the P3 VME connector. Data are read out by the CDF Data Acquisition system from the Hit
Count and Hit Data Buffers. An asterisk indicates registers or memories that are VME-accessible. The individual blocks in the diagram
are described in the text.
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[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Sample data
Time value
0
0
1
1
1
2
1
3
1
4
0
5
0
6
0
7
0
8
1
9
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Trigger Bits
Data Stream
48 Occupancy Detectors
Time-window
enable bits
Time-window
clear bits
CDF_CLK
BC
Trigger
Logic
Control
Output
Multiplexer
Trigger
Primitives
B0
BC Delayed
Fig. 5. Block diagram of the TDC XFT Logic. The data stream comes from the MUX/MASK Block (Section 5.1) as 480-bit words
every 12 ns. The CDF_CLK, BC and B0 signals are the 132 ns CDF master clock, and the Bunch Crossing and Bunch Zero signals
generated by the Tevatron, and are transmitted to the VME backplane through the CDF DAQ system [16]. The TDC XFT block sends
out the Trigger Primitives, which are the multiplexed trigger bits, and trigger control signals.
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Trigger Logic Control (TLC). The TLC controls the XFT logic. Every 12 ns the Trigger
Logic Control block sends 22 bits, two per timewindow to the Occupancy Detectors dening
which 11 time-windows are enabled for this
clock cycle. All Occupancy Detectors get the
same 22 time-window bits. These time-window
bits are stored in a 22-bit wide RAM, accessible
via VME. The RAMs Address Counter is
incremented every 12-ns clock and hence the
time-window bits refresh every 12 ns. The
Address Counter starts to count on receiving
an XFT-Enable pulse, which is adjusted to be
delayed by the same amount as the COT data
stream relative to the Bunch Crossing (BC) and
Bunch Zero (B0).
Output Multiplexer (OM). This receives the
trigger bits from the 48 Occupancy Detectors
and sends the Trigger Primitives in parallel
to the P3 backplane. Each OM sends out a
16-bit Trigger Primitive word every 22 ns on
the P3 connector to the XFT. The signals
are buffered to the P3 connector as TTL levels.
The OM also sends synchronously a Word_0
marker, the B0 marker if appropriate (i.e. the
crossing is that of the Tevatron bunch 0), and
an alignment signal (Data Strobe). The OM
does not perform any logical operations on
the trigger bits, but sends them in the order
required by the XFT [18].
The existing cables to the XFT have too low a
band-width to transmit the 22-ns Main Clock as
a data strobe, and so Trigger Primitive bits are
sent on the leading and trailing edges of a
slower clock which is also transmitted on the
cables. The Data Strobe (DS) is a 44 ns clock
formed from doubling the period of the Main
Clock. Thirty-two bits, 16 from each TDC
Chip, are sent every 22 ns, with 18 such cycles in
the beam-crossing period of 396 ns.
5.4.1. TDC XFT-DAQ Block
The TDC XFT-DAQ block of the rmware,
used for testing and diagnostic purposes only,
connects to a dedicated DAQ system similar to the
hit-data stream. It has the same structure, consisting of a Pipeline, L2 buffers, and VME-readout
buffers, and follows the same L1A/L2A sequence
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200
Avg CNT=175.0
Avg CNT=158.4
Avg CNT=142.0
Avg CNT=125.0
150
100
Avg CNT=108.1
Avg CNT=91.5
Slope is 1-count/1.202 ns
50
00
T0 +0 ns
+20 ns
+40 ns
+60 ns
+80 ns
+100 ns
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Acknowledgements
We thank Bill Badgett, Frank Chlebana, Pat
Lukens, Aseet Mukherjee, and Kevin Pitts for
help, support, and advice. Nils Krumnack and Ed
Rogers deserve special thanks for providing
critical input on the XFT specications and the
design of the XFT sections of the TDC. We thank
Rich Northrop for the picture of the board.
This work was supported in part by the
National Science Foundation under Grant No.
5-43270, and the US Department of Energy.
References
[1] T. Affolder, et al., Nucl. Instr. and Meth. A 526 (2004)
249.
[2] The CDF-II detector is described in the CDF Technical
Design Report (TDR), FERMILAB-Pub-96/390-E. The
TDC described here is intended as a further upgrade
beyond that described in the TDR.
[3] R.S. Moore [the CDF Run II collaboration], A custom 96channel VME TDC for the CDF detector for Tevatron
collider Run II; FERMILAB-CONF-04-262 Prepared for
2004 IEEE Nuclear Science Symposium and Medical
Imaging Conference (NSS/MIC), Rome, Italy, 1622
October 2004.
[4] D.I. Porat, IEEE Trans. Nucl. Sci. NS-20 (1973) 36.
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[5] J. Kalisz, Metrologia 41 (2004) 17
http://www.iop.org/EJ/abstract/0026-1394/41/1/004.
[6] J.F. Genat, Nucl. Instr. and Meth. A 315 (13) (1992) 411.
[7] An extensive list of references can be found in:
A. Mantyniemi, A High Resolution Time-to-Digital
Converter Based on Stabilised Three-stage Delay Line
Interpolation, Department of Electrical and Information
Engineering, University of Oulu; OULU 2004 Thesis;
ISBN 951-42-7460-I;ISBN 951-42-7460-X; http://herkules.
oulu./isbn951427461X/isbn951427461X.pdf
[8] J. Kalisz, R. Szplet, J. Pasierbinski, A. Poniecki, IEEE
Trans. Instrum. Meas. 46 (1997) 51.
[9] ANSI/VIPA 23-1998, March 22, 1998. These crates
support geographical addressing. Chain Block Transfer is
described in Appendix E.
[10] T. Shaw, G. Sullivan, A Standard Front-End Trigger
VME Bus-Based Readout Crate for the CDF Upgrade,
CDF/DOC/TRIGGER/CDFR/2388, May 12, 1998. The
CDF readout crate is a 21-slot 9U VME crate based on the
VIPA standard, with added bussed signals on rows A and
C of the P2 connector. All 64 of the user-dened pins on
these rows are bussed between slots 2 and 21 using the
same termination scheme as the standard VME bussed
lines. Additional power pins are provided on the P0
connector. The J3 backplane, which is physically separate
from J1/J2, is customized for I/O specic to each CDF
subsystem.
[11] The schematics and test results are available online
at: http://edg.uchicago.edu/bogdan/tdc/index.html. The
rmware is in CVS at http://www-cdfonline.fnal.gov/
cgi-bin/cvsweb.cgi/NuTDC. The schematics and code are
available on request.
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