EE 311 Notes/Prof Saraswat

Handout # 2

Trends in Integrated Circuits Technology

Semiconductors have become increasingly more important part of world
economy

Silicon CMOS has become the pervasive technology

Handout # 2

Minimum lithographic
feature size (m)

Transistors or bits per chip

EE 311 Notes/Prof Saraswat

Year
Ref:

Year
Technology node
(DRAM half pitch)
Minimum Feature
Size
DRAM Bits/Chip
DRAM Chip Size
(mm2 )
Microprocessor
Transistors/chip
Maximum Wiring
Levels
Minimum Mask
Count
Minimum Supply
Voltage (volts)

A. I. Kingon et al., Nature 406, 1032 (2000).

1997
250 nm

1999
180 nm

2003
130 nm

2006
100 nm

2009
70 nm

2012
50 nm

180 nm

120 nm

70 nm

60 nm

40

30

256M
280

1G
400

4G
560

16G
790

64G
1120

256G
1580

11M

21M

76M

200M

520M

1.40B

6-7

7-8

8-9

22

22/24

24

24/26

26/28

28

1.8-2.5

1.5-1.8

1.2-1.5

0.9-1.2

0.6-0.9

0.5-0.6

Future projections for silicon technology taken from the SIA ITRS 1999
2

EE 311 Notes/Prof Saraswat

Handout # 2

Ref. H. komiya IEEE ISSCC 1993

Device structures are becoming increasingly more complex

The scaling trends for Intel microprocessors.

3

EE 311 Notes/Prof Saraswat

Handout # 2

MOS Device Scaling

L
xox

Scaled MOS Transistor

Xj

N+

N+

Na

D
N+

N+

lo

P
Why do we scale MOS transistors?
1. Increase device packing density
2.

Improve frequency response (transit time)

1
L

3. Improve current drive (transconductance gm)

gm =

ID
VG VD = const

L n
W

L n

Kox
V
for VD < VD SAT , linear region
to x D
Kox
(VG VT ) for VD > VDSAT , saturation region
to x

Decreasing the channel length and gate oxide thickness increases gm, i.e., the current drive
of the transistor. Much of the scaling is therefore driven by decrease in L and tox. However if
only these two parameters are scaled many problems are encountered, e.g., increased
electric field.
The most widely used scaling rule is to maintain the electric field in the device constant

Device/Circuit Parameter
Dimension :
x o x, L, W, Xj,
Substrate doping :
Na
Supply voltage :
V
Supply current :
I
Gate Capacitance :
W L/xo x
Gate delay :
CV/I
Power dissipation :
C V2 / delay
Delay power product :

Constant Field Scaling Factor

1/K
K
1/K
1/K
1/K
1/K
1/K2
1/K3
4

EE 311 Notes/Prof Saraswat

Handout # 2

Speed increases as a result of scaling

109

10

the effect of better

microprocessor
architectures

Number of
Instructions 107
per Second

486

speed doubles each

3-yr generation
10

10

Pentium

386

80286
8080
Intel Microprocessors
4004

104

1965

1975

1985

1995

So Does the Cost of a Factory

10,000

2x every 4 years
1000

cost of a modern
wafer fab
100
($ million)

2x every 3 years

1.47x every 2 years

10

1960

1970

1980

1990

2000

EE 311 Notes/Prof Saraswat

Handout # 2

In reality constant field scaling has not been observed strictly. Since the transistor
current is proportional to the gate overdrive (VG-VT), high performance demands have
dictated the use of higher supply voltage. However, higher supply voltage implies
increased power dissipation (CV2f). In the recent past low power applications have
become important and have required a scaling scenario with lower supply voltage.

Ref: Davri, et al. Proc. IEEE, April 1995

In general the device scaling methodology does not take into account many other chip
performance and reliability issues, e.g., interconnects, contacts, isolation, etc. These
factors are now becoming an obstacle in the evolution of integrated circuits.
How far can we continue to scale?

(Source: J. Plummer)

EE 311 Notes/Prof Saraswat

Handout # 2

Effect of Reducing Channel Length: Drain Induced Barrier Lowering

Gate
N+ source

L
Depletion
region
L

N+ drain
rj

P-Si

QB depleted
by source

QB depleted
by drain

In devices with long channel lengths, the gate is completely responsible for depleting
the semiconductor (QB). In very short channel devices, part of the depletion i s
accomplished by the drain and source bias. Since less gate voltage is required to
deplete QB, the barrier for electron injection from source to drain decreases

Potential variation along the channel for MOS transistors with 2.5
and 0.5 m channel lengths. The 0.5 m device shows DIBL effect.
The reduction in the barrier is known as drain induced barrier lowering (DIBL). DIBL
results in an increase in drain current at a given VG. Therefore VT as L. Similarly, as

EE 311 Notes/Prof Saraswat

Handout # 2

VD , more QB is depleted by the drain bias, and hence ID and VT. This is

An approximate relation for threshold voltage due to DIBL is:

VT = VFB 2 F

QB
Cox

r
2 W
1 1 +
1 j
rj
L

To minimize the effect of DIBL:

Cox should be increased, i.e., decrease gate oxide thickness.
This results in increased control of the gate.
Decrease junction depth (rj )
Scaling of gate oxide thickness and junction depth causes many other problems.

Hot Carrier Effects

For a reverse biased p-n junction discussion we remember that the maximum electric
field intensity is near the junction itself and it increases with the reverse bias.

max =

2qN a ( i VD )
ox

In the case of MOS transistor the potential drop along the channel is not uniform with
most of it across the reverse biased drain-substrate junction. Therefore the electric
field intensity is also non-uniform with the maximum occurring near the drain junction.
As the channel length is reduced the electric field intensity in the channel near the
drain increases more rapidly in comparison to the long channel case, even if VD i s
scaled, as i does not scale.

EE 311 Notes/Prof Saraswat

Handout # 2

The free carriers passing through the high-field can gain sufficient energy to cause
several hot-carrier effects. This can cause many serious problems for the device
operation.
Hot carriers can have sufficient energy to overcome the oxide-Si barrier. They are
injected from channel to the gate oxide (process 1) and cause gate current to flow.
Trapping of some of this charge can change VT permanently. Avalanching can take
place producing electron-hole pairs (process 2). The holes produced by avalanching
drift into the substrate and are collected by the substrate contact (process 3) causing
Isub IR drop due to Isub(process 4) can cause substrate-source junction to be
forward biased causing electrons to be injected from source into substrate (process
5). Some of the injected electrons are collected by the reversed biased drain and
cause a parasitic bipolar action (process 5).

EE 311 Notes/Prof Saraswat

Handout # 2

Scaling of MOS Gate Dielectric

(Ref: S. Asai, Microelectronics Engg., Sept. 1996)

By the end of this decade the MOS gate dielectric thickness will be well below 10 .
ID gm

K
thickness

How far can we push MOS gate dielectric thickness?

How will we grow such a thin layer uniformly?
How long will such a thin dielectric live under electrical stress?
Can we improve the endurance of the dielectric by changing its structure?

Problems in scaling gate oxide

Polysilicon gate electrode

Dopant
penetration

Leakage current
gate oxide
Reliability due to
charge injection

Defects and
nonuniformity of film
Dielectric breakdown
Si substrate

10

EE 311 Notes/Prof Saraswat

Handout # 2

Gate Dielectric Degradation and Breakdown

Under high field electrons are injected in the SiO2 conduction band because of
reduction in barrier height and thickness. Some electrons gain excess energy in the
conduction band of the oxide. At the anode they lose kinetic and potential energy
causing physical damage leading to traps generation. Further trapping of electrons
and holes causes dielectric degradation.

Cathode

(1) Electron injection

(2) Energy released by hot electron
(3) Bond breaking at the interface - trap generation
(4) Hot hole generation by impact ionization and injection
(5) Energy released by hot hole - trap generation
(6) Hydrogen release - trap generation

(1)

(3)
e

Oxide
(5)
h

(2)
(6)

Anode

(3) e
Hydrogen
(4)
h
Ref: Apte & Saraswat IEEE Trans. Electron Dev., Sept 1994

We can improve the endurance of the dielectric by optimizing the process technology
and changing its structure. For example incorporating nitrogen or fluorine instead of
hydrogen strengthens the Si/SiO2 interface and increases the gate dielectric lifetime
because Si-F and Si-N bonds are stronger than Si-H bonds.

Poly-Si Gate
Oxide

N or F

Si substrate

11

EE 311 Notes/Prof Saraswat

Handout # 2

Problems caused by conduction in ultrathin gate oxide

As we decrease the gate dielectric thickness, the conduction through the dielectric
film becomes appreciable. This may increase power dissipation and cause problems
for circuit stability. Increased leakage due to direct tunneling through the gate
dielectric may make dynamic and static circuits unstable.
Thick Oxide
Thin Oxide
Fowler-Nordheim Tunneling
Direct Tunneling
Oxide
Si

Si

(Ref: From Y. Taur et al., Proc. IEEE, April 1997.)

Gate Leakage Current Density Versus Gate

Voltage for Various Oxide Thicknesses
12

EE 311 Notes/Prof Saraswat

Handout # 2

Current (A/m)

1000

Ion

10
0.1
Ioff

0.001
Source G. Bersuker, et al. Sematech

Igate

0.00001
50

70

100

130

180

Technology Generation (nm)

Rather than scaling thickness of SiO2 perhaps we can scale the dielectric constant (K)
to improve the performance. Alternatively for the same performance we can increase
the dielectric thickness by increasing its K.

K
ID gm
thickness
high K > 20

SiO2 K 4

40

20
Today

100
Si 3N4 K 8
Near future

Long term

Near term and long term approaches for scaling the MOS gate dielectric.

However, replacing SiO2 by another dielectric is a very difficult task as it is

one of the best dielectrics and is one of the main reasons of the success
of Si technology.

13

EE 311 Notes/Prof Saraswat

Handout # 2

Scaling of Ohmic Contacts and Junctions

Silicide
metal

Poly-Si

Rc

Xj
source

Rs

Rs

Rch

Rd

Rd
drain

Device scaling dictates shallow junctions.

How will we form such shallow junctions?
How will we make low resistance contacts to them?
What will be the impact of the resistance of the contacts and junctions?

Rc

Source: Jasonn Woo, UCLA

Year
Min Feature Size
Contact xj (nm)
xj at Channel (nm)

1997
0.18
100-200
50-100

1999
0.12
70-140
36-72

2003
0.07
50-100
26-52

2006
0.06
40-80
20-40

2009
0.04
15-30
15-30

2012
0.03
10-20
10-20

14

EE 311 Notes/Prof Saraswat

Handout # 2

Specific contact resistivity

2
c = co exp B
qh

sm*

ohm cm 2

where B is the barrier height and N is the doping density in the

semiconductor.
Problem in scaling:
Contact resistance is a strong function of doping density at the
metal/silicon interface
Sheet resistance of a junction is a strong function of doping density in
the junction
However, the maximum doping density is limited by solid solubility and
it does not scale !

15

EE 311 Notes/Prof Saraswat

Handout # 2

Solutions to Shallow Junction Problem

Shallow extension implants to minimize (DIBL)

Elevated source/ drain to minimize (DIBL)

Silicidation to junction minimize resistance

16

EE 311 Notes/Prof Saraswat

Handout # 2

Scaling of Device Isolation Technologies

Isolation pitch as a function of minimum dimension
2.5
2.0
16M
64M

1.5
1G

1.0
0.5
0.0

0.0

0.2

0.4

0.6

Minimum dimension [m]

0.8

1.0

P. Fazan, Micron, IEDM-93

LOCOS based isolation technologies have serious problems in loss of area due to
birds beak.
Semi-recessed LOCOS
Nitride

Nitride

Pad oxide

Field oxide
After field oxidation

Fully recessed LOCOS

Nitride
Pad oxide

After field oxidation

Large stresses can build up in LOCOS based isolation technologies.

F2
F3
F1
F4

17

EE 311 Notes/Prof Saraswat

Handout # 2

Shallow trench isolation

P-substrate

N-well

Deep trench isolation

Trench isolation can minimize area loss, however, large stresses can build up in
trench structures resulting in bandgap reduction and eventually if the stress is too
much it can cause crystal defects leading to increase in leakage and yield loss.
10-11
N+ P

10-12

Distance [m]

10-13

10-14 0

500
1000
Compressive stress [MPa]

1500

The stress is a function of process temperatures as at higher temperatures SiO2 has

viscous flow which can relieve the stress. However, thermal budget demands low
temperature processing.
103
900 C
102
1000 C
101
1100 C

100

1
10
Active area pitch [ m]

100

18

EE 311 Notes/Prof Saraswat

Handout # 2

Source: J. D. Meindl, , Integration Limits on XXI Century Gigascale Integration, IEEE

Interconnect Technology Conf. Short Course, San Francisco, CA, May 31, 1998

1E8
Local

Semiglobal Global

1E6
1E4

LSemi-global

1E2
2D

LLocal

1E0

3D

1E-2
1E-4
1

10
100
1000
Interconnect Length, l (gate pitches)

Number of interconnects are increasing

Most of the interconnects are very short but a few are very long

19

EE 311 Notes/Prof Saraswat

Handout # 2

Impact of Scaling of Interconnections on Circuit Performance

Chip area is increasing => length of the longest wire is increasing

Cross sectional dimensions of the interconnects are decreasing resulting in an
increase in resistance and capacitance
Increased R and C results in higher signal propagation delay

500
400

CAPACITANCE
Line To Ground
Line To Line
Total

300
200

Capacitance (fF/mm)

100
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Space Width (m) [=Line Width]

Higher Packing Density

Decreased Space Between

Interconnects

Higher RC-Delay

20

EE 311 Notes/Prof Saraswat

Handout # 2

Parasitic resistance and capacitance associated with interconnections and

contacts are
now begining to influence circuit performance and will be the primary factors in the
evolutions of submicron ULSI technology.

Lower resistivity metals and lower dielectric constant insulators will reduce the R and C

Delay (ns)

1.0

Interconnect Delay

0.1

Typical Gate Delay

0.01
60

80

100 120 140 160 180

Technology Generation (nm)

.

Copper 6

Copper 5
Copper 4
Copper 3
Copper 2
Copper 1

Tungsten
Local Interconnect

Current Cu technology (Courtesy of IBM)

21

EE 311 Notes/Prof Saraswat

Handout # 2

global

semiglobal

local

By increasing the levels of wires interconnect problem can be minimized. Shorter

(local) wires can be placed in thinner interconnects and longer (global) wires can be
made with larger cross section to minimize R and C.
14
13
12
11
10
9
8
7
6
5
4
3
2
1

Al & SiO2 ( = 4)
Cu & SiO2 ( = 4)

Al & low- ( = 2)

Cu & lo w- ( = 2)
0.09 0.13 0.18 0.25 0.35 m
2007 2004 2001 1998 1995 Year

Tec hnology Generation

Reduced resistivity and dielectric constant results in reduction in number of metal layers
as more wires can by placed in lower levels of metal layers.

22

EE 311 Notes/Prof Saraswat

Handout # 2

Problems in Scaling of Interconnections

Cu diffuses in most dielectrics readily and acts as a recombination center
in Si. Hence a barrier is generally needed to enclose Cu line to avoid its
diffusion in the dielectric. Barriers are generally highly resistive.

As decreases
Resistivity increases as grain size decreases
Resistivity increases as main conductor size decreases but not the
surrounding film size
Surrounded Interconnect
Cu

av

Barrier

Layered Interconnect
Al

Barrier
Al
Pure Metal
Interconnect
Cu

Minimum Feature Size ()

23

EE 311 Notes/Prof Saraswat

Handout # 2

4
3
2
1
0

35 50 70 100 130

180

1.2
1
0.8
0.6
0.4
0.2
0

Thermal Conductivity
[ W / mK ]

Dielectric Constant

Thermal Behavior
Energy dissipated (CV2f) is increasing as performance improves
Thermal conductivity of low-k insulators is poor
Average chip temperature is rising

30
25
20
15
10
5
0

5
4
3
2
1
0
35 50 70 100 130

180

Jmax [ MA / cm2 ]

Power Density [ W / cm2 ]

Technology Node [nm]

Technology Node [nm]

24

EE 311 Notes/Prof Saraswat

Handout # 2

Electromigration

Electromigration due to electron wind induced diffusion of Al through grain boundaries

SEM of hillock and voids formation due to electromigration in an Al(Cu,Si) line

Mean time to failure due to electromigration is given by

A
E
MTF = m n exp a
kT
r J

25

EE 311 Notes/Prof Saraswat

Handout # 2

Summary: Technology Progression

MOS Transistor in 2010
Gate oxide thickness 10
Channel Length < 500
Junction depth < 500
Size of an atom ~ 5
A Circuit in 2010
In integrated system
> 1 billion components
> 10 interconnect layers

26