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SN54HC574, SN74HC574

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS


WITH 3-STATE OUTPUTS
SCLS148F DECEMBER 1982 REVISED AUGUST 2003

D
D
D
D
D

SN54HC574 . . . J OR W PACKAGE
SN74HC574 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)

Wide Operating Voltage Range of 2 V to 6 V


High-Current 3-State Noninverting Outputs
Drive Bus Lines Directly or Up To 15 LSTTL
Loads
Low Power Consumption, 80-A Max ICC
Typical tpd = 22 ns
6-mA Output Drive at 5 V
Low Input Current of 1 A Max
Bus-Structured Pinout

OE
1D
2D
3D
4D
5D
6D
7D
8D
GND

description/ordering information
These octal edge-triggered D-type flip-flops
feature 3-state outputs designed specifically for
bus driving. They are particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.

20

19

18

17

16

15

14

13

12

10

11

VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK

2D
1D

SN54HC574 . . . FK PACKAGE
(TOP VIEW)

The eight flip-flops enter data on the low-to-high


transition of the clock (CLK) input.

3D
4D
5D
6D
7D

3 2 1 20 19
18

17

16

15

14
9 10 11 12 13

2Q
3Q
4Q
5Q
6Q

8D
GND
CLK
8Q
7Q

A buffered output-enable (OE) input can be used


to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines without interface or pullup components.

OE
VCC
1Q

D
D

ORDERING INFORMATION

PDIP N

SN74HC574N

Tube of 25

SN74HC574DW

Reel of 2000

SN74HC574DWR

SSOP DB

Reel of 2000

SN74HC574DBR

HC574

SOP NS

Reel of 2000

SN74HC574NSR

HC574

Tube of 70

SN74HC574PW

Reel of 2000

SN74HC574PWR

Reel of 250

SN74HC574PWT

CDIP J

Tube of 20

SNJ54HC574J

SNJ54HC574J

CFP W

Tube of 85

SNJ54HC574W

SNJ54HC574W

LCCC FK

Tube of 55

SNJ54HC574FK

TSSOP PW

55 C to 125
55C
125C
C

TOP-SIDE
MARKING

Tube of 20

SOIC DW
C
40C
40
C to 85
85C

ORDERABLE
PART NUMBER

PACKAGE

TA

SN74HC574N
HC574

HC574

SNJ54HC574FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.


Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

On products compliant to MIL-PRF-38535, all parameters are tested


unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

SN54HC574, SN74HC574
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS148F DECEMBER 1982 REVISED AUGUST 2003

description/ordering information (continued)


OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
FUNCTION TABLE
(each flip-flop)
INPUTS
OE

CLK

OUTPUT
Q

H or L

Q0

logic diagram (positive logic)


OE
CLK

1
11

C1
1D

19

1Q

1D

To Seven Other Channels

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA
Package thermal impedance, JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

SN54HC574, SN74HC574
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS148F DECEMBER 1982 REVISED AUGUST 2003

recommended operating conditions (see Note 3)


SN54HC574
VCC
VIH

Supply voltage
VCC = 2 V
VCC = 4.5 V

High-level input voltage

VCC = 6 V
VCC = 2 V
VIL
VI
VO
t/v
t/ v

Low-level input voltage

NOM

MAX

MAX

3.15

3.15

4.2

4.2

UNIT
V
V

0.5

0.5

1.35

1.35

1.8

1.8

VCC
VCC

VCC = 2 V
VCC = 4.5 V

Input transition rise/fall time

NOM

1.5

Output voltage

MIN

1.5

VCC = 4.5 V
VCC = 6 V

Input voltage

SN74HC574

MIN

VCC
VCC

1000

1000

500

500

V
V
V
ns

VCC = 6 V
400
400
TA
Operating free-air temperature
55
125
40
85
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless


otherwise noted)
PARAMETER

VOH

VOL

TEST CONDITIONS

VI = VCC or 0,

SN54HC574
MIN

MAX

SN74HC574
MIN

MAX

UNIT

2V

1.9

1.998

1.9

1.9

4.4

4.499

4.4

4.4

6V

5.9

5.999

5.9

5.9

IOH = 6 mA
IOH = 7.8 mA

4.5 V

3.98

4.3

3.7

3.84

6V

5.48

5.8

5.2

5.34

2V

0.002

0.1

0.1

0.1

IOL = 20 A
A

4.5 V

0.001

0.1

0.1

0.1

6V

0.001

0.1

0.1

0.1

4.5 V

0.17

0.26

0.4

0.33

6V

0.15

0.26

0.4

0.33

6V

0.1

100

1000

1000

nA

6V

0.01

0.5

10

160

80

10

10

10

pF

IOL = 6 mA
IOL = 7.8 mA

ICC
Ci

TA = 25C
TYP
MAX

4.5 V

VI = VIH or VIL

VI = VCC or 0
VO = VCC or 0

MIN

IOH = 20 A
A
VI = VIH or VIL

II
IOZ

VCC

IO = 0

6V
2 V to 6 V

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

SN54HC574, SN74HC574
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS148F DECEMBER 1982 REVISED AUGUST 2003

timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
TA = 25C
MIN
MAX

VCC

fclock

Clock frequency

tw

Pulse duration, CLK high or low

tsu

Setup time, data before CLK

th

Hold time, data after CLK

SN54HC574
MIN

MAX

SN74HC574
MIN

MAX

2V

4.5 V

30

20

24

6V

38

24

28

2V

80

120

100

4.5 V

16

24

20

6V

14

20

17

2V

100

150

125

4.5 V

20

30

25

6V

17

26

21

2V

4.5 V

6V

UNIT

MHz

ns

ns

ns

switching characteristics over recommended operating free-air temperature range, CL = 50 pF


(unless otherwise noted) (see Figure 1)
PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

fmax

tpd

ten

tdis

tt

CLK

OE

OE

Any Q

Any Q

Any Q

Any Q

VCC

TA = 25C
MIN
TYP
MAX

SN54HC574
MIN

MAX

SN74HC574
MIN

2V

11

4.5 V

30

36

20

24

6V

36

40

24

MAX

MHz

28

2V

90

180

270

225

4.5 V

28

36

54

45

6V

24

31

46

38

2V

77

150

225

190

4.5 V

26

30

45

38

6V

23

26

38

32

2V

52

150

225

190

4.5 V

24

30

45

38

6V

22

26

38

32

2V

28

60

90

75

4.5 V

12

18

15

6V

10

15

13

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

UNIT

ns

ns

ns

ns

SN54HC574, SN74HC574
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS148F DECEMBER 1982 REVISED AUGUST 2003

switching characteristics over recommended operating free-air temperature range, CL = 150 pF


(unless otherwise noted) (see Figure 1)
PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

fmax

tpd

ten

tt

CLK

OE

Any Q

Any Q

Any Q

VCC

MIN

TA = 25C
TYP
MAX

SN54HC574
MIN

MAX

SN74HC574
MIN

2V

4.5 V

30

24

6V

36

28

MAX

UNIT

MHz

2V

105

265

400

330

4.5 V

36

53

80

66

6V

31

46

68

57

2V

95

235

355

295

4.5 V

32

47

71

59

6V

28

41

60

51

2V

60

210

315

265

4.5 V

17

42

63

53

6V

14

36

53

45

ns

ns

ns

operating characteristics, TA = 25C


PARAMETER
Cpd

Power dissipation capacitance per flip-flop

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

TEST CONDITIONS

TYP

UNIT

No load

100

pF

SN54HC574, SN74HC574
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS148F DECEMBER 1982 REVISED AUGUST 2003

PARAMETER MEASUREMENT INFORMATION


VCC

From Output
Under Test
CL
(see Note A)

PARAMETER

S1

Test
Point

tPZH

ten

RL

1 k

tPZL
tPHZ

tdis

S2

RL

tPLZ

tpd or tt

1 k

Data
Input

VCC

50%
10%

50%

50%
0V

In-Phase
Output

50%
10%

tPHL
90%

90%

tr
tPHL
Out-ofPhase
Output

90%

tf

Open

Closed

Closed

Open

Open

Open

VCC

th

90%

90%

VCC
50%
10% 0 V
tf

50%
10%

Output
Control
(Low-Level
Enabling)

VCC
50%

50%
0V

tPZL
VOH
50%
10% V
OL
tf

tPLH
50%
10%

Open

VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES

VCC

tPLH

Closed

tr

VOLTAGE WAVEFORMS
PULSE DURATIONS

50%

Closed

0V

0V

Input

Open

tsu

0V

50%

50 pF
or
150 pF

50%

50%
tw

Low-Level
Pulse

S2

50 pF
or
150 pF

Reference
Input

VCC
50%

S1

50 pF

LOAD CIRCUIT

High-Level
Pulse

CL

90%

VOH
VOL

Output
Waveform 1
(See Note B)

tPLZ

10%

tPZH
Output
Waveform 2
(See Note B)

VCC

VCC
50%

VOL

tPHZ
50%

90%

VOH
0 V

tr

VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES

VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS

NOTES: A. CL includes probe and test-fixture capacitance.


B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns.
D. For clock inputs, fmax is measured when the input duty cycle is 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. tPLZ and tPHZ are the same as tdis.
G. tPZL and tPZH are the same as ten.
H. tPLH and tPHL are the same as tpd.

Figure 1. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM


www.ti.com

28-Feb-2005

PACKAGING INFORMATION
Orderable Device

Status (1)

Package
Type

Package
Drawing

Pins Package Eco Plan (2)


Qty

JM38510/65604BRA

ACTIVE

CDIP

20

None

Call TI

Level-NC-NC-NC

SN54HC574J

ACTIVE

CDIP

20

None

Call TI

Level-NC-NC-NC

SN74HC574DBR

ACTIVE

SSOP

DB

20

2000

Pb-Free
(RoHS)

CU NIPDAU

Level-2-260C-1 YEAR/
Level-1-235C-UNLIM

SN74HC574DW

ACTIVE

SOIC

DW

20

25

Pb-Free
(RoHS)

CU NIPDAU

Level-2-250C-1 YEAR/
Level-1-235C-UNLIM

SN74HC574DWR

ACTIVE

SOIC

DW

20

2000

Pb-Free
(RoHS)

CU NIPDAU

Level-2-250C-1 YEAR/
Level-1-235C-UNLIM

SN74HC574N

ACTIVE

PDIP

20

20

Pb-Free
(RoHS)

CU NIPDAU

Level-NC-NC-NC

Lead/Ball Finish

MSL Peak Temp (3)

SN74HC574N3

OBSOLETE

PDIP

20

None

Call TI

SN74HC574NSR

ACTIVE

SO

NS

20

2000

Pb-Free
(RoHS)

CU NIPDAU

Call TI
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM

SN74HC574PW

ACTIVE

TSSOP

PW

20

70

Pb-Free
(RoHS)

CU NIPDAU

Level-1-250C-UNLIM

SN74HC574PWR

ACTIVE

TSSOP

PW

20

2000

Pb-Free
(RoHS)

CU NIPDAU

Level-1-250C-UNLIM

SN74HC574PWT

ACTIVE

TSSOP

PW

20

250

Pb-Free
(RoHS)

CU NIPDAU

Level-1-250C-UNLIM

SNJ54HC574FK

ACTIVE

LCCC

FK

20

None

Call TI

Level-NC-NC-NC

SNJ54HC574J

ACTIVE

CDIP

20

None

Call TI

Level-NC-NC-NC

SNJ54HC574W

ACTIVE

CFP

20

None

Call TI

Level-NC-NC-NC

(1)

The marketing status values are defined as follows:


ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)

Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DATA
MLCC006B OCTOBER 1996

FK (S-CQCC-N**)

LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

18

17

16

15

14

13

NO. OF
TERMINALS
**

12

19

11

20

10

MIN

MAX

MIN

MAX

20

0.342
(8,69)

0.358
(9,09)

0.307
(7,80)

0.358
(9,09)

28

0.442
(11,23)

0.458
(11,63)

0.406
(10,31)

0.458
(11,63)

21

22

44

0.640
(16,26)

0.660
(16,76)

0.495
(12,58)

0.560
(14,22)

23

52

0.739
(18,78)

0.761
(19,32)

0.495
(12,58)

0.560
(14,22)

24

6
68

0.938
(23,83)

0.962
(24,43)

0.850
(21,6)

0.858
(21,8)

84

1.141
(28,99)

1.165
(29,59)

1.047
(26,6)

1.063
(27,0)

B SQ
A SQ

25

26

27

28

4
0.080 (2,03)
0.064 (1,63)

0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)

0.055 (1,40)
0.045 (1,14)

0.045 (1,14)
0.035 (0,89)

0.045 (1,14)
0.035 (0,89)

0.028 (0,71)
0.022 (0,54)
0.050 (1,27)

4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.

All linear dimensions are in inches (millimeters).


This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

MECHANICAL DATA
MSSO002E JANUARY 1995 REVISED DECEMBER 2001

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN
0,38
0,22

0,65
28

0,15 M

15

0,25
0,09
8,20
7,40

5,60
5,00

Gage Plane
1

14

0,25

08

0,95
0,55

Seating Plane
2,00 MAX

0,10

0,05 MIN

PINS **

14

16

20

24

28

30

38

A MAX

6,50

6,50

7,50

8,50

10,50

10,50

12,90

A MIN

5,90

5,90

6,90

7,90

9,90

9,90

12,30

DIM

4040065 /E 12/01
NOTES: A.
B.
C.
D.

All linear dimensions are in millimeters.


This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30
0,19

0,65
14

0,10 M

0,15 NOM
4,50
4,30

6,60
6,20
Gage Plane
0,25

7
0 8
A

0,75
0,50

Seating Plane
0,15
0,05

1,20 MAX

PINS **

0,10

14

16

20

24

28

A MAX

3,10

5,10

5,10

6,60

7,90

9,80

A MIN

2,90

4,90

4,90

6,40

7,70

9,60

DIM

4040064/F 01/97
NOTES: A.
B.
C.
D.

All linear dimensions are in millimeters.


This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TIs terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TIs standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
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Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products

Applications

Amplifiers

amplifier.ti.com

Audio

www.ti.com/audio

Data Converters

dataconverter.ti.com

Automotive

www.ti.com/automotive

DSP

dsp.ti.com

Broadband

www.ti.com/broadband

Interface

interface.ti.com

Digital Control

www.ti.com/digitalcontrol

Logic

logic.ti.com

Military

www.ti.com/military

Power Mgmt

power.ti.com

Optical Networking

www.ti.com/opticalnetwork

Microcontrollers

microcontroller.ti.com

Security

www.ti.com/security

Telephony

www.ti.com/telephony

Video & Imaging

www.ti.com/video

Wireless

www.ti.com/wireless

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