T Flip-Flop

Waveforms:

==============================================================================
*
Final Report
*
==============================================================================
Final Results:
RTL Top Level Output File Name : t_ff.ngr
Top Level Output File Name
: t_ff
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics:
# IOs

:5

Cell Usage:
# BELS
#
INV
# FlipFlops/Latches
#
FDRE
#
FDSE
# Clock Buffers
#
BUFGP
# IO Buffers
#
IBUF
#
OBUF

:2
:2
:2
:1
:1
:1
:1
:4
:2
:2

Device utilization summary:

Selected Device :
Number of Slices:
Number of Slice Flip Flops:
Number of 4 input LUTs:
Number of IOs:
Number of bonded IOBs:
Number of GCLKs:

3s400tq144-4
1 out of 3584 0%
2 out of 7168 0%
2 out of 7168 0%
5
5 out of 97 5%
1 out of
8 12%

Partition Resource Summary:

No Partitions were found in this design.

Timing Report:
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
Clock Signal
clk

| Clock buffer(FF name) | Load |

|
BUFGP
| 2 |

Asynchronous Control Signals Information:

No asynchronous control signals found in this design
Timing Summary:
Speed Grade: -4
Minimum period: 3.152ns (Maximum Frequency: 317.259MHz)
Minimum input arrival time before clock: 2.724ns
Maximum output required time after clock: 7.241ns
Maximum combinational path delay: No path found
Timing Detail:
All values displayed in nanoseconds (ns)
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 3.152ns (frequency: 317.259MHz)
Total number of paths / destination ports: 2 / 2
Delay:
3.152ns (Levels of Logic = 1)
Source:
q (FF)
Destination:
q (FF)
Source Clock: clk rising
Destination Clock: clk rising
Data Path: q to q
Gate Net
Cell:in->out
fanout Delay Delay Logical Name (Net Name)
FDRE:C->Q
2 0.720 0.877 q (q_OBUF)
INV:I->O
1 0.551 0.801 q_not00011_INV_0 (q_not0001)
FDRE:D
0.203
q
Total
3.152ns (1.474ns logic, 1.678ns route)
(46.8% logic, 53.2% route)
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 4 / 4
Offset:
2.724ns (Levels of Logic = 1)
Source:
rst (PAD)
Destination:
q (FF)
Destination Clock: clk rising
Data Path: rst to q
Gate Net
Cell:in->out
fanout Delay Delay Logical Name (Net Name)
IBUF:I->O
2 0.821
0.877 rst_IBUF (rst_IBUF)
FDRE:R
1.026
q
Total

2.724ns (1.847ns logic, 0.877ns route)

(67.8% logic, 32.2% route)

Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'

Total number of paths / destination ports: 2 / 2
Offset:
7.241ns (Levels of Logic = 1)
Source:
q (FF)
Destination:
q (PAD)
Source Clock: clk rising
Data Path: q to q
Gate Net
Cell:in->out
fanout Delay Delay Logical Name (Net Name)
FDRE:C->Q
2 0.720 0.877 q (q_OBUF)
OBUF:I->O
5.644
q_OBUF (q)
Total
7.241ns (6.364ns logic, 0.877ns route)
(87.9% logic, 12.1% route)
Total REAL time to Xst completion: 13.00 secs
Total CPU time to Xst completion: 13.60 secs
Total memory usage is 131564 kilobytes

RTL Schematic:

TTL Schematic:

XPower Analyzer:

Power summary:
Total estimated power consumption
Total Vccint 1.20V
Total Vccaux 2.50V
Total Vcco25 2.50V
Inputs
Outputs
Vcco25
Signals
Quiescent Vccint 1.20V
Quiescent Vccaux 2.50V

| I(mA) | P(mW) |
|
|
56
|
|
15 |
19
|
|
15 |
38
|
|
0
|
0
|
|
0
|
0
|
|
|
0
|
0
|
|
0
|
0
|
|
15 |
19
|
|
15 |
38 |