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Son una coleccin de datos binarios ubicados en la memoria de programa flash de una PIC
MCU.
Los Bits de configuracin estn programados en el PIC MCU con el cdigo de la aplicacin.
Bits de configuracin no son cdigo ejecutable como sus direcciones no son accesibles por el
contador de programa.
Cuando se programa en una PIC MCU configuracin de bits circuito completo que activa o
desactiva las caractersticas de hardware de la MCU.
Bits de configuracin estn "leer" al salir de un reinicio y no se pueden modificar en tiempo de
ejecucin.
Las caractersticas especiales de funcionamiento MCU controladas por los bits de configuracin
incluyen:
System Clocking
Gestin de energa
Seguridad del dispositivo
Caractersticas de funcionamiento
Los Bits de configuracin se generan por las directivas del compilador insertadas en el cdigo
fuente de la aplicacin. Cuando se construye un proyecto PIC MCU, los valores de los bits de
configuracin estn incrustadas en el archivo de salida HEX. Los bits de configuracin estn
programados en el PIC junto con el programa de aplicacin.
Los siguientes registros CONFIG1 & CONFIG2 son registros definidos
PIC24FJ128GA010:
para el MCU
Fast RC
The Fast RC (FRC) internal oscillator runs at a nominal frequency of 7.37 MHz. User software can tune
the FRC frequency. User software can optionally specify a factor (ranging from 1:2 to 1:256) by which the
FRC clock frequency is divided. This factor is selected using the FRCDIV<2:0> bits (CLKDIV<10:8>).
Primary
The primary oscillator can use one of the following as its clock source:
XT (Crystal): Crystals and ceramic resonators in the range of 3 MHz to 10 MHz. The crystal is
connected to the OSC1 and OSC2 pins.
HS (High-Speed Crystal): Crystals in the range of 10 MHz to 40 MHz. The crystal is connected to
the OSC1 and OSC2 pins.
EC (External Clock): The external clock signal is directly applied to the OSC1 pin.
Low-Power RC
The LPRC (Low-Power RC) internal oscIllator runs at a nominal frequency of 32.768 kHz. It is also used as
a reference clock by the Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM).
FRC
The clock signals generated by the FRC and primary oscillators can be optionally applied to an on-chip
Phase Locked Loop (PLL) to provide a wide range of output frequencies for device operation. PLL
configuration is described in Section 8.1.3 PLL Configuration.
The FRC frequency depends on the FRC accuracy (see Table 24-18) and the value of the FRC Oscillator
Tuning register (see Register 8-4).
For example, suppose a 10 MHz crystal is being used with the selected oscillator mode of XT with PLL.
If PLLPRE<4:0> = 0, then N1 = 2. This yields a VCO input of 10/2 = 5 MHz, which is within the
acceptable range of 0.8-8 MHz.
If PLLDIV<8:0> = 0x1E, then M = 32. This yields a VCO output of 5 x 32 = 160 MHz, which is
within the 100-200 MHz ranged needed.
If PLLPOST<1:0> = 0, then N2 = 2. This provides a Fosc of 160/2 = 80 MHz. The resultant device
operating speed is 80/2 = 40 MIPS.
Programando en el DSPIC
Utilizando la ecuacion:
(
(
Este
)
)
se declara en la programacin:
This is the default setting. The NOSC control bits (OSCCON<10:8>) do not control the clock selection
when clock switching is disabled. However, the COSC bits (OSCCON<14:12>) reflect the clock source
selected by the FNOSC Configuration bits.
The OSWEN control bit (OSCCON<0>) has no effect when clock switching is disabled. It is held at 0 at all
times.
8.2.2 OSCILLATOR SWITCHING SEQUENCE
Performing a clock switch requires this basic sequence:
1. If desired, read the COSC bits (OSCCON<14:12>) to determine the current oscillator source.
2. Perform the unlock sequence to allow a write to the OSCCON register high byte.
3. Write the appropriate value to the NOSC control bits (OSCCON<10:8>) for the new oscillator source.
4. Perform the unlock sequence to allow a write to the OSCCON register low byte.
5. Set the OSWEN bit (OSCCON<0>) to initiate the oscillator switch.
Once the basic sequence is completed, the system clock hardware responds automatically as follows:
1. The clock switching hardware compares the COSC status bits with the new value of the NOSC control
bits. If they are the same, the clock switch is a redundant operation. In this case, the OSWEN bit is cleared
automatically and the clock switch is aborted.
2. If a valid clock switch has been initiated, the LOCK (OSCCON<5>) and the CF (OSCCON<3>) status
bits are cleared.
3. The new oscillator is turned on by the hardware if it is not currently running. If a crystal oscillator must be
turned on, the hardware waits until the Oscillator Start-up Timer (OST) expires. If the new source is using
the PLL, the hardware waits until a PLL lock is detected (LOCK = 1).
4. The hardware waits for 10 clock cycles from the new clock source and then performs the clock switch.
5. The hardware clears the OSWEN bit to indicate a successful clock transition. In addition, the NOSC bit
values are transferred to the COSC status bits.
6. The old clock source is turned off at this time, with the exception of LPRC (if WDT or FSCM are
enabled) or LP (if LPOSCEN remains set).
If the PLL multiplier is used to scale the system clock, the internal FRC is also multiplied by the same
factor on clock failure. Essentially, the device switches to FRC with PLL on a clock failure.
Unlike the similar sequence with the oscillators LOCK bit, IOLOCK remains in one state until changed.
This allows all of the peripheral pin selects to be configured with a single unlock sequence followed by an
update to all control registers, then locked with a second lock sequence.
Programando en el DsPIC33F:
Each I/O pin on the device has an associated bit in the TRIS, PORT and LAT registers.
TRISx:
Determina si un pin es Entrada o Salida.
PORTx:
Los datos en los pines I/O son accedidos a travs de este registro. Una lectura del registro
PORTx lee los valores de los pines I/O, mientras una escritura al registro PORTX escribe un
valor al el Puerto de data latch.
Solo se usa en modo lectura ya que ocurren problemas con las instrucciones de read-modify
write.
LATx:
Registro asociado con los pines de I/O elimina el problema que ocurre con las instrucciones de
read-modify-write. Usado para escribir data en el Puerto.
Open-Drain Control Registers
Adems del PUERTO, LAT y TRIS registro para el control de datos, cada pin del puerto tambin
se puede configurar de forma individual, ya sea para la salida digital u open-drain. Esto es
controlado por el registro de control Open-Drain, ODCx, asociado con cada puerto.
Configuracin de cualquiera de los bits configura el pin correspondiente para actuar como una
salida-drenaje abierto.
La funcin de open-drain permite la generacin de salidas superior a VDD (por ejemplo, 5 V) en
cualquier slo digitales pines deseados mediante el uso de resistencias pull-up externos.
La funcin de I/O open-drain no es soportado en los pines que tienen funcionalidad
multiplexado analgica en el pin.
El mximo voltaje open-drain permitido es la misma que la especificacin mxima VIH. La
salida open-drain caracterstica es compatible tanto pin del puerto y las configuraciones de
perifricos.
Programando en el DsPIC33F:
Ejemplo1:
Simulando en Proteus:
Ejemplo2: