Proceedings International Conference On Advances In Engineering And Technology

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A Low Power and High Throughput Re-Configurable BIP for Multipurpose Applications
1
1
2

. R.Akshara ,2..Murthy Raju

. M.tech, akshara.rentapalli@gmail.com, VLSID, Shri Vishnu Engineering College for Women, Bhimavaram

Associate Proff, venkateswara.106@gmail.com, E.C.E, Shri Vishnu Engineering College for Women, Bhimavaram

ABSTRACT: The main objective of this project is

recognition, tracking, motion detection and machine

to design a reconfigurable binary image processor to

intelligence

perform real-time binary image processing. The

understanding

processor

consists of a reconfigurable binary

computer vision [10], [11], and identification and

processing module, input and output image control

authentication systems [12][15]. Binary image

units, and peripheral circuits. The reconfigurable

processing has been commonly implemented using

binary processing module has a mixed-grained

processors such as CPU or DSP. However, it is

architecture with the characteristics of high efficiency

inefficient and difficult to use such processors for

and performance. The dynamic reconfiguration

binary image processing [10], [11], [16]. High-speed

approach was used to increase the processor

implementation

performance.

morphology

operations can be efficiently realized by using chips

operations and complicated algorithms can easily be

specialized for binary image processing. Therefore,

implemented on it because of its simple structure.

binary image processing chips have attracted much

The processor, featured by high speed, simple

attention

structure, and wide application range, is suitable for

Application-specific chips and hardware have been

binary image processing, such as object recognition,

reportedfor various applications. A chip with a 500-

object tracking and motion detection, computer

dpi cellular-logic processing array was implemented

vision, identification, and authentication. Further this

to enhance and verify fingerprint images [17]. A

technique is enhanced to design a reconfigurable low

pointing device using a specialized algorithm was

power processor for image processing applications.

presented

In-order to implement this processor, line memories

Reconfigurable binary image processing chips have

are selected for less power consumption. Line

been designed to generalize the binary image

memories power is reduced by using clock gating

applications of a chip. Chips were presented to

technique.

perform basic binary morphological operations, such

KEYWORDS: mixed-grained architecture, binary

as dilation, erosion, opening, and closing [16], [20],

processing

[21]. Programmable analog vision processors based

Basic

module,

mathematical

Reconfigurablility,

Image

processing, object recognition, object tracking.

[1][6],

in

for

[7],

of

the

image

[8],

video

binary

field

motion

of

analysis

and

processing

[9],

image

image

detection

processing

processing.

in

[18]

on the cellular neural or nonlinear network universal

machine architecture were proposed for a wide range

INTRODUCTION: BINARY IMAGE processing is

extremely useful in various areas, such as object

ISBN NO: 978 - 1503304048

of applications such as motion analysis and texture

classification

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Proceedings International Conference On Advances In Engineering And Technology

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Literature Survey: [1]. A. J. Lipton, H. Fujiyoshi,

Drawbacks:

Only small scale images can be

and R. S. Patil, Moving target classification and

compresses and cant be done for videos.

tracking from real-time video, in Proc. Workshop

[4]. R. Dominguez-Castro, S. Espejo, A. Rodriguez-

Appl. Comput. Vision, 1998, pp. 814.

Vazquez et al., A 0.8-m CMOS 2-D programmable

This paper describes an end-to-end method for

mixed-signal focal-plane array processor with on-

extracting moving targets from a real-time video

chip binary imaging and instructions storage, IEEE

stream, classifying them into predefined categories

J. Solid-State Circuits, vol. 32, no. 7, pp. 10131026,

according to image-based properties, and then

Jul. 1997.

robustly tracking them. Moving targets are detected

This project designs tiny a processor, which can be

using the pixel wise difference between consecutive

implemented in Cameras. This extra chip has the

image frames. A classification metric is applied these

capability to increase image quality and can remove

targets with a temporal consistency constraint to

blurring effects also. Less area occupancy and low

classify them into three categories: human, vehicle or

latency are the main advantages by using this project.

background clutter. Drawbacks: Even though,

Drawbacks: It cant be implemented for shuttering

Background subtraction takes place properly, this

images. Only single snap shot images can be

method is used for only object extraction for single

processed through this chip.

image.
This project presents a binary image processor that
[2]. M. R. Lyu, J. Song, and M. Cai, A
comprehensive method for multilingual video text
detection, localization, and extraction, IEEE Trans.
Circuit Syst. Video Technol., vol. 15, no. 2, pp. 243
255, Feb. 2005.

consists of a reconfigurable binary processing

module, including reconfigurable binary compute
units and output control logic, input and output image
control

units,

and

peripheral

circuits.

The

reconfigurable binary compute units are of a mixed

This project deals in security applications. Any

grained architecture, which has the characteristics of

texture or image can be embedded in to any cover

high flexibility, efficiency, and performance. The

image. Hiding is the main criteria designed in this

performance of the processor is enhanced by using

project. Drawbacks: This project is used for only

the dynamic reconfiguration approach. The processor

images. But video security cant be provided by using

is implemented to perform real time binary image

this project.

processing. It is found that the processor can process

pixel-level images and extract image features, such as

[3]. W. Chan, J. Chang, T. Chen et al., Efficient

boundary and motion images. Basic mathematical

content analysis engine for visual surveillance

morphology operations and complicated algorithms

network, IEEE Trans. Circuits Syst. Video Technol.,

can easily be implemented on it. The processor has

vol. 19, no. 5, pp. 693703, May 2009.

the merit of high speed, simple structure, and wide

The

algorithm

correlation

incorporates

predictor

which

a
can

temporal

data

exhibit

application range.

the

correlation between data and reduce computation

based on this correlation.

ISBN NO: 978 - 1503304048

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Proceedings International Conference On Advances In Engineering And Technology

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binary compute unit outputs according to the given

parameters and converts the series data of 1-b binary
images into parallel data.

Fig1. Architecture of the binary image processor.

Fig2.
The proposed processor is designed for applications
in image or video processing, computer vision,
machine

intelligence,

and

identification

and

authentication systems. Such systems should have a

high flexibility and high performance processor for
wide applications; therefore, the processor design is
focused on high flexibility and speed. Some of the
conventional works are designed for specific
applications and some have large areas and high
power consumption. Then, a reconfigurable binary
processing module with high speed and simple
structure is implemented for wide use and consuming
fewer hardware resources. The architecture of the

Diagram

of

the

reconfigurable

binary

processing module
The second part consists of several binary compute
units that perform binary logic and binary image
operations at a high speed. The binary image
algorithms are realized by the operations in the
individual binary compute units and the connection
pattern of these units. The units can execute binary
image operations in a pipelined or parallel manner.
The operation executed in a binary compute unit is
decided by configurable registers, including logic
operation parameters, image resolution parameters;
mask sizes, input and output selection parameters,
and auxiliary parameters.

proposed processor is shown in Fig. 1. The core of

the processor is a reconfigurable binary processing
module consisting of binary compute units and output
control logic. The processor also has two bus
interfaces, the input and output control logic units,
the process control unit, and a configuration register
group.
RECONFIGURABLE BINARY PROCESSING
MODULE:
The diagram of the reconfigurable binary processing
module (RBPM) is given in Fig. 2. It can be divided
into two main parts. The first part is the output
control logic, which selects the output from all the

ISBN NO: 978 - 1503304048

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Proceedings International Conference On Advances In Engineering And Technology

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The binary compute element comprises two input

content hierarchy by integrating audio, video, and

control multiplexers, n binary logic elements, a

text information, in Proc. IEEE Int. Conf. Acoust.,

binary reduction element, and a binary median filter.

Speech, Signal Process., vol. 6, 1999, pp. 30253028.

The input control multiplexer selects input data for

[2] W. Qi, L. Gu, H. Jiang, X.-R. Chen, and H.-J.

the binary logic element from the line memories, the

Zhang, Integrating visual, audio and text analysis for

SDRAM, and the parameters in the register group.

news video, in Proc. Int. Conf. Image Process., vol.

When a video image is processed, line memories are

3, 2000, pp. 520523.

needed to buffer image signals before they are input

[3] M. R. Lyu, E. Yau, and K. S. Sze, A

to binary logic elements. Line memory structure is

multilingual,

changed to the following structure.

system, in Proc. Joint Conf. Digital Libraries,

Line memory address generator circuit:

Portland,OR, Jul. 2002, pp. 145153.

Existing:

[4] R. Lienhart, Automatic text recognition for video

multimodal

digital

video

library

indexing, in Proc. ACM Multimedia, Boston, MA,

Nov. 1996, pp. 1120.
[5] S. Sato and T. Kanade, NAME-IT: Association
of face and name in video, in Proc. IEEE Conf.
Comput. Vis. Pattern Recognit., San Juan, Puerto
Rico, Jun. 1997, pp. 368373.
[6] A. Jian and S. Bhattacharjee, Text segmentation

Proposed:

using

gabor

filters

for

automatic

document

processing, Machine Vis. Applicat., vol. 5, pp. 169

184, 1992.
[7] V. Wu, R. Manmatha, and E. M. Riseman,
Textfinder: An automatic system to detect and
recognize text in images, IEEE Trans. Pattern Anal.
Mach. Intell., vol. 21, no. 11, pp. 12241229, Nov.
1999.
[8] H. Li, D. Doermann, and O. Kia, Automatic text
detection and tracking in digital video, IEEE Trans.
Image Process., vol. 9, no. 1, pp. 147156, Jan. 2000.
In proposed ring counter, power can be halved by

[9] M. R. Lyu, J. Song, and M. Cai, A

inserting SR control circuitry.

comprehensive method for multilingual video text

detection, localization, and extraction, IEEE Trans.
Circuit Syst. Video Technol., vol. 15, no. 2, pp. 243

REFERENCES:

255, Feb. 2005.

[1] Q. Huang, Z. Liu, A. Rosenberg, D. Gibbon, and

[10] W. Miao, Q. Lin, W. Zhang et al., A

B. Shahraray, Automated generation of news

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applications, IEEE J. Solid-State Circuits, vol. 43,

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