,,

MOTOROLA

Order as MC68HC25/D

SEMICONDUCTOR
TECHNICAL DATA

MC68HC25

Advanced Information
1/0 EXPANDER (PORT REPLACEMENT UNIT)
The MC68HC25 is a peripheral device which permits simple interfacing of a range
of MCUS to external devices without potential loss of port 1/0. Intended for use with
the 146805E2, 6801,6801 U4, 6803, 6803U4, and 68HCI 1 processors manufactured
by Motorola, the MC68HC25 provides address/data demultiplexing and port
operation which replicates that of the displaced ports.
Use of the MC68HC25 provides a cost effective, monolithic solution to the situation
of an MCU/MPU operating in expanded mode. This is particularly relevant where
board space is at a premium.
0,.

(,,:,, , ,...

PIN ASSIGNMENT
52 ~n Quad Pack

...-;;.J
\
~.~>
<
~,>::
~.
t,~$::,,.
,,?
..:$:

Features

...:*$,:,,,,,.>
~:
g .;4
.
,~.!.~~!!.?,.>}:.?i
. Choice of Memory Devices : 16K, 32K, 64K, 256K
.$.+:..
*,;*:>?.,
,,. \~t\\
2 Chip Select
signals for use with External Devices
.,.
,,,,,t!Y.\.
,
2 Handshake Control Lines (Port 3)$$@~#qQ output
e 8 Bit Bi-Directional Pon with
?>: ?:*.
forsignalling MCU
,,. ~tf~
,~~k.
it,>
,,,,*W?!.$
e 8 Bit Bi-Directional Port (Port 4)
-,1{~,:j~s.

Choice

of Memory Map Size : 8K, 64K

o Shifi Mode to permit FuII Utilisation of On-Board and Extern%$Memory (No

$, ..,,:~
Holes in Map)
\\>y
$.!.
.<.+:,,
,
I.\, *,j:
. ~Lor CMOS Input Capability
.:lj.
~
~i,,!.
,$.,
,,.*,
,,
,.?.%,
. Full Demultiplexing of Address and Data
,,~,,
, ~,$~~
o System Reset Controlled through MC68NA$lJdws
,,&~!$,\:.
*~,$?
MCU without Affecting Port 1/0 Status ,&,%$~..
.,

Low power Consumption

o 02.1

Mhz Operation

o compatible

Full Reset or Resetting of

6803U4,

P32
P33
P34
P35

HCMOS ~~~k~~~~gy
3$.,:,:*F
\bf:<i?
,.Q
,
1,:~,,,{?

with 6801, 6801 ~Yj~W~

P31

P36
P37

146805E2,

P43

14

P44
P45
P46
kJ P47

21

LTD., 1990

33

26

PIN NAME

DESCRIPTIGb

1+

A4-A7

ADDHESS

LOW OUT

5.12

A8.A15

ADORESS

HIGH IN

13-20

P3Q.P31

PORT .j

21

PDRT =3 OUTPUT STROE6

22

Resel ,1

RESET 0u7

23

Reset

HESET lh

24.25

AD7-AD6

ADDRESS

16

VS*

GROUND

27.32

A05.ADQ

ADDRESS

33

PORT =3 10 lNTERRUP7

34

R~

READ m

35

CLOCK IN

36.43

P47.P40

PORT =4

44

CHIP SELECT I

45

CHIP SELECT 2

46

A3

AOORESS

47

PORT =3 INPUT STROBE

48-51

AO-A3

AODRESS

52

Vdd

SUPPLY

+.

MOTOROLA

Rw

68HCI 1 Devices

PIN *

@ MOTOROU

1!
E

20

DA7A I O

DATA 10

STROBE

LOW 0U7

EADI 0049R2

SYSTEM CONFIGURATION
Device Organisation
The block diagram of Figure 1 shows the main functional elements of the device.

. ..

~~~,

~.ils,,~:tt:l,,
~,,

Hiah-order address bits (ADDRE=~%~)

are provided by the MPU/MCU on the non-multi~lexed
bu;. The bus is also connected ~~$$lftothe
memory devices within the users system.
Low-order address bits and,%~:~,#a transferred in either direction between the MC68HC25 and
the processor are multi pleA&d$n a single 8-bit bus (ADDRESS LOW lN/DATA). The low-order
addresses are latched a#fk~tiegative
edge of AS supplied by the MPU/MCU. The address inputs
are fed to the decodqs,m~
determines
the output low-order address (ADDRESS LOW OUT) and

activates the releva~$$~~lp select (CSI, CS2). Decoding is controlled by the user-programmable
mode select re~8]er (MODE SELECT) as described below,
.!,:,~,~,t.
,.,
?~t,~~i..,
.,7
*..
J@!
:\>T+
>,,s
The direc~~~q+d$%alid data on the multiplexed address/data bus is determined by the R~ input.
Demulti.~l@~~~g of address and data is carried out directly using the Address Strobe (AS) signal.
~1 !fln~bnded for enabling read-only devices and is only qualified when R~is high.
C~~!@dalified
independently of R~ and therefore may be used to enable PROM, RAM, and
$~~f~%eral devices. Both CSI and CS2 are qualified by E-clock and therefore maybe used with
f$REbMS which do not have a separate output enable line, eg. MCM68766.
V)(
Ports 3 and 4 operate similarly to those of the MCU/MPU to which the MC68HC25 is connected.
Poti 3 offers
handshaking facilities identical to those faund on the 6801/03 and 6801 U4/03U4
through the 0S3, lS3and~Qsignals.
RESET IN is intended as the master reset, initializing the system to a known state. The MPU/MCU
reset line should be connected to the RESET OUT output which becomes active twa E-cycles afier
the reset condition is detected. The time between the two signals is used to input the mode select
information from the external memory.

MOTOROLA
2

MC68HC25

Since the RESET OUT output is designed with a resistive pull-up, it maybe wire-ORed with
another reset signal. This allows an MPU/MCU reset without affecting the condition of the
MC68HC25 thus maintaining
the status of the ports.

FUNCTIONAL
The following

PIN DESCRIPTION

paragraphs

Note: all timings

describe

are referred

the function

pins.

to the E-clock provided

by the controlling

&
?~
~
..:?:>>,,
x-~$.m
..t:r+>l:,~?

Vdd AND VSS

Power is supplied
ground.

*,\
*X,l,
$J,$<,.
,,.
,+ts.,
~
,$:.
!i.,,,1
.P::*S, >,,$
>.,

MCU/MPU.

to the 68HC25 using these two pins. Vdd is the power

,.,i,
,+,,,
~,.
,,,.i~J+\
input and Vss is
\ 3*$Fp
~.,,,;,.
/!i
*, \\,\ .,%
,,,
,<,$a,,$~
. ~,$..}.
,it
>;*Y$,!;T,i~
-\.)*#.
,-,..,. ~:l?
t.. ~

~t:} ~.
.x!
.>,\,:\, ~i

RESET IN

!>\&?+;$,.
This active low high impedance input is used to initialise the MC68HC25 to a kn$g~$i~ate.
Minimum
low time is 1 E-clock cycle. During the Iowtime
of this input, Addre~J@~~~ 1/0 pins
and Address Low Out pins are forced to high impedance; Ports 3 & 4 data ~i~~~~h registers
are initialised such that the ports are in the input mode; Port 3 handshake r#~~&?er is initialised;
Chip Select (CS) 1 & 2 outputs are disabled and RESET OUT is held acti~~
Ioti.
;+::,t,~i.ji>..~:
.,..
~~,,..,>,.<,
RESET IN is sampled on the rising edge of E-clock. the input mu~~ ~~~dble prior to E rising
edge. After the rising edge of E, the required mode selection inf~~fi%ffon is captured from the
external memory prior to the rising edge of RESET OUT. SeqjMob
Select Register.
,,,1$.
.\,,.\
*$$
,
Note: When RESET IN is low, external PROMS maybe p~~g$rnrned
since Address/Data
and
Address Low Out busses are held at high impedance.
*h,F.*>>
.?$$
.,q~$~<
.J*:I

RESET OUT

<.
,\*:;
?
$t
.

*,V

This output is intended for connection to th#O-Wtil?olling MCU and any other peripherals.
RESET OUT follows RESET IN in phase ~}t~~~ti~nge of state occurring on the rising edge of Eclock. Immediately
after RESET IN go~$:&t~,~YAddress
Low Out is configured to $BF and CSI is
held active low allowing the Mode ~~~f~formation
to be retrieved. See Mode Select
Register. Two cycles after RESET tw,,~~~been recognised as returning high, RESET OUT
.J].\\\.g~*
follows.
ttt,.$
.$l
~.,+~i:,:.
\.,~..
,,
Note: RESET OUT contain$~~~ave
pulldown device and a resistive pullup device with a
typical impedance of 40k~,,rn~$
Thus a wire-or configuration
~:...,,. in a CMOS push-pull configuration.
is possible externally.~~?~ltilng
the controlling
MCU to be reset without affecting the registers
of the MC68HC25. ,~hIs %@llity permits continuity of the port outputs.
.:~>:,
,~t
Y>
.~..~
!;:3:,)>\\,,

CLOCK (E~:j;~;~~<
E CLOCK ~,@Ri~h impedance input which provides timing reference information
for the
MC68~~~5~fw general, when E is low an internal process is taking place and when high, data is
bei~:~~~p~sed.
\,;~3:..>,!..
~J.>t
,,, :&ii,
.,,!:~\~.,:?~,

AtitiRESS

STROBE

ADDRESS STROBE(AS) demultiplexes

the Address/Data
bus. The falling edge of AS causes the
low order address AO-A7 to be latched within the MC68HC25. Note that AS has an internal
pullup of 40kohm nominal active during RESET OUT low.

MC68HC25

MOTOROLA
3

READ/WRITE

(R/W)

RW is a high impedance input and is used to control the direction of transfers on the
multiplexed
Address/Data
bus. Data is transferred
on the high half cycle of E-clock. When the
68HC25 is selected and R~ is high (read), data output buffers are enabled. A low level on Rm
enables data to be written to a selected register.

CHIP SELECT 1 (CSI)

CSI is a push-pull output which is active low when a specific memory

zone is being addressed.

,*!.
,,<,
* :$.,l,+,
The relevant zone is defined bv the Mode Select Register. While RESET IN is low, CSI is
,,,,.,
..,.,+,
;,.,..:~
,.+.,>
.,it.
~
disabled with only a 40kohm nominal pullup visibIe=This
pullup is disconnected
while the
. ..\~.
,)$..l$
-,,i.l~.
$
.,
,)~
:;.,,
output buffer is enabled. The buffer is capable of driving 90pF and 1 TTL load. In normal
.
+i$$,>
&;>*4~
,,.:* .:<.,
operation, CSI is qualified only on E-clock high and RW high.
,?,,.7,:+*,..,
.,.>
.. %&!,.
*

.:,

a
..J ,, .,...:

ADDRESS/DATA

4-

j ~
~s~$..
~i~:,<ihgl
~t,pr,
,::*.J>
~),..*
.$.:.
,,.

1/0

Address and data information

must be supplied to the 68HC25 durin~~e
I&ti and high half
cycles of the E-clock respectively.
Low order address bits (AO-A7) m#~/&&stable
prior to the
falling edge of AS at which time they are latched. This address in~~o~fiction
with the high
order address (A8-A15) is used to decode the internal register$$&~*&V@*sert CS1 or CS2 as
appropriate.
Valid write data must be presented to the MC6~~~
with RW active low during
the high half of the E-clock. Where R~ is asserted high, r@&~t4datawill be output during the
high half cycle of E. (See Bus ~ming Characteristics). ~~~ftbuffers
are capable of driving
90pF and 1 ~L load. Pullup devices of 40kohm nomi~#liq,~@ active only during RESET IN,

:...~,
.,.. a,

ADDRESS LOW OUT

Address Low Out provides the demultiplex~~~

order address bits (AO-A7). Note that ALO
bus is transparent
during AS high and f~l~#~Address/Data
bus in order to provide maximum
access time to the PROMS. Push-pull b~~er$are
implemented,
capable of driving 90pF and 1
TTL load. While RESET IN is low, a,h@~%#pedance
is presented.
.:$f>~;.?i
:~,.)e,
..!:
*~~
,,,:,.
..?t..b,~
~.,,$.
.
[.>,l

ADDRESS HIGH IN

?!*:,
,<;?
.,,:)::<
,,,}
,,,.,\
\:. $?

Address High In bits (A8-&?f~wk

decoded internally. In the case of 64K map operation, all bits
are valid. For 8K mode&~@g~~per three address lines are dent-cared
within the device.
However, it is recom~~~~ed
that the unused pins are grounded on the application
board.
,.~. i~\>,,t..

Port 3 is an ~-&~&directional
l/O port (P30-P37). Each output buffer is capable of driving 30pF
and 1 ~~$,~&&: Port operation is controlled through data and data direction registers. The data
registarfo~.~ort
3 is normally resident at address $0006, except in displace mode. The data
dir~~~~#&gister
is decoded at $0002 in CMOS mode and $0004 in ~L mode, again with the
e&c@#~bn of displace mode. (See Mode Select Register). Both data and data direction registers
d~$~sadable and writable.
~!}~;.
!,..
A zero written to the specific data direction bit forces the corresponding
output buffer to go to
the high impedance input mode. A logic one written to the DDR bit configures the
corresponding
port line to the output mode. Transitions of data and data direction register bits
are synchronised
to occur on the rising edge of AS afier a Port 3 register access.

MOTOROLA
4

MC68HC25

A zero written to the data register drives the pulldown device of the output buffer when the
corresponding DDR bit is preset to the output mode. Note that a write to the data register is
retained even where the DDR is preset to the input mode which allows clean simultaneous
switching of outputs upon configuring the port lines as outputs. A read of the data register
where the DDR is configured as output returns the value currently stored in the data register,
irrespective of the actual level on the pin. However in the input mode, only the actual level on
the pin is returned. The level on the pin is latched on the rising edge of E and maintained until
the falling edge irrespective of changes to the input.
During RESET IN, the data direction and data registers are set to $00, hence the ports are preset
to the input mode.

gX..
$J,$<,.
,,.,+ts.,
~
,$:.
!i.,
,,1
I:a..
{,~~$
J,)
,,. !j.~~,.
,/ ~
.:\. . , J\~

a
,*
.,:{l,,

,.!,
.
~<
,,.*},
,~t*
,,~~,v
*..
,,i,::.,,{,,
,,~i:$

PORT 3 HANDSHAKE SIGNALS

Ns,...

:$

!\ .:~+>
%
Port 3 handshaking is analogous to that found on the M6801 family of MCUS. The three a~~~~
signals, 0S3, 1S3 and IRQ, are predefine
by the Handshake Control and Status registe~~~@Y
,
,..,
located at address $OF.
,. .~!,!:.}.+

.,*,$

When set, IRQ enabled whenever

Cleared at reset.

ISF set..~hen ~lear, IRQ is inhibited.

~..?.\y*
,\ $.),
~:i: ...
ST
... .:i} :.:~1
When set, bits ISS, 0S1 and 0S0 a~~~.~~?stated below. when clear, these
bits read as zero and their functions %Kedisabled. Cleared at reset.
*$>.,

Bit 6

ISE

Bit 5

MOD

Bit 4

0SS

When clear, 0S3 will be gen#;~Jed by a read of Port 3 data register. When
set, generated by a writew~~~reti at reset.

Bit 3

LEN

When
clear.
MOD
input

Bit 2

ISS

When cl,@F~&~ 3 data is captured on the falling edge of 1S3. When set, data
is cap~,U~~<t@nthe rising edge. When MOD is clear, ISS is cleared and a read
of th~~~~tion
returns logical O. No spurious strobes are generated while
waplp&ating ISS via software.

,,A\.

,,.
~,..

,~,,,

set, input data:.,~~,:~~~~ked

by negative edge on 1S3, provided MOD is
If MOD is sq,$~~~~~~ latching edge depends on 1SS. Irrespective of
bit, the iata~~%wansparent after a Port 3 read, When clear, Port 3 data
is transQ,~%g3~?
independent of MOD status. Cleared at reset.
../ . ...

0S1 and 0S0 are preset to zero when MOD is clear. A write instruction which sets MOD cannot
simultaneously affect 1SS, 0S1 and 0S0. These bits may be manipulated only on subsequent
instructions. However, resetting the MOD bit has immediate effect on 1SS, 0S1 and 0S0,
putting them to their preset states.

MC68HC25

MOTOROLA
5

PORT 3 OUTPUT STROBE 0S3

0S3 may be used to strobe outputs to an external device or provide acknowledgement
depending on the configuration
of Port 3. In pulse mode, the active pulse low time is one Eclock cycle. Assertion of 0S3 is synchronised
to the rising edge of E on the machine cycle after
the access of Port 3 and negated on the next rising edge of E. In handshake mode, the pulse
width is determined
by successive reads of the Port 3 data register. 0S3 is asserted on the
rising edge of E following
the Port 3 data register access and remains active until the next
rising edge of E following
a Port 3 data register access. The Handshake Control and Status
Register (HCS) determines whether a read or write is the active access.
,*!.

*{,3,
es:<.\.*:<2~,
~
,.+.,> *rit.

. ..\~.
,)$..l$
-,,i.l~.
$
high or constant low modes, 0S3 changes state synchronised
to the
,>,:;.,,~,,,)<:~
follows the modifying
access to HCS. See Port 3 Handshake Signals. ,t,KtiYk$IW4*
,?,,.7,:+*,..,
.,.>
.. %&!,.
*
of driving 30pF and 1 TTL load.

In the case of constant

rising edge of E which
0S3 is capable

~?~.$>

:\ *?:l$@
~,
),.)\,.
,q<.
.,1?
.;>

DATA INPUT STROBE 1S3

1S3 may be used as an input strobe or data acknowledgement

from an extern~J:@~~#e
depending on Port 3 configuration.
See Port 3 Handshake Signals. An activ~~~J@dge will set
ISF flag in HCS which may be used to generate an IRQ signal. 1S3 may al~.q~wsed
to latch
data into Port 3 where LEN in HCS is set, 1S3 is an asynchronous
input.,:{herq(ore the timings
specified in Bus Tming Characteristics must be adhered to. The 1S3 ~~$h~,contains an active
pullup device of 40kohm nominal which is active during normal o,~%x~~~~n.

.,,,.
,::
i-, ~:y>
,,:,,.
,~L~\,

INTERRUPT REQUEST IRQ

IRQ is a push-pull output with an active pulldown devic~qya

driven resistive pullup device.
Pullup impedance is nominally 40kohm. As a result, q{~~rw~ctive low interrupt sources can be
wire ored to IRQ with the resistive pullup serving d~j~~rces.
Secondly, if the MC68HC25 is the
only device present, the buffer avoids DC current dra~m. the output of IRQ is dependent on
CMOS~L
mode, See Mode Select Register. 1$TT&mode is selected, then IRQ output is a
NAND function of ISF and ISE. See Port 3 Hp#~hake
Signals. However, if CMOS mode is
selected, IRQ generates a 1 E-clock cycle~~[~$, as a result of the falling edge of the NAND
function of ISF and ISE. This facilitates oq~~atibility
with the latched negative edge sensitive
interrupt of 146805E2,

PORT 4

..

Port 4 performs in the sa~~~%,~~as Port 3 with the exception of handshaking

facilities. Also, in
TTL mode an active PUIIWQd~40kohm nominal is connected on all pins. The pullups are
disabled in CMOS m@@~~&~ept during RESET OUT low when pullups are enabled in both
modes. Port 4 data,. re&lsJdr is decoded at address $07,
in displace mode. See Mode
,, exceDt
,.
Select Register. ~~$4-data
direction register is decoded at $03 for CMOS mode and $05 for TTL
mode, exceptl,n~~2@?ace mode,
~$i
, }(J..:,
,~:t~
.,.,, ,~,~..
t$~.:J4+%
3**,~.,

OPE~+%hAL
Thq~&@C25

ENVIRONMENTS
allows

the user to select specific modes of operation depending

on the desired
en*g&%m ent.
~:..?,:,>
:.J~:\\
.. ~i
.,1,.,
.:ty,.,
:~+.
:
lw.the 6801/03 environment,
Ports 3 and 4are replaced by the MC68HC25
and an address range of
64K bytes of memory

is available.

Port3

handshaking

is implemented

on the 68 HC25via

Rand

1S3 in the same way as in the MC6801.

In the 146805E2 environment,
memory may be addressed.
In the 68HCII
handshaking

MOTOROLA

ports are provided

whilst up to 8K bytes of external

environment
ports B and C are replaced, although it should be noted that
is not fully replicated.
Up to 64K bytes of memory maybe addressed.

Consult the relevant Motorola

two additional

data sheets in each case.

MC68HC25

MODE SELECT REGISTER

The mode select register must be configured by the user to determine
decoding. Six types of information are required:
MAP SIZE
SHIFT

the required memoy

: either 8K or 64K bytes

SIZE 1

: re-locate external memory addressing to allow use of internal MCU ROM

: 16K, 32K or 64K bit external PROM 1

SIZE 2

: 16K, 32K, 64K or 256K bit external PROM 2

CMOS~L

: CMOS or ~L

input capability

,..
,...
. .~?:$.>
,
The register vaiue is programmed

by the user at external memory address $XFBF. W= I for 8K

memory map, X=F for 64K memory map.) The information

the rising edge of the RESET IN (~)

is transferred

to the MC68HC25 during

signal prior to the rising edge of the RESET OUT. During this

period, the MPU/MCU is in reset and hence the Address High bus output is in the default condi~~,
of $FF. During the cycle following the rising edge of RSI, the Address LOW Out lines are forc~~j$

,@ ~~~]~~)
,+%.>+t:
$:~,,
,,.,$:.... .4,.$$~
$~<$t~>~
~~w*

$BF. Simultaneously Chip Select 1 (CSI ) is asserted low, ensuring that PROM 1 is activat#~F~$i
., ,-,,~
.,,,?,
~ >>
$XFBF. During the E high-time of this cycle, the contents of the PROM at this address ar~. t,@
...!.. ~~i,t
transferred and latched in an internal register inaccessible to the user. Note that an EPw~device
,,+
?,..! .,l\..
\,y ~
must be connected to CS1 for correct operation. (See Figure 12.)
\ki.*,*.l~-j$i
$;,,,

M9
PROM 2
SIZE
SELECT

M6

M5

PROM 2
SIZE
SELECT

PROM 1
SIZE
SELECT

M3

M4
PROM 1
SIZE
SELECT

,,

DISPLACE (MO)

-,, ~tc+$
:$2

PROM 1,, :~:;$MOS

DEC-,,
OR TTL

Ml

MO

MEMORY
MAP

PORT
DECODE
DISPLACE

.%/;

If MO is read as 1, then both Port 3 and Port 4 data ,~~$~ata direction registers are translated by
$0100. This permits Poti 4 to act as a fully progra~$~le
1/0 poti, even when the 6801 U4 is
configured in mode 1*. The displace mode ai~~~~~re%nts conflict of the on-board RAM of the
MC68HCI 1 with both Poti 3 and Port 4 by ~~~~~ddng the relevant addresses outwith the RAM
.i..t,,
,i,; ~~,!~.
J<:;~,i::...
~{{,,
i.i\).&,
.\,\,\
:$, ~$$
* See MC6801 U4 data sheet
area.

~$%ts
-?
.,~+;,j~y$

MEMORY MAP SIZE (M 1)

The map size information
Ml transferred

~~~~~~$es the total memoy

during re~~?~the

map available in the system. If the value of

MC68HC25 is high, then a MK memo~

If Ml is low, then an,,~~m%~!s used. In the latter case, the uppermost

HIGH bus are igno&&~J@in
8K memory m~j%greset.
,,...
t~$+,
..*,,
,,:>;,.:
,
In the caiw~~~~memo~

the MC68HC25. This feature effectively

map size is recognised.

3 inputs of the ADDRESS

remaps CHI P SELECT 2 to the

map mode, a zero level must be hardwired on the corresponding

pins on

the MC&H&25,
..+,,
.. .:,..i\
\i,!$ namely the uppermost 3 addresses of the ADDRESS HIGH input bus address Al 5,
Al~~@,~?3.
These are ignored (dont cared) during all the internal decoding as well as for the
@#J~~ELECT 1 and 2 outputs.
$,.
*~*.*
J$\
.,,

CtiOS OR ~L

MODE (M2)

This bit allows the MC68HC25 to configure Port 4 address decoding, Port 4 pull up device control,
as well as IRQ edge or level output modes, If M2 is low, ~L

mode is active. For M2 high, CMOS

mode is used.

PROM 1 DECODE ZONE SHl~

{M3)

When set, this bit translates (shifts) the decode zone of CS1 by $2000. See Figure 4. The translation
facilitates the use of the on-board ROM of the MCU.

MC68HC25

MOTOROW
7

PROM 1 SIZE SELECT (M4, M5)

These two bits select the decode zone for Chi~ Select 1. The available
of 16K, 32K or64K bit PROMS. See Figures3 and 4.
M4

M5

11
11

M3

10

16K PROM DECODE : X800-XFFF

16K PROM DECODE : D800-DFFF
+FFFO-FFFF

(*) :

32K PROM DECODE : XOOO-XFFF

32K PROM DECODE : DOOO-DFFF
+FFFO-FFFF

MOTOROLA
8

(*)

(*) 1

allow full use

CHIP SELECT 1 DECODE RANGE

(*) ;

01
01

combinations

64K PROM DECODE : EOOO-FFFF

64K PROM DECODE : COOO-DFFF
+FFFO-FFFF

MC68HC25

MCU/MPU

,.y
MC146818

MC68HC25

MOTOROLA
o

50000

$0800

FIGURE 3
MC68HC25 PROM 1 DECODE FOR
8K MEMORY MAP OPERATION

$1000

$1800

$1 FFF

$Cooo

5DOO0

FIGURE 4
5D800

MC68HC25 PROM 1 DECODE FOR

64K MEMORY MAP OPERATION

$EOOO

$FOOO

$F800
$FFFO
$FFFF

.,?,:
?
l$j:r,.,.,
..)j

32K PROM WITHOUT

SHln

WITH SHIFT
64K PROM WITHOUT

SHl~

WITH SHl~

MOTOROLA

10

MC68HC25

ELECTRICAL SPECIFICATIONS
This section
MC68HC25.

MAXIMUM

contains

the electrical

RATINGS

(Vdd=5.OV

specification

(+/-1 OYO),

and related

VSS=OV,

timing

Ta=-40C

Rating

information

to +85C

unless

Vdd

Input voltage

Vin

otherwise

stated)

Value

Symbol

Supply voltage

for the

-0.5

Unit

to 0.7

VSS-O.5 to Vdd+O.5

*+
.=[,>,

..:$~,
,:i?:~)
.:
Iik

Current drain per pin

Operating temperature
Storage temperature

range
range

10

pfi:

Ta

-40 to +85

?
,:1~
~, *&,>!
..,>
r?! >>
~

Tstg

-65 to + 125

.2

,,~T$>k?$
,,.:,~\\,
,,,,$
,,,. C
.. ..
.>~:$$+~
..<
>~.
:~\~\+

*S:, *2.$!

THERMAL CHARACTERISTICS

TJ = TA + (PD. OJA)

(1)

Where:
*..!,.

*,,

,$.!

S$$.,)s:~kty:...

T~
6~*
P~
P,~~
P,,o

=
=
=
=
=

-~
. ,,.,.
.,J*
::.,
,:.,
,~.+,\
..$&\.,,,{\
~.~:..:,
:.,
Junction t@ Ambient
,:.;!. .,~;!~

Ambient Temperature
C
Package Thermal Resistance,
P,~~ + P,,~
Icc x Vcc, Watts - Chip lnterna[:+@&~er
Power Dissipation
on lnput,a~~~:Qu~put

>.>
$,. >

Pins -

Cm

User Determined

,:.~

Where K is a cons~f~$ pe~;aining to the particular part. K can be determined

from equation {3)
by measuring
P~:~$*@fiilibrium)
from a known TA. Using this value of K the values of P~ and T~
can be obtain@@Q@jsolving equations
(1) and (2) iteratively for any value of TA.
\:,. ~\%\ .!
::4,,:
%$.
.$:.\
,>p.,,:,\:,,.
*x:$i.,
*$.::+-..,!:<
...,% ~,,?,
<..,
*,...
..:J
\,,,~:.
~.:.::*/,,
.i{t,
~:4,\,x4
:<.,<.t$l,,

MC68HC25

MOTOROLA
11

DC ELECTRIC CHARACTERISTICS
Wdd=5.OV (+/-1 O%),

VSS=OV, Ta=40C

to +85C unless othewise

stated)

CHARACTERISTICS

Symbol

Output low voltage @ Iol = 2.OmA

Vol

Output high voltage (for IRQ and RESET OUT) Iload = 0.1mA

Vohr

Output high voltage @ Iol = 0.36mA

Voh

Input low voltage (TTL MODE)+ RESET

(CMOS MODE)

Vil

Input high voltage (~L MODE)

(except RESET IN (CMOS MODE))

Vih

Input high voltage RESET IN

Vihr

Max

Unit

0.5

Vdd4.8

Input current CS1, CS2, PORT 4

ADDRESS LOW/DATA @ RESET IN ]OW

:?:;>
l+:*),
Qi$;: $9 v
~~:.,
..S.
(}~$:~)~$ti
.,,,...
.,*,.
..v+>
2.44
Vdd-2.&3 ?*W&d
v

.\~
& ~~}?
.6:.$,
,&*i,\,

.,k\.
:Ji$d

Total supply current (tcyc=470ns)

;:
~.$,. ~.,:,.,
*y?!~
,
Cin
..,.
,.e.$,,,i,
.T,.

Total capacitance*
(* Design specification value only - NOT tested)

,.!!)

.,:
~+:$;$,
,,
:
:.
. :s:~-
..\$T\~

4.1
Vss

$,a;:~
... :~ Vdd
*~A>
,\.~
.*,.
...y. ,:>
.3$)y:}.><~~
*$
.~,,
.,;..
\,.~,
Idz ,,?,
.*>t~m~
~sf.,
+/- 10
.~::
i~*:J
\$y

Input leakage current PORT 3,

A8-A15, E, AS, RW, RESET IN, 1S3

MOTOROU
12

Min

v
PA

-150

PA

350

PA

12

pF

,,.: ~.$,,
,.$:,,,
;$+ *,+
..?,*.i\\4J
...
?.
~.%:y;>:....+.l,;:,.
~.,
t,,,...
,.:~,
.$~

MC68HC25

BUS TIMING

CHARACTERISTICS

(Vdd=5.OV(+/-1O%)VSS=OV Ta=-40C to +85C)

Ident
Numbel

Characteristics

S,mbo,w

Cycle Time

tcyc

Pulse Width Low (high)

E Clock Rise and Fall

tr,tf

R/W Hold Time

trwh

10

18

Read Data Hold Time

21

Write Data Hold Time

22

AO-A7 Valid Time to E Rise

24

AO-A7 Setup Time before AS Fall

25

AO-A7 Hold Time after AS Fall

26

Delay Time E fall to AS rise

25

,<:$*,,:,,
.:J!,.
,k.
!$ p ns

tav

70

13

R/W Setup Time before E Rise

trws

70 6$<:p~

tdhr

29

30
31

,..
],+
,\,,S:T.

~Data Out Delay (read)

Data In Data Setup Time (write)

~$~
,,*,.. $:
Peripheral Data Setup Time
~~)+>ii,..:!?
,.
$<:~t+
$~<>\
Peripheral Data Hold Time -,~:$:$;:?,
35

Input Data Hold Time ,,,:l,$~j~

.,
,,.

36
..

.. .

ns
ns

,$~~$kp
v
tdhw t#*;?~&
,,\.
tav~~ >$:75
.,:+.
#$ya[ :
20
F
,;,$.
*?.:*ail
10
,. .... ..
.*:$,
,,,
).b;* tasd
50
,..$:,
;,
,.,:.. ,.,-.
-,
*J).::+>>}.
twash
90
..:. ~,k
.,,
..
,$$ ~~.$%,
?,>
tased
50
!{:,.?+,.
,,,*

AO-A7 Output Delay

ns,,,>
~
.,,,
*
~:~~.$
,, .,.,:?<

>

~:;?ks
:.$.
,,..+,

Non-Muxed Address Valid Time to E

Delay Time AS Fall to E Rise

ns

12

AS Pulse Width High

476

pwel(h) 200(210)

F
F
F

Unit

ns
ns
ns
ns
ns
ns
ns

taod

90

ns

tddr

175

ns

tdsw

125

ns

tpwsu

100

ns

tpdh

100

ns

tih

30

ns

tis

40

ns

tpwis

100

ns

,!~~$~

38

Delay Tim~~ PeF@#eralData Write

tpwd

210

ns

39

Delay ~~&[~~able
Tran@@$.

tosdl

200

ns

tosd2

200

ns

tcsl

120

ns

tcsh

120

ns

tirq

150

ns

40

Positive Transition to 0S3 Negative

Q@@~;fime,Enable Positive Transition to ~

~Tr<h%ition

4(;2s ~~elay Time E Rise to ~1~

vf~~

Delay Time E Fall to ~i~

Positive

Asserted (Low)
Negated (High)

43

Delay Time E Rise to ~Assetied

44

Delay Time E Rise to RSO Asseded (Low)

trso

200

ns

45

Delay Time E Rise to RSO Negated (High)

trsh

200

ns

(Low)

NOTES:
1, All Timing is shown with respect to 20% VDD unless otherwise
2, VOH level measurement

MC68HC25

noted.

point is at 60% VDD.

MOTOROU
13

TIMING CHARACTERISTICS
The external

timing

of the circuit

is shown

in figures

5 to 11

Bus Timing

Address
(Non-Muxed

+!

e!
I

Rw

Add/Data
Muxed

Read

I
1

Add/Data
Muxed

Write
I
I
,.:,.

,?,

Address
Low

Out
I

II

Figure 5
Note:
1.
All Timing
MOTOROLA
14

is shown

with

respect

to 20%

VDD and 70%

VDD unless

otherwise

noted.

MC68HC25

Port #3 Latch Timing

II

II

1s3

P30 - P37
Inputs

,.

MPU write
*

Port 3 non-latched

operation

Figure 7

MC68HC25

MOTOROLA
15

CS1/CS2 ~ming
I
I

I
I
I
I
I
I

I
I
I
I
I
,

Address
Bus

{,~~$
J,)

I
I

42

Access matches output strobe select (0SS = O, a read; 0SS = 1, a write)

Figure 9

MOTOROU
16

MC68HC25

IRQ Timing

I
E

Address

44

;+

@
1

45

Figure 11

MC68HC25

MOTOROU
17

Mode Select Register Load Sequence

Reset In

Internal Reset In

Reset Out

Address Low Out

,:,>,
Load Mode Register

Address/Data Low In
PROM 1 Read

Csl

MOTORO~
18

.....

MC68HC25

MC6BHC25

MOTOROU
19

J!Y.
s...
.. .,,.*,
,,
:i:j,.$>$+,
c~;$,

&otorola reserves the right to make changes without funher notice to any products herein to improve reliabihty, function or design. Motorola doee not aasume any
IiAbilityarising out of theapphcstion oruseof any product or circuit described herein; neither does it convevanvlicense under its patent rights nor the rights of others,
Motorola products are not authorized for use as components in life support devices or sy~ems intended for surgical implant into the bdy or intended to suppon
or sustain life. B~er agrees to notifv Motorola of any such intended end use whereupon Motorola shall determine availability and suitability of its products for the
use intended. Motorola and @
are registered trademarks of Motorola, Inc. Motorola, Inc. ia an Equal Employment Opwrtunity/Affirmative Action Employer,

Literature Distribution Centres:

USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036.
EUROPE: Motorola Ltd; European Literature Centre: 88 Tanners Drive, Blakelands, Milton Keynes, MK14 56P, England.
ASIA PACIFIC: Motorola Semiconductors
H.K. Ltd.; PO. Box 80300 Cheung Sha Wan Post Offics Kowloon, Hong Kong.
JAPAN: Nippon Motorola Ltd.; 3-20-1 Minamiazabu, Minato-ku, Tokyo 106 Japan.

MOTOROLA
,,1.,,6
I.
Greet

0,1,.1

b,

Tavlsto.k

Press (B.4tOrd)

Lid

4000

S!90

MC68HC25