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UNIVERSITY OF HOUSTON – CLEAR LAKE

Design of a 4 – bit ALU using VHDL

Luz Orlando Ramirez and Alfredo Nava CENG 3511, Section 2, Saurin Ganatra

4 bit ALU designed using behavioral VHDL coding techniques. The 4 bit ALU using the aforementioned coding techniques successfully performed arithmetic, logical, and shifting operations. The ALU performs a limited number of arithmetic, logical, and shifting operations dependent on the user defined input.

CENG 3511

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Contents

I. Background

2

II. Project Overview

2

a. Objective

2

b. Method

2

c. Procedure

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III. Observations

3

IV. RTL (Register Transfer Level) schematic and Waveform of ALU

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a. Top level

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b. Detailed RTL schematic

3

c. Waveforms

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V. Conclusion

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VI. Recommendation

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Works Cited

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Appendix

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VHDL Code for ALU

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VHDL Code for 4-bit Full Adder

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VHDL Code for a 1-bit Full Adder

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Detailed RTL Schematic of designed ALU

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CENG 3511

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Introduction

The main goal of this experiment is to design a 4-bit ALU using one main VHDL coding technique

The 4-bit ALU was implemented using a VHDL coding techniques that model a four bit

VHDL coding was primarily done using a student version of XILINX

using XILINX.

full adder and numerous MUXes.

software.

I. Background

ALU’s (Arithmetic Logic Units) are significant in that they primarily perform nearly all arithmetic and logical operations. “The arithmetic logic unit (ALU) is the brawn of the computer, the device that performs the arithmetic operations like addition and subtraction or logical operations like AND and OR” (Patterson, Hennessy C-26). More detailed information about MUXes, Adders, and other devices can be found in the textbook Fundamentals of Logic Design (2010) by Charles H. Roth, JR. and Larry L. Kinney. Also a complete description of ALU’s is provided by the text Computer Organization and Design (2009) by David A. Patterson and John L. Hennessy.

The primary goal and results of the experiment will be discussed in the following sections.

II. Project Overview

a. Objective

Build a 4-bit ALU that performs basic arithmetic, logic, increment/decrement and shifting operations using only one VHDL coding technique. The 4-bit ALU will have: 4-bit input, output and operation select lines and 1-bit carry in and carry out lines. In addition, the 4-bit ALU will perform eleven distinct operations.

b. Method

To enter different inputs into the 4-bit ALU to determine if the outputs of the ALU correspond to the predicted function and result. A pre-defined set of Operation Select of 4-bit inputs will aid in the identification in the case that the ALU produces an output that does not agree with the predicted function or outcome.

c. Procedure

Since the ALU is composed of numerous internal components the operation select inputs are a significant role in determining what output the ALU produces. Specifically, there are only two cases in which the carry in line is not treated as a don’t care and does not affect the ALU output, these occur when 4-bit input A needs to be transferred directly onto the 4-bit output G. Although, the design of the 4-bit ALU includes a four-bit full adder the output of the ALU is significantly affected by the numerous MUXes used in the design as defined per the use of “WHEN-ELSE” VHDL statements in main VHDL source file. In respect to the carry out output of the ALU, the ALU was designed so that the carry out retains the previous carry in of a past operation where in the carry in is not in use.

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I II.

Obse rvations

 

a.

T

he design i mplemented

effective u se of multip plexers for

all the signa ls. This all ows for eac h

 

s

gnal to be

modified an d reused ac cording to t he operatio n the ALU

needs to pe rform. Thes e

here used t o increase th e efficiency of the desig n, and impl ement four arithmetic fu nctions wit h o nly a single adder.

w

 

b.

T

he heavy u se of MUX es helped i ncrease the

stability sig nificantly b y allowing

the ALU t o

 

p roduce its o wn internal signals for o perations w here the Cin was not ne cessary.

 

c.

M UXes redu ce errors in the design

of the ALU is that all c ases are co vered for ea ch signal, s o

 

t

at a signal

will never gi ve an “Unid entified” ou tput or erro r.

 
 

d.

M UXes have

minimal p ropagation

delay, and

are a much

better impl ementation

than severa l

 

a rithmetic co mponents.

 

I V.

RTL (Register T ransfer Le vel) schema tic and Wa veform of

ALU

a.

T

op level

F I GURE 1.2 A LU with in t ernal comp o nents

F IGURE 1.2

ALU with in ternal comp onents

A

larger version n of FIGURE

1.2 is availab le in the App endix

se ction of the re port. On furth er inspection

of the ALU on e can multiple fou r bit

no

tice the pref erred use of

MUXes over

ad

ders.

b.

D

etailed RTL

schematic

F I GURE 1.1 T op Level R TL Schemat i c of ALU

F IGURE 1.1

Top Level R TL Schemat ic of ALU

T he schematic

depicts a top

level represen tation of the

A LU with its re spective input and outputs.

Note that Op

(3 :0) is what d etermines wha t operation th e ALU will

pe

rform.

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c.

W

aveforms

d.
d.

FI GURE 1.3 A LU Wavef orm of AL U

sec ond test case

trac k of since if a n arithmetic o peration occu rs for thousan ds of times a hav e a significant outcome on th e calculated p roduct.

does not have overflow.

The above wavef orm represents two test case s. The first te st case happe ns to have ove rflow while th e

Th e values of c arry in and ca rry out are im portant to kee p

missing value of carry in ca n

V. Conc lusion

in is not ne eeded. Also , since the 4 -bit ALU V HDL sourc e

RTL Sche matic in X ILINX disp lays variou s

i nternal MU Xes. The i nternal use of MUXes in the 4-bit ALU impr oves perfor mance but t he more tha t

a

p erformance – cost trade off in the de sign of the 4-bit ALU.

For som e ALU oper ations the v alue of carry

c ode contai ns numerou s “WHEN- ELSE” stat ements the

MUXes are

used the m ore probab le that the

cost of the

design co uld increas e.

Thus, th ere exists

VI.

Reco mmendatio n

Inclu ding a cost- performanc e analysis in the project to illustrate how cost c an limit the performanc e o f an ALU a nd vice vers a.

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Works Cited

Roth, Charles H., and Larry L. Kinney. Fundamentals of Logic Design . Stamford, CT: Cengage Learning,

2010. Print.

Patterson, David A., and John L. Hennessy. Computer Organization and Design . Boston: Morgan Kaufmann,

2009. Print.

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A ppendix

VHDL Code for ALU

CENG 35 1 1 6 A ppendix VHDL Code for A LU

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V HDL Code for 4-bit F ull Adder

CENG 35 1 1 9 V HDL Code for 4-bit F ull Adder V H DL

V HDL Code for a 1-bit F ull Adder

CENG 35 1 1 9 V HDL Code for 4-bit F ull Adder V H DL

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Detail ed RTL Sc hematic of designed ALU

CENG 35 1 1 10 Detail ed RTL Sc hematic of d esi gned ALU