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+t
PHL PLH
t = ----------------------------------------p
2
Typical complex system has 20-50 propagation delays per clock
cycle.
Typical propagation delays < 1nsec
B. Hand Calculation
Use an input signal that has tr=0 and tf=0 for hand calculation
Calculate current drive
Calculate capacitance being driven
VIN
VOH
tCYCLE
VOL
t
VOUT
tPHL
tPLH
VOH
VOH
50%
tCYCLE
VOL
t
VDD
2
W
L n2
W
L p1
VIN
+
VOUT
CL
VIN
VDD
W
L n1
W
L p3
W
L n3
(a)
(b)
in
ox
( W L ) p + C ox ( W L ) n
CG above is
C
ox
( WL ) p2 + C ox ( WL ) n2 + C ox ( WL ) p3 + C ox ( WL ) n3
source
interconnect
drain
interconnect
bulk
interconnect
,
,,,,
,,,,
,,
,,,,
,,,,
,,,
,,,,
,,,,
deposited
oxide
,
,,
,,
,,
L
field
oxide
n+ drain diffusion
Ldiff
n+ source diffusion
p+
[ p-type ]
(a )
,,,,,
,
,,,,
,,,
, , ,,,,,,,,,,,,,,
,,,,, ,,,,,,,,,,,,
,,,,, , , , , , ,
,,,,, , , , , ,
,
,
,,,,,,,,,,,,
,,,,,,,,,,,,
,
,
,
,
,
,
gate contact
gate
interconnect
polysilicon gate
contact
n+ polysilicon gate
metal
interconnect
source contacts
bulk
contact
source
interconnect
drain
interconnect
drain
contacts
edge of
active area
(b)
Ldiff
(c)
,,
E. Parasitic Capacitance-Wires
Wires consist of metal lines connecting the output of the inverter
to the input of the next stage
,,
,,,,,
,,,,,
,,,,,
,,,,,
,,,,,
,,,,,
,,,,,
,,,,,
,
,
,
metal interconnect
(width Wm, length Lm)
polysilicon
gate
p+
(grounded)
gate oxide
The p+ layer (i.e., heavily doped with acceptors) under the thick
thermal oxide (500 nm = 0.5 m) and deposited oxide (600 nm = 0.6
m) depletes only slightly when positive voltages appear on the
metal line, so the capacitance is approximately the oxide
capacitance:
wire
thickox
( W m Lm)
VOH
slope = dvOUT / dt
VOH/2
tPHL
( V OH 2 ) V OH
I Dn ( sat )
--------------- = ---------------------------------------- = ----------------------t
dt
C +C
PHL
G
P
dv
OUT
PHL
( C G + C P ) ( V OH 2 )
= -----------------------------------------------------------------------------------2
( 1 2 ) n C ox ( W L ) n ( V OH V Tn )
H. Graphical Interpretation
The n-channel driver remains saturated throughout the first half of
the transition from high-to-low... all that matters, according to the
definition of propagation delay for hand analysis.
ID
VOUT
t = 0+
VIN = VOH
t = tPHL
VOH
t = 0
VIN = 0V
VOH
2
0
0
VOH
2
VOH
VOUT
(a)
0
0
tPHL
(b)
PLH
( C G + C P ) ( V OH 2 )
= -------------------------------------------------------------------------------------2
( 1 2 ) p C ox ( W L ) p ( V OH + V Tp )
charge
i(t) dt
V Q
+ 2
= ( V ) ( CG + C P)
E
= - (C + C ) (V )
store 2
G
P
Energy lost in p-channel MOSFET during charging:
E
diss
1- ( C + C ) ( V + ) 2
E
=
2 G
charge
store
P
= ( 2E diss )
+ 2
= ( CG + C P) ( V )
In practice, many gates dont change state for every clock cycle,
which lowers the power dissipation
Additional source of dissipation: power flow from V+ to ground
when both transistors are saturated. Can be signifcant, but hard to
estimate by hand. Eliminate with Circuit Techniques.
M3
M4
A
B
+
M2
VOUT
_
M1
(b)
VDD
VM
M3
M4
ID
VM
VM
VGS1 = VM
M2
+
V
M1 DS1
VGS2 = VM VDS1
ID1 = ID2
VDS
(a)
(b)
,,
,,
VM
,,
,,
source
VM
gate
gate
M1
M2
n+
L1
L2
(a)
,,
,,
drain
VM
,,
source
VM
gate
gate
M1
M2
L1
L2
,,
drain
(b)
M W
W
= --- ----- Ln
2 Lp
M4
A
M3
+
M1 B
M2 VOUT
_
(a)
W
= 2M W
---- Lp
Ln