ASIC-System on Chip-VLSI Design: Synthesis Con...

http://asic-soc.blogspot.in/2007/10/synthesis-cons...

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Synthesis Constraints
Let us discuss something about ASIC front end design and its related issues. I would like post some articles
related to synthesis constraints, DFT and formal verification. I will consider Synopsys tools to support the
discussion.
Three types of constraints can be set for the design in Design Compiler (DC). They are:
1) DRC constraints
2) Optimization constraints
3) Environmental constraints.
DRC constraints exist in library. DRC constraints cant be relaxed. They can be chosen from library.
DRC constraints are: set_max_fanout, set_max_transition, set_max_capacitance.
If DRC constraints are not specified, then default values from the library are taken.
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Three types of optimizations are possible-area, power and timing. We have optimization constraints related to
all these.

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set_max_area, set_min_area are area constraints.

Only basic level of power optimization is carried out by DC. Its primary target is to meet timing constraints.
set_max_leakege and set_max_dynamic are the two power constraints that can be provided to DC.

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Both DRC and optimization constraints follow environmental constraints. Setting up of operating conditions and
wire load model falls under environmental constraints. The constraints are: set_operating_conditions,
set_wire_load_model and set_wire_load_mode. By default enclosed wire load mode is considered by DC.
Synthesis is timing driven process. Several timing constraints are put to synthesis process of SAMM. No timing
specifications may be mentioned for a design. Hence to extract the possible value of clock,
derive_timing_constraints command is used. This gives a clock period of x. A nearest clock period less than
x can be chosen. This value of clock should satisfy slack requirement of DFT enabled circuit also.
Examples of timing constraints are listed bellow:
->set_clock -period 4.75 clock: Clock period constraint set at 4.75 (210 MHz).
->set_clock_uncertainty setup 0.475 clock: -ve clock skew can lead to setup violations. Possible value of ve
skew is provided to DC so that it can model for that. Generally setup uncertainty is taken as 10% of the clock.
->set_clock_uncertainty hold 0.27 clock: +ve clock skew can lead to hold violations. Possible value of +ve
skew is provided to DC so that it can model for that. Generally hold uncertainty is taken as 5% of the clock.
->set_clock_latency 0.45 clock: This provides possible network latency constraint to DC.
->set_clock_latency source 0.4 clock: Source latency of 0.45 is selected.

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04/24/2014 03:31 PM

ASIC-System on Chip-VLSI Design: Synthesis Con...

http://asic-soc.blogspot.in/2007/10/synthesis-cons...
and Answers
Below are the sequence of questions asked for a
physical design engineer. In which field are you
interested? Answer to this question...

->set_clock_transition 0.04 clock: Clock transition time of 0.04 is modeled.

->set_input_delay 0.40 [all_inputs]: Input delay of 0.4 is set to all inputs.

Clock Gating
Clock tree consume more than 50
% of dynamic power. The
components of this power are: 1)
Power consumed by
combinatorial log...

->remove_input_delay [get_ports clock]: Constraining clock with input delay leads to wrong timing analysis. To
exclude clock port from the input delay this command is used.
->set_output_delay 0.40 [all_outputs]: Output delay of 0.4 is provided. If all outputs are registered this delay
does not affect the timing analysis.
I/O ports of the design become pads of the IC. Hence tool has to be informed about this so that it analyzes
delay, area and power appropriately. This is done using command set_port_is_pad, which sets the I/O ports as
pad and insert_pad, which inserts pad.

What is the difference between FPGA and

CPLD?
FPGA-Field Programmable Gate Array and
CPLD-Complex Programmable Logic Device-both are programmable logic devices made by
the same compani...

Reference

Clock Definitions
lock Definitions: Rising and falling
edge of the clock For a +ve edge
triggered design +ve (or rising)
edge is called ...

[1] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler
and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[2] Design Compiler User Guide, Version X-2005.09, September 2005

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Tags: Synthesis

Verilog code for asynchronous FIFO

Verilog code for asynchronous FIFO is given
below. The module a_fifo5 should be used for
Modelsim (or any other HDL simulator)
simulation...

1 comment:
vinoth April 2, 2009 at 2:14 PM
Is the code Synthesizable, if we use Switch Level Modelling in Verilog?
In case of structural, behavioral and gate level modelling, the RTL is translated to GTECH representation which is
technology independent. Then the logic is optimized and mapped to standard cells in technology library. The
standard cells will be primitive gates, flops. AOI, OAI cells etc...

Temperature controller using

Microchip PIC16F877A
Microcontroller
In continuously monitoring the
surrounding temperature of
industrial applications
Temperature Monitoring Control System play v...
Setup and hold slack
13. Setup and hold slack Slack
Slack is defined as difference
between actual or achieved time
and the desired time for a timing
...

I need to know whether any transistor components will be available in technology library. If the tech library does
not have NMOS, PMOS and CMOS transistors, then how mapping will happen and the switch level modelling will
properly get synthesized. Please let me know in this regard.
Reply

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