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Input-Output Organization

INPUT-OUTPUT ORGANIZATION
Peripheral Devices
Input-Output Interface
Asynchronous Data
Transfer
Modes of Transfer
Priority Interrupt
Direct Memory Access

Computer Architectures

Input-Output Organization

Input/Output Interfaces

INPUT/OUTPUT INTERFACE
Provides a method for transferring information between internal storage (such as
memory and CPU registers) and external I/O devices
Resolves the differences between the computer and peripheral devices
Technology
Peripherals - Electromechanical Devices, electromagnetic,
CPU or Memory Electronic (semiconductor) Device
Data Transfer Rate
Peripherals - Usually slower
CPU or Memory - Usually faster than peripherals
Data Length and Format
Peripherals Byte, Block,
CPU or Memory Word, Binary

Computer Architectures

Input-Output Organization

Input/Output Interfaces

I/O BUS AND INTERFACE MODULES


I/O bus

Data
Address
Control

Processor

Interface

Interface

Interface

Interface

Keyboard
and
display
terminal

Printer

Magnetic
disk

Magnetic
tape

Each peripheral has an interface module associated with it


Interface
- Decodes the device address (device code)
- Decodes the commands (operation)
- Provides signals for the peripheral controller
- Synchronizes the data flow and supervises
the transfer rate between peripheral and CPU or Memory

Computer Architectures

Input-Output Organization

Input/Output Interfaces

CONNECTION OF I/O BUS


Connection of I/O Bus to One Interface
Data lines

Device
address

I/O
bus

Peripheral
register
Buffer register

AD = 1101

Function code

Status lines

Interface
Logic

Output
peripheral
device
and
controller

Command
decoder
Status
register

Computer Architectures

Input-Output Organization

Input/Output Interfaces

I/O BUS AND MEMORY BUS


Physical Organizations

* Many computers use a common single bus system


for both memory and I/O interface units
* Some computer systems use two separate buses,
one to communicate with memory and the other with I/O interfaces

Computer Architectures

Input-Output Organization

Input/Output Interfaces

ISOLATED vs MEMORY MAPPED I/O


Isolated I/O
- Separate I/O read/write control lines in addition to memory read/write
control lines
- Separate (isolated) memory and I/O address spaces
- Distinct input and output instructions
Memory-mapped I/O
- A single set of read/write control lines
(no distinction between memory and I/O transfer)
- Memory and I/O addresses share the common address space
reduces memory address range available
- No specific input or output instruction
The same memory reference instructions can
be used for I/O transfers
- Considerable flexibility in handling I/O operations

Computer Architectures

Input-Output Organization

Input/Output Interfaces

EXAMPLE OF I/O INTERFACE


Bidirectional
data bus

I/O data

Port B
register

I/O data

Bus
buffers

Chip select

CS

Register select

RS1

Register select

RS0

I/O read

RD

I/O write

WR

CS RS1 RS0
0
x
x
1
0
0
1
0
1
1
1
1
1
1
0

Timing
and
Control

Internal bus

CPU

Port A
register

Control
register
Status
register

Control

I/O
Device

Status

Register selected
None - data bus in high-impedence
Port A register
Port B register
Status register
Control register

Computer Architectures

Input-Output Organization

EXAMPLE OF I/O INTERFACE


The transfer of data, control, and status is always via the common data bus.
The distinction between data, control, or status is determined from the particular
interface register with the CPU communication.
By loading appropriate bits into control register, the operating mode of the
interface can be controlled:
Port A may be defined as an input port, port B as an output port,

Status register is used for status conditions and for errors


A status bit may indicate that port A has received a new data
Another bit may indicate that a parity error has occurred

Computer Architectures

Input-Output Organization

Asynchronous Data Transfer

DATA TRANSFER
Four Different Types of Transfer
1.

Asynchronous parallel transfer

2.

Synchronous parallel transfer

3.

Asynchronous serial transfer

4.

Synchronous serial transfer

Synchronous Data Transfer: All devices derive the timing information


from common clock line
Asynchronous Data Transfer: No common clock

Computer Architectures

Input-Output Organization

Asynchronous Data Transfer

DATA TRANSFER
Asynchronous Data Transfer
Asynchronous data transfer between two independent units requires that
control signals be transmitted between the communicating units to
indicate the time at which data is being transmitted

Two Asynchronous Data Transfer Methods


Strobe pulse
- A strobe pulse is supplied by one unit to indicate the other unit when the
transfer has to occur
Handshaking
- A control signal is accompanied with each data being transmitted to indicate
the presence of data
- The receiving unit responds with another control signal to acknowledge
receipt of the data

Computer Architectures

Input-Output Organization

Asynchronous Data Transfer

STROBE CONTROL
* Employs a single control line to time each transfer
* The strobe may be activated by either the source or the destination unit

Source-Initiated Strobe
for Data Transfer

Destination-Initiated Strobe
for Data Transfer

Block Diagram

Block Diagram
Data bus

Data bus
Source
unit

Strobe

Timing Diagram
Data

Strobe

Destination
unit

Source
unit

Destination
unit

Strobe

Timing Diagram
Valid data

Valid data
Data

Strobe

Computer Architectures

Input-Output Organization

Asynchronous Data Transfer

HANDSHAKING
Strobe Methods Problems
Source-Initiated
The source unit that initiates the transfer has no way of knowing whether the
destination unit has actually received data
Destination-Initiated
The destination unit that initiates the transfer no way of knowing whether
the source has actually placed the data on the bus
To solve this problem, the HANDSHAKE method introduces a second control
signal to provide a Reply to the unit that initiates the transfer

Computer Architectures

Input-Output Organization

Asynchronous Data Transfer

SOURCE-INITIATED TRANSFER USING HANDSHAKE


Block Diagram

Timing Diagram

Data bus
Data valid
Data accepted

Source
unit

Destination
unit

Valid data

Data bus

Data valid

Data accepted

Sequence of Events

Source unit

Destination unit

Place data on bus.


Enable data valid.
Accept data from bus.
Enable data accepted
Disable data valid.
Invalidate data on bus.
Disable data accepted.
Ready to accept data
(initial state).

* Allows arbitrary delays from one state to the next


* Permits each unit to respond at its own data transfer rate
* The rate of transfer is determined by the slower unit
Computer Architectures

Input-Output Organization

Asynchronous Data Transfer

DESTINATION-INITIATED TRANSFER USING HANDSHAKE


Block Diagram

Timing Diagram

Source
unit

Data bus
Data valid
Ready for data

Destination
unit

Ready for data

Data valid

Data bus

Sequence of Events

Source unit
Place data on bus.
Enable data valid.

Disable data valid.


Invalidate data on bus
(initial state).

Valid data

Destination unit
Ready to accept data.
Enable ready for data.

Accept data from bus.


Disable ready for data.

* Handshaking provides a high degree of flexibility and reliability because the


successful completion of a data transfer relies on active participation by both units
* If one unit is faulty, data transfer will not be completed
Can be detected by means of a timeout mechanism
Computer Architectures

Input-Output Organization

Example: parallel printer interface


Data

/Strobe
Parallel
Printer
Port

/Ack

Parallel
Printer
Port

Busy

The computer checks the BUSY signal from the printer, if not BUSY then:
When the PC presents a character to the data bus, it activates the STROBE pin, telling it
that there is a byte sitting at the data pins. Prior to asserting STROBE pin, the data must be
at the printers data pins for at least 0.5 s. (data setup time)
The STROBE must stay for 0.5 s
The printer asserts BUSY pin indicating the PC to wait
When the printer picks up the data, it sends the ACK signal, keeps ACK low for 5 s.
As the ACK signal is going high, the printer makes the BUSY pin low to indicate that it
is ready to accept the next byte
The PC can use ACK or BUSY signals from the printer to initiate the process of sending
another byte
Computer Architectures

Input-Output Organization

Asynchronous Data Transfer

ASYNCHRONOUS SERIAL TRANSFER


Asynchronous Serial Transfer
- Employs special bits which are inserted at both ends of the character code
- Each character consists of three parts; Start bit; Data bits; Stop bits.

1
Start
bit
(1 bit)

Character bits

1
Stop
bits
(at least 1 bit)

A character can be detected by the receiver from the knowledge of 4 rules;


- When data are not being sent, the line is kept in the 1-state (idle state)
- The initiation of a character transmission is detected by a Start Bit , which is always a 0
- The character bits always follow the Start Bit
- After the last character, a Stop Bit is detected when the line returns to the 1-state for at
least 1 bit time

The receiver knows in advance the transfer rate of the bits and the number of
information bits to expect
Computer Architectures

Input-Output Organization

Modes of Transfer

MODES OF DATA TRANSFER


3 different Data Transfer Modes between the central computer (CPU or
Memory) and peripherals;
1.

Program-Controlled I/O

2.

Interrupt-Initiated I/O

3.

Direct Memory Access (DMA)

Computer Architectures

Input-Output Organization

Modes of Transfer

MODES OF TRANSFER: PROGRAM-CONTROLLED I/O


Program-Controlled I/O (Input Dev to CPU)
Interface

Data bus
Address bus
CPU

I/O bus

Data register

I/O read
I/O write

Status
register

Data valid

I/O
device

Data accepted

Read status register


Check flag bit

flag

=0

=1
Read data register
Transfer data to memory
no

Operation
complete?

Polling or Status Checking

- Continuous CPU involvement


- CPU slowed down to I/O speed
- Simple
- Least hardware

yes
Continue with
program

Computer Architectures

Input-Output Organization

Modes of Transfer

MODES OF TRANSFER: INTERRUPT INITIATED I/O


Interrupt Initiated I/O
- Open communication only when some data has to be passed
- I/O interface, instead of the CPU, monitors the I/O device
- When the interface determines that the I/O device is ready for data
transfer, it generates an Interrupt Request to the CPU
- Upon detecting an interrupt, CPU stops momentarily the task it is doing,
branches to the service routine to process the data transfer, and then
returns to the task it was performing

Computer Architectures

Input-Output Organization

Modes of Transfer

MODES OF TRANSFER: DMA


DMA (Direct Memory Access)
- Large blocks of data transferred at a high speed to or from high speed
devices, magnetic drums, disks, tapes, etc.
- DMA controller
Interface that provides I/O transfer of data directly to and from the
memory and the I/O device
- CPU initializes the DMA controller by sending a memory address and the
number of words to be transferred
- Actual transfer of data is done directly between the device and memory
through DMA controller
Freeing CPU for other tasks

Computer Architectures

Input-Output Organization

Priority Interrupt

PRIORITY INTERRUPT
Priority
Determines which interrupt is to be served first when two or more requests
are made simultaneously
Also determines which interrupts are permitted to interrupt the computer
while another is being serviced
Higher priority interrupts can make requests while servicing a lower priority
interrupt
Priority Interrupt by Software(Polling)
Priority is established by the order of polling the devices(interrupt sources)
+ Flexible since it is established by software
+ Low cost since it needs a very little hardware
- Very slow
Priority Interrupt by Hardware
- Require a priority interrupt manager which accepts all the interrupt requests to
determine the highest priority request
- Fast since identification of the highest priority interrupt request is identified by
the hardware
- Fast since each interrupt source has its own interrupt vector to access directly
to its own service routine
Computer Architectures

Input-Output Organization

Priority Interrupt

HARDWARE PRIORITY INTERRUPT


VAD 1
Device 1
PI
PO

Processor data bus


VAD 2
Device 2
PI
PO

VAD 3

Device 3
PI
PO

To next
device

Interrupt request

INT

CPU
Interrupt acknowledge

INTACK

* Serial hardware priority function


* Interrupt Request Line - Single common line
* Interrupt Acknowledge Line - Daisy-Chain
Interrupt Request from any device
CPU responds by INTACK
Among interrupt requesting devices the only device which is physically
closest to CPU gets INTACK=1, puts the VAD on the bus, and it blocks
INTACK to propagate to the next device
interrupt acknowledge line is passed through each device, from the highest
priority device first, to the lowest priority device last.
Computer Architectures

Input-Output Organization

DAISY-CHAIN
One stage of the daisy chain priority arrangement
PI
Interrupt
request
from device

Priority in

VAD

Enable

Vector address

Priority out

RF
S

PO

Delay
Interrupt request to CPU

PI RF PO Enable
0 0
0
0
0 1
0
0
1 0
1
0
1 1
0
1

Computer Architectures

Input-Output Organization

Priority Interrupt

PARALLEL PRIORITY INTERRUPT


Bus
Buffer

Interrupt register
Disk

I0

Printer

I1

Reader

Keyboard

Priority
I 2 encoder

I3

VAD
to CPU

0
0
Mask
register

1
2
3

IEN

IST

0
0
Enable
Interrupt
to CPU
INTACK
from CPU

IEN: Set or Clear by instructions ION or IOF


IST: (Interrupt Status) Represents a not masked interrupt has occurred. INTACK
enables tristate Bus Buffer to load VAD generated by the Priority Logic
Interrupt Register:
- Each bit is associated with an Interrupt Request from different Interrupt Source different priority level
- Each bit is set by external condition and cleared by a program instruction
Mask Register:
- Mask Register is associated with Interrupt Register
- Each bit can be set or cleared by an Instruction
Computer Architectures

Input-Output Organization

Priority Interrupt

INTERRUPT PRIORITY ENCODER


Determines the highest priority interrupt when
more than one interrupts take place

Priority Encoder Truth table


Inputs
I0
1
0
0
0

I1
X
1
0
0

X
X
1
0

Outputs
x

y IST

X
X
X
1

0
0
1

0
1
0

1
1
1

X X

I2

I3

Boolean functions
x = I0' I1'
y = I0' I1 + I0 I2
(IST) = I0 + I1 + I2 + I3

Computer Architectures

Input-Output Organization

Priority Interrupt

INTERRUPT CYCLE
At the end of each Instruction cycle
- CPU checks IEN and IST
- If IEN IST = 1, CPU Interrupt Cycle
SP SP - 1 Decrement stack pointer
M[SP] PC Push PC into stack
INTACK 1 Enable interrupt acknowledge
PC VAD
Transfer vector address to PC
IEN 0 Disable further interrupts
Go To Fetch
to execute the first instruction
in the interrupt service routine

Computer Architectures

Input-Output Organization

Priority Interrupt

INTERRUPT SERVICE ROUTINE


address

VAD=0000001
1

KBD
interrupt

Memory
0
1
2
3

1
749
750
11
2

JMP DISK
JMP PTR
JMP RDR
JMP KBD
Main program

I/O service programs


7

DISK

Program to service
magnetic disk

PTR

Program to service
line printer

RDR

Program to service
character reader

current instr.
Stack

5
256
750

KBD

Disk
interrupt

Program to service
keyboard
255
256
6

10

Initial and Final Operations


Each interrupt service routine must have an initial and final set of operations for
controlling the registers in the hardware interrupt system
Final Sequence
Initial Sequence
[1] IEN 0
[1] Clear lower level Mask reg. bits
[2] Restore CPU registers
[2] IST 0
[3] Clear the bit in the Interrupt Reg
[3] Save contents of CPU registers
belonging to the device
[4] IEN 1
[4] Set lower level Mask reg. bits
[5] Proceed with Service Routine
[5] Restore return address, IEN 1
Computer Architectures

Input-Output Organization

Direct Memory Access

DIRECT MEMORY ACCESS


* Block of data transfer from high speed devices, Drum, Disk, Tape
* DMA controller - Interface which allows I/O transfer directly between Memory
and Device, freeing CPU for other tasks
CPU bus signals for DMA transfer
Bus request

BR

Bus granted

BG

Address bus

ABUS
DBUS
RD
WR

CPU

Data bus
Read
Write

High-impedence
(disabled)
when BG is
enabled

Block diagram of DMA controller


Address bus

DMA select
Register select
Read
Write

Data bus
buffers

DS
RS
RD
WR

Bus request

BR

Bus grant

BG

Interrupt

Control
logic

Interrupt

Address bus
buffers
Internal Bus

Data bus

Address register
Word count register
Control register

DMA request
DMA acknowledge

to I/O device

Computer Architectures

Input-Output Organization

Direct Memory Access

DMA I/O OPERATION


Starting an I/O
- CPU initializes the DMA by
1. Load starting address of memory block into Address Reg
2. Load word count into Word Count Reg
3. Load Function (Read or Write) to be performed into Control Reg
4. Issue a GO command
Upon receiving a GO Command DMA performs I/O operation as follows
Input
1. DMA checks DMA request
2. If DMA request is active, the DMA activates the BR line
3. CPU activates BG line
4. DMA puts the contents of AR into address bus, activates WR signal, and sends DMA
acknowledge
5. Peripheral device puts a word in the data bus
6. DMA increments AR and decrements WCR
7. If WCR does not reeach zero, go to 1.
If WCR reaches zero, DMA deactivate BR and sends interrupt to CPU.
Output ?
Computer Architectures

Input-Output Organization

Direct Memory Access

DMA TRANSFER
Interrupt
BG

Random-access
memory unit (RAM)

CPU

BR
RD

WR

Addr

Data

RD

WR

Addr

Data

Read control
Write control
Data bus
Address bus
Address
select
RD

WR

Addr

DMA ack.

DS
RS
BR
BG

Data

I/O
Peripheral
device

DMA
Controller
DMA request

Interrupt

Computer Architectures

Input-Output Organization

Direct Memory Access

CYCLE STEALING
When the DMA takes control of the bus system, the transfer can be
made in several ways:
DMA Burst Transfer:
a block of words is transferred in a continuous
burst until an entire block is transferred.
This mode needed for fast devices such as disks.
Cycle Stealing:
DMA transfers one word at a time, and returns control of the
buses to the CPU. The CPU merely delays its operation for one
memory cycle to allow DMA to steal one memory cycle.

Computer Architectures

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