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INPUT-OUTPUT ORGANIZATION
Peripheral Devices
Input-Output Interface
Asynchronous Data
Transfer
Modes of Transfer
Priority Interrupt
Direct Memory Access
Computer Architectures
Input-Output Organization
Input/Output Interfaces
INPUT/OUTPUT INTERFACE
Provides a method for transferring information between internal storage (such as
memory and CPU registers) and external I/O devices
Resolves the differences between the computer and peripheral devices
Technology
Peripherals - Electromechanical Devices, electromagnetic,
CPU or Memory Electronic (semiconductor) Device
Data Transfer Rate
Peripherals - Usually slower
CPU or Memory - Usually faster than peripherals
Data Length and Format
Peripherals Byte, Block,
CPU or Memory Word, Binary
Computer Architectures
Input-Output Organization
Input/Output Interfaces
Data
Address
Control
Processor
Interface
Interface
Interface
Interface
Keyboard
and
display
terminal
Printer
Magnetic
disk
Magnetic
tape
Computer Architectures
Input-Output Organization
Input/Output Interfaces
Device
address
I/O
bus
Peripheral
register
Buffer register
AD = 1101
Function code
Status lines
Interface
Logic
Output
peripheral
device
and
controller
Command
decoder
Status
register
Computer Architectures
Input-Output Organization
Input/Output Interfaces
Computer Architectures
Input-Output Organization
Input/Output Interfaces
Computer Architectures
Input-Output Organization
Input/Output Interfaces
I/O data
Port B
register
I/O data
Bus
buffers
Chip select
CS
Register select
RS1
Register select
RS0
I/O read
RD
I/O write
WR
CS RS1 RS0
0
x
x
1
0
0
1
0
1
1
1
1
1
1
0
Timing
and
Control
Internal bus
CPU
Port A
register
Control
register
Status
register
Control
I/O
Device
Status
Register selected
None - data bus in high-impedence
Port A register
Port B register
Status register
Control register
Computer Architectures
Input-Output Organization
Computer Architectures
Input-Output Organization
DATA TRANSFER
Four Different Types of Transfer
1.
2.
3.
4.
Computer Architectures
Input-Output Organization
DATA TRANSFER
Asynchronous Data Transfer
Asynchronous data transfer between two independent units requires that
control signals be transmitted between the communicating units to
indicate the time at which data is being transmitted
Computer Architectures
Input-Output Organization
STROBE CONTROL
* Employs a single control line to time each transfer
* The strobe may be activated by either the source or the destination unit
Source-Initiated Strobe
for Data Transfer
Destination-Initiated Strobe
for Data Transfer
Block Diagram
Block Diagram
Data bus
Data bus
Source
unit
Strobe
Timing Diagram
Data
Strobe
Destination
unit
Source
unit
Destination
unit
Strobe
Timing Diagram
Valid data
Valid data
Data
Strobe
Computer Architectures
Input-Output Organization
HANDSHAKING
Strobe Methods Problems
Source-Initiated
The source unit that initiates the transfer has no way of knowing whether the
destination unit has actually received data
Destination-Initiated
The destination unit that initiates the transfer no way of knowing whether
the source has actually placed the data on the bus
To solve this problem, the HANDSHAKE method introduces a second control
signal to provide a Reply to the unit that initiates the transfer
Computer Architectures
Input-Output Organization
Timing Diagram
Data bus
Data valid
Data accepted
Source
unit
Destination
unit
Valid data
Data bus
Data valid
Data accepted
Sequence of Events
Source unit
Destination unit
Input-Output Organization
Timing Diagram
Source
unit
Data bus
Data valid
Ready for data
Destination
unit
Data valid
Data bus
Sequence of Events
Source unit
Place data on bus.
Enable data valid.
Valid data
Destination unit
Ready to accept data.
Enable ready for data.
Input-Output Organization
/Strobe
Parallel
Printer
Port
/Ack
Parallel
Printer
Port
Busy
The computer checks the BUSY signal from the printer, if not BUSY then:
When the PC presents a character to the data bus, it activates the STROBE pin, telling it
that there is a byte sitting at the data pins. Prior to asserting STROBE pin, the data must be
at the printers data pins for at least 0.5 s. (data setup time)
The STROBE must stay for 0.5 s
The printer asserts BUSY pin indicating the PC to wait
When the printer picks up the data, it sends the ACK signal, keeps ACK low for 5 s.
As the ACK signal is going high, the printer makes the BUSY pin low to indicate that it
is ready to accept the next byte
The PC can use ACK or BUSY signals from the printer to initiate the process of sending
another byte
Computer Architectures
Input-Output Organization
1
Start
bit
(1 bit)
Character bits
1
Stop
bits
(at least 1 bit)
The receiver knows in advance the transfer rate of the bits and the number of
information bits to expect
Computer Architectures
Input-Output Organization
Modes of Transfer
Program-Controlled I/O
2.
Interrupt-Initiated I/O
3.
Computer Architectures
Input-Output Organization
Modes of Transfer
Data bus
Address bus
CPU
I/O bus
Data register
I/O read
I/O write
Status
register
Data valid
I/O
device
Data accepted
flag
=0
=1
Read data register
Transfer data to memory
no
Operation
complete?
yes
Continue with
program
Computer Architectures
Input-Output Organization
Modes of Transfer
Computer Architectures
Input-Output Organization
Modes of Transfer
Computer Architectures
Input-Output Organization
Priority Interrupt
PRIORITY INTERRUPT
Priority
Determines which interrupt is to be served first when two or more requests
are made simultaneously
Also determines which interrupts are permitted to interrupt the computer
while another is being serviced
Higher priority interrupts can make requests while servicing a lower priority
interrupt
Priority Interrupt by Software(Polling)
Priority is established by the order of polling the devices(interrupt sources)
+ Flexible since it is established by software
+ Low cost since it needs a very little hardware
- Very slow
Priority Interrupt by Hardware
- Require a priority interrupt manager which accepts all the interrupt requests to
determine the highest priority request
- Fast since identification of the highest priority interrupt request is identified by
the hardware
- Fast since each interrupt source has its own interrupt vector to access directly
to its own service routine
Computer Architectures
Input-Output Organization
Priority Interrupt
VAD 3
Device 3
PI
PO
To next
device
Interrupt request
INT
CPU
Interrupt acknowledge
INTACK
Input-Output Organization
DAISY-CHAIN
One stage of the daisy chain priority arrangement
PI
Interrupt
request
from device
Priority in
VAD
Enable
Vector address
Priority out
RF
S
PO
Delay
Interrupt request to CPU
PI RF PO Enable
0 0
0
0
0 1
0
0
1 0
1
0
1 1
0
1
Computer Architectures
Input-Output Organization
Priority Interrupt
Interrupt register
Disk
I0
Printer
I1
Reader
Keyboard
Priority
I 2 encoder
I3
VAD
to CPU
0
0
Mask
register
1
2
3
IEN
IST
0
0
Enable
Interrupt
to CPU
INTACK
from CPU
Input-Output Organization
Priority Interrupt
I1
X
1
0
0
X
X
1
0
Outputs
x
y IST
X
X
X
1
0
0
1
0
1
0
1
1
1
X X
I2
I3
Boolean functions
x = I0' I1'
y = I0' I1 + I0 I2
(IST) = I0 + I1 + I2 + I3
Computer Architectures
Input-Output Organization
Priority Interrupt
INTERRUPT CYCLE
At the end of each Instruction cycle
- CPU checks IEN and IST
- If IEN IST = 1, CPU Interrupt Cycle
SP SP - 1 Decrement stack pointer
M[SP] PC Push PC into stack
INTACK 1 Enable interrupt acknowledge
PC VAD
Transfer vector address to PC
IEN 0 Disable further interrupts
Go To Fetch
to execute the first instruction
in the interrupt service routine
Computer Architectures
Input-Output Organization
Priority Interrupt
VAD=0000001
1
KBD
interrupt
Memory
0
1
2
3
1
749
750
11
2
JMP DISK
JMP PTR
JMP RDR
JMP KBD
Main program
DISK
Program to service
magnetic disk
PTR
Program to service
line printer
RDR
Program to service
character reader
current instr.
Stack
5
256
750
KBD
Disk
interrupt
Program to service
keyboard
255
256
6
10
Input-Output Organization
BR
Bus granted
BG
Address bus
ABUS
DBUS
RD
WR
CPU
Data bus
Read
Write
High-impedence
(disabled)
when BG is
enabled
DMA select
Register select
Read
Write
Data bus
buffers
DS
RS
RD
WR
Bus request
BR
Bus grant
BG
Interrupt
Control
logic
Interrupt
Address bus
buffers
Internal Bus
Data bus
Address register
Word count register
Control register
DMA request
DMA acknowledge
to I/O device
Computer Architectures
Input-Output Organization
Input-Output Organization
DMA TRANSFER
Interrupt
BG
Random-access
memory unit (RAM)
CPU
BR
RD
WR
Addr
Data
RD
WR
Addr
Data
Read control
Write control
Data bus
Address bus
Address
select
RD
WR
Addr
DMA ack.
DS
RS
BR
BG
Data
I/O
Peripheral
device
DMA
Controller
DMA request
Interrupt
Computer Architectures
Input-Output Organization
CYCLE STEALING
When the DMA takes control of the bus system, the transfer can be
made in several ways:
DMA Burst Transfer:
a block of words is transferred in a continuous
burst until an entire block is transferred.
This mode needed for fast devices such as disks.
Cycle Stealing:
DMA transfers one word at a time, and returns control of the
buses to the CPU. The CPU merely delays its operation for one
memory cycle to allow DMA to steal one memory cycle.
Computer Architectures