EC2354 VLSI Design

Synchonizer
Lecture by
R. Sivarajan, Assistant Professor
Department of ECE
Adhiparasakthi Engineering College

Introduction
Sequencing element characterize by setup and hold
time
If D changes before setup time, output reflects new
value after bounded propagation delay
If D changes after hold time, output reflects old value
after bounded propagation delay
If D changes during aperture between setup and hold
time, output may be unpredictable
Properly designed synchronous circuits guarantee that
D is stable during aperture
However many systems must interface with data
coming from source are not synchronized to same clock
Lecture by R. Sivarajan, AP/ECE/APEC

Contd
Synchronizer
circuit accepts an input that can
change at arbitrary time and produce an output aligned
to synchronizers clock
Because input can change during synchronizers
aperture, synchronizer has nonzero probability of
producing metastable output

Lecture by R. Sivarajan, AP/ECE/APEC

Metastability
Latch
bistable device
It has 2 stable state 0 and 1
Under right condition, latch enter a metastable state in
which output at an indeterminate level between 0 and 1
Figure below shows the simple model for a static latch
consisting of 2 switches and 2 inverters

Lecture by R. Sivarajan, AP/ECE/APEC

Contd
While latch transparent, sample switch closed and hold
switch opened
While latch opaque, sample switch opened and hold
switch closed
Figure below shows DC transfer characteristics of the 2
inverters

Lecture by R. Sivarajan, AP/ECE/APEC

Contd

Lecture by R. Sivarajan, AP/ECE/APEC

Contd
Because A=B when latch is opaque, stable states are
A=B=0 and A=B=VDD
Metastable state is A=B=Vm, where Vm is not a legal
logic level
This point is called metastable because voltages are self
consistent and remain there indefinitely

Lecture by R. Sivarajan, AP/ECE/APEC

Simple
Synchronizer
Accepts input D and clock
Produces output Q that ought to be valid some bounded
delay after clock
Synchronizer has an aperture defined by setup and
hold time around rising edge of clock
If D stable during aperture, Q=D
If D changes during aperture, Q chosen arbitrary
Impossible to build perfect synchronizer because
duration of metastability can be unbounded

Lecture by R. Sivarajan, AP/ECE/APEC

Contd
Figure below shows a simple synchronizer built from
pair of flip flops

Lecture by R. Sivarajan, AP/ECE/APEC

Contd
F1 samples D
Output X be metastable for some time, but settle to a
good level with high probability if we wait long enough
F2 samples X and produces output Q that should be
valid logic level and be aligned with a clock
Synchronizer has a latency of one clock cycle Tc
It can fail if X has not settled to a valid level by a setup
time before second clock edge

Lecture by R. Sivarajan, AP/ECE/APEC

10

Contd

Lecture by R. Sivarajan, AP/ECE/APEC

11

Contd

Lecture by R. Sivarajan, AP/ECE/APEC

12