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Product Preview
This heading on a data sheet indicates that the device is in the
formative stages or in design (under development). The disclaimer
at the bottom of the first page reads: This document contains
information on a product under development. Motorola reserves the
right to change or discontinue this product without notice.
Advance Information
This heading on a data sheet indicates that the device is in sampling,
pre-production, or first production stages. The disclaimer at the
bottom of the first page reads: This document contains information
on a new product. Specifications and information herein are subject
to change without notice.
Fully Released
A fully released data sheet contains neither a classification heading
nor a disclaimer at the bottom of the first page. This document
contains information on a product in full production. Guaranteed
limits will not be changed without written notice to your Motorola
Semiconductor Sales Office.
The data sheets contained in this book were the most current available as of the date
of publication, July 1996.
A more current version of data sheets designated Product Preview or Advance
Information may be available.
General Information
ECLinPS, ECLinPS Lite, MOSAIC, MECL 10K and MECL 10H are trademarks of Motorola Inc.
The brands or product names mentioned are trademarks or registered trademarks of their respective holders.
Suggested References:
Low Voltage ECLinPS SPICE Modeling Kit, Motorola Inc., 1996. Stock code AN1560/D.
Motorola MECL Device Data Book, Motorola Inc., 1993. Stock code DL122/D.
F100K ECL Data Book, Fairchild Camera and Instrument Corp.
Motorola MECL System Design Handbook, second edition. Motorola Inc., 1983. Stock code HB205/D.
Signetics ECL 10K/100K Data Manual.
ii
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes
no warranty, representation or guarantee regarding the suitability of its products for any particular purpose,
nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical
parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating parameters, including Typicals must
be validated for each customer application by customers technical experts. Motorola does not convey any
license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could
create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products
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employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent
regarding the design or manufacture of the part. Motorola and
are registered trademarks of Motorola, Inc.
Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Printed in U.S.A.
iii
CONTENTS
MC10E411 . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC10E416/MC100E416 . . . . . . . . . . . . . . .
MC10E431/MC100E431 . . . . . . . . . . . . . . .
MC10E445/MC100E445 . . . . . . . . . . . . . . .
MC10E446/MC100E446 . . . . . . . . . . . . . . .
MC10E451/MC100E451 . . . . . . . . . . . . . . .
MC10E452/MC100E452 . . . . . . . . . . . . . . .
MC10E457/MC100E457 . . . . . . . . . . . . . . .
MC10E1651 . . . . . . . . . . . . . . . . . . . . . . . . . .
MC10E1652 . . . . . . . . . . . . . . . . . . . . . . . . . .
Ch 1. General Information
Numeric Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . 13
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Family Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Electrical Characteristics . . . . . . . . . . . . . . . . . . . 110
Engineering Evaluation Board . . . . . . . . . . . . . . 115
2189
2193
2197
2199
2205
2209
2211
2213
2216
2220
iv
CONTENTS
Ch 4. Low Voltage ECLinPS Data Sheets
MC100LVE111 . . . . . . . . . . . . . . . . . . . . . . . . . . 42
MC100LVE164 . . . . . . . . . . . . . . . . . . . . . . . . . 47
MC100LVE210/MC10E210 . . . . . . . . . . . . . . 411
MC100LVE222 . . . . . . . . . . . . . . . . . . . . . . . . 417
MC100LVE310/MC10E310 . . . . . . . . . . . . . . 422
MC100LVEL11 . . . . . . . . . . . . . . . . . . . . . . . . . 428
MC100LVEL13/MC100EL13 . . . . . . . . . . . . . 431
MC100LVEL14/MC100EL14 . . . . . . . . . . . . . 434
MC100LVEL16 . . . . . . . . . . . . . . . . . . . . . . . . 438
MC100LVEL17/MC100EL17 . . . . . . . . . . . . . 440
MC100LVEL29/MC100EL29 . . . . . . . . . . . . . 443
MC100LVEL30/MC100EL30 . . . . . . . . . . . . . 445
MC100LVEL32 . . . . . . . . . . . . . . . . . . . . . . . . 447
MC100LVEL38/MC100EL38 . . . . . . . . . . . . . 449
MC100LVEL39/MC100EL39 . . . . . . . . . . . . . 453
MC100LVEL51 . . . . . . . . . . . . . . . . . . . . . . . . 456
MC100LVEL56/MC100EL56 . . . . . . . . . . . . . 458
MC100LVEL59/MC100EL59 . . . . . . . . . . . . . 461
MC100LVEL90/MC100EL90 . . . . . . . . . . . . . 463
MC100LVEL91/MC100EL91 . . . . . . . . . . . . . 466
MC100LVEL92 . . . . . . . . . . . . . . . . . . . . . . . . 469
Application Notes:
ECLinPS Circuit Performance at
Standard VIH Levels (AN1404) . . . . . . . . 545
ECL Clock Distribution
Techniques (AN1405) . . . . . . . . . . . . . . . . 553
Designing With PECL (AN1406) . . . . . . . . . . 560
ECLinPS I/O SPICE Kit (AN1503) . . . . . . . . 569
Metastability and the ECLinPS
Family (AN1504) . . . . . . . . . . . . . . . . . . . . 579
Interfacing Between LVDS and
ECL (AN1568) . . . . . . . . . . . . . . . . . . . . . . 588
Distributor and Worldwide Sales Offices . . NO TAG
vi
General Information
This section contains a numerical listing of
ECLinPS and ECLinPS Lite family functions, a
technical overview of the ECLinPS amd ECLinPS
Lite families and an outline of their electrical
characteristics. In addition, this section outlines the
procedures and philosophies used to AC test the
families. (MC10E/EL series devices are compatible
with the MECL 10H family. MC100E/EL series are
compatible with 100K ECL.)
CONTENTS
Numeric Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . 13
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Family Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Electrical Characteristics . . . . . . . . . . . . . . . . . . . 110
Engineering Evaluation Board . . . . . . . . . . . . . . . 115
11
MOTOROLA
MOTOROLA
Numeric Index
SEMICONDUCTOR GENERAL INFORMATION
SECTION 1
Numeric Index
ECLinPS Devices
MC10/
MC100
E016
E101
E104
E107
E111
E112
E116
E122
E131
E136
E137
E141
E142
E143
E150
E151
E154
E155
E156
E157
E158
E160
E163
E164
E166
E167
Function
8-Bit Synch Binary Counter
Quad 4-Input OR/NOR Gate
Quint 2-Input AND/NAND Gate
Quint 2-Input XOR/XNOR Gate
1:9 Differential Clock Driver
Quad Drive, Common Enable
Quint Diff Line Receiver
9-Bit Buffer
4-Bit D Flip-Flop
6-Bit Universal Counter
8-Bit Ripple Counter
8-Bit Universal Shift Register
9-Bit Shift Register
9-Bit Hold Register
6-Bit D Latch
6-Bit D Register
5-Bit 2:1 Mux Latch
6-Bit 2:1 Mux Latch
3-Bit 4:1 Mux Latch
Quad 2:1 Mux, Separate Selects
5-Bit 2:1 Multiplexer
12-Bit Parity Gen/Checker
2-Bit 8:1 Multiplexer
16:1 Multiplexer
9-Bit Magnitude Comparator
6-Bit 2:1 Mux Register
Page
23
211
215
219
223
228
232
236
240
242
251
256
260
264
268
272
276
280
284
288
292
296
2100
2104
2108
2112
MC10/
MC100
Function
Page
E171
E175
E193
E195
E196
E197*
E/LVE210[
E211
E212
E241
E256
E/LVE310[
E336
E337
E404
E411*
E416
E431
E445
E446
E451
E452
E457
E1651*
E1652*
2116
2120
2124
2128
2133
2138
411
2155
2162
2166
2170
422
2176
2180
2185
2189
2193
2197
2199
2205
2209
2211
2213
2216
2220
MOTOROLA
Function
4-Input OR/NOR
2-Input AND/NAND
2-Input Differential AND/NAND
2-Input XOR/XNOR
1:2 Differential Fanout Buffer
Low Impedance Driver
Dual 1:3 Fanout Buffer
1:5 Clock Distribution Chip
1:4 Clock Distribution Chip
Differential Line Receiver
Quad Differential Receiver
Dual Diff Data/Clock D FlipFlop SR
Triple D FlipFlop With Set & Reset
D Flip-Flop With Set and Reset
Integrated 2 Divider, Diff Input
Integrated 4 Divider, Diff Input
2, 4, 8 Clock Generation Chip
JK Flip-Flop
2, 4/6 Clock Generation Chip
2/4, 4/6 Clock Generation Chip
MC10/
MC100
Page
37
39
311
314
316
319
431
434
322
326
440
443
445
332
335
338
341
343
449
453
EL51
EL52
EL56**
EL57
EL58
EL59**
EL89*
EL90
EL91
ELT20
ELT21
ELT22
ELT23[
ELT24
ELT25
ELT26
ELT28
Function
D Flip-Flop w/ Reset and Diff Clock
D Flip-Flop w/ Diff Data and Clock
Dual Differential 2:1 Multiplexer
4:1 Differential Multiplexer
2:1 Multiplexer
Triple 2:1 Multiplexer
Coaxial Cable Driver
Triple ECL to PECL Translator
Triple PECL to ECL Translator
TTL to Differential PECL Translator
Differential PECL to TLL Translator
Dual TTL to Diff PECL Translator
Dual Diff PECL to TTL Translator
Dual TTL to Diff ECL Translator
Dual Diff ECL to TTL Translator
1:2 Fanout Diff PECL to TTL Trans
TTL to Diff PECL/Diff PECL to TTL
Page
347
349
458
352
354
461
356
463
466
361
363
365
367
369
371
373
374
12
Device Nomenclature
Low Voltage ECLinPS and ECLinPS Lite Devices
MC100
LVE111
LVE164
LVE210
LVE222
LVE310
LVEL11
LVEL13
LVEL14
LVEL16
LVEL17
LVEL29
Function
Page
MC100
42
47
411
417
422
428
431
434
438
440
443
Function
LVEL30
LVEL32
LVEL38
LVEL39
LVEL51
LVEL56
LVEL59
LVEL90
LVEL91
LVEL92
Page
445
447
449
453
456
458
461
463
466
469
SECTION 2
Device Nomenclature
ECLinPS, ECLinPS Lite
MC
WWW
XXX
YYY
ZZ
Package Type
FN = PLCC
D = Plastic SOIC
L = Ceramic DIP
P = Plastic DIP
Motorola
Circuit Identifier
MC = Fully Qualified Circuit
XC = Non Reliability Qualified
Function Type
YYY = 3-Digits for ECLinPS
YY= 2-Digits for ECLinPS Lite
Compatibility Identifier
10 = 10H Compatible (0 to +85C)
100 = 100K Compatible (0 to +85C)
SECTION 3
Selection Guide
Gates
Buffers
EL01
9-Bit Buffer
E101
EL04
EL15
E104
E/LVE111]
EL05
EL07
E107
E404
E/LVE210[
E/LVE310[
13
E122
EL/LVEL11]
E411*
EL/LVEL13[
EL12
E112
E212
MOTOROLA
Selection Guide
Parity Generator/Comparator
EL31
EL/LVEL29[
E131
Triple D
EL/LVEL30[
EL/LVEL51]
E160
E166
E193
E175
Line Receivers
E151
E451
EL/LVEL16]
E143
EL/LVEL17[
E431
E451
Single JK
EL35
E416
EL52
E452
Bus Transceivers
Latches
6-Bit D (Async Reset)
E150
E175
E116
E336
E337
Translators
Multiplexers
EL/LVEL90[
EL/LVEL91[
EL57
LVEL92[
EL58
ELT20
EL/LVEL56[
ELT21
EL/LVEL59[
ELT22
E158
ELT23[
E171
ELT24
E163
ELT25
E164
ELT26
E157
ELT28
E457
Miscellaneous
Mux-Latches
EL/LVEL32]
EL33
E154
E155
E156
EL/LVEL38[
E256
EL/LVEL39[
Mux-Registers
6-Bit 2:1 Mux-Register
E167
Counters
EL34
EL89*
E195
E196
E197*
E016
E445
E136
E446
E137
E1651*
E1652*
Shift Registers
8-Bit Shift Register (bidirectional)
E141
E241
E142
E143
E212
MOTOROLA
14
MOTOROLA
SECTION 4
Family Overview
Transmission Line Drive Capability
The low output impedance, high input impedance and
high current drive capability of ECL makes it an ideal
technology for driving transmission lines. Regardless of the
technology, as system speeds increase, interconnect
becomes more of a transmission line phenomenon. With
ECL no special line driving devices are necessary, as all
ECL devices are line drivers.
Introduction
Advances in bipolar processes led to a proliferation of very
high speed LSI and VLSI gate arrays in high end computer
applications. The advent of these high speed arrays created
a need for a high speed logic family to tie or glue them
together. Because arrays have a finite amount of circuitry and
I/O pins, glue functions which are sensitive to either of these
parameters may be better performed off of the array. In
addition glue functions which require very tight skew control
may be difficult to perform on an array due to the inherent skew
of the large packages associated with large gate arrays.
Therefore although the trend is to push more and more of the
logic onto the array, there are design constraints which make
performing some of the logic, such as clock distribution,
multiplexing, decoding, latching, memory addressing and
translating, in glue an attractive alternative.
The high end computer segment is not the only market
segment pushing for higher performance logic parts. ATE,
instrumentation and communication designs can have data
rate requirements ranging from 300MHz to as high as 2.5GHz.
Because large high speed arrays do not always lend
themselves to passing high frequency signals on and off chip,
portions of the designs must be realized with discrete logic.
The current bipolar logic families are not capable of operating
at these high frequencies.
To answer the call for a very high speed bipolar logic family
Motorola designed and produced the ECLinPS* (ECL in Pico
Seconds) logic family. The family is designed to meet the most
stringent of system requirements in speed, skew and board
density as well as maintaining compatibility to existing ECL
families.
Complimentary Outputs
Complimentary outputs are available on many functions
with equal propagation delays between the two paths. This
alleviates the need for external inverters and saves system
power and board space while maintaining exceptional
system timing.
* Any reference to ECLinPS in this section includes the ECLinPS Lite and Low Voltage ECLinPS families.
15
MOTOROLA
Family Overview
Internal Differential Interconnect
Input Buffers
To minimize propagation delays in a system environment,
inputs with a large internal fanout are buffered to minimize the
loading capacitance on the transmission line.
Universal Compatibility
Input and output pins have been laid out in a flow through
pattern with the inputs on one side of the package and the
outputs on the other. This flow through pattern helps to simplify
the PC board layout operation.
Multiple VCCO pins
To minimize the noise generated in simultaneous
switching situations, a minimum of three single-ended
outputs per VCCO has been employed in the family.
Optimum placement of these VCCOs also results in superior
output-to-output skew.
MOTOROLA
16
Family Overview
The 28-pin PLCC package emerged as the clear favorite
both internally and with the high speed market in general. The
package offers a quad layout to minimize both lead lengths
and lead length differences. As a result, the parasitics and
delays of the package are very well suited for a high speed
logic family. In addition, the nearly matched lead lengths allow
for tighter skew among similar paths through the chip.
The board density potential of the PLCC is also attractive in
that it allows for a nearly 100% reduction in board space when
compared to the DIP alternative. The package is
approximately a half inch square with 50 mil spaced J-bend
leads. More detailed measurements can be found in the
package section of this data book. The J-bend leads provide
a smaller footprint than a gull wing package and propose fewer
temperature expansion coefficient mismatch problems than
the leadless alternative.
Thermally, the standard PLCC exhibits a JA of 43.5C per
watt at 500lfpm air flow. With this thermal resistance most
28-pin functions can be implemented with the MOSAIC III
process without encountering any severe thermal problems.
For more details on thermal issues of the ECLinPS family refer
to the thermal section of this data book.
Abbreviation Definitions
The following is a list of abbreviations found in this data book
and a brief definition of each.
Summary
Summarizing the above information, in general, the two
ECL design standards, although differing somewhat in DC
parameters, are nearly identical when one compares the AC
performance for a given device. There may be very small
differences in the AC measurements due to the slightly
smaller output swing of the 100E device. However, these
differences are negligible when compared to the absolute
value of the measurements. Therefore, from an AC
stand-point, there is no real advantage in using one standard
over the other, thus removing AC performance as a decision
variable in high-speed system design.
Current
ICC
IEE
IIL
IINH
IOUT
Packaging
During the definition phase of the ECLinPS family, much
attention was placed on the identification of a suitable
package for the family. The package had to meet the criteria
of minimum parasitics and propagation delays along with an
attractive I/O vs board space relationship. Although the DIP
package offered a level of familiarity and convenience, the
performance of the package with a very high speed logic
family was inadequate. In addition to the obvious parasitics
and board space problems, the propagation delays through
the DIP package were nearly twice as long as the delay
through the silicon.
Voltage
17
VBB
VBE
VCB
MOTOROLA
Family Overview
VCC
VCUT
VCCO
VSUP
VEE
Timing Parameters
tR
tF
TPD
xpt
VIH
VIH max
VIH min
VIL
VIL max
TPLH
TPHL
fMAX
fCOUNT
fSHIFT
tSKEW
ts
tH
tRR
tw min
VIL min
VOH
VOHA
VOH max
VOH min
VOL
VOLA
VOL max
VOL min
VTT
VPP
VCMR
MOTOROLA
18
Family Overview
Temperature
Miscellaneous
TSTG
DUT
CIN
TJ
ZIN
COUT
TA
ZOUT
JA
PD
RL
Load resistance.
RT
RP
PUT
SMA
JC
CA
lfpm
19
MOTOROLA
MOTOROLA
SECTION 5
Electrical Characteristics
0.8
1.0
1.48, 0.98
1.13, 0.98
1.2
25C
1.4
1.6
1.13, 1.63
1.48, 1.63
1.8
OR
NOR
VEE = 4.94V TO 5.46V
0
SLOPE = 6 8
2.0
1.8
1.6
1.4
1.2
1.0 0.8
10
0.8
15
1.0
OUTPUT VOLTAGE (V)
DC Characteristics
100 TO 2.0V
20
25 TO 2.0V
25
VOL
50 TO 2.0V
30
TA = 25C
35
VOH
25C
75C
0C
1.2
1.4
1.6
1.8
OR
40
2.0
1.75
1.5
1.25
2.0
1.8
NOR
1.6
1.4
1.2
1.0
0.8
* Any reference to ECLinPS in this section includes the ECLinPS Lite and Low Voltage ECLinPS families.
MOTOROLA
110
Electrical Characteristics
high and low output level tracking rates. Table 2.1 also
outlines the temperature tracking behavior of a 10E VBB
switching reference.
10E
min
typ
max
VOH/T (mV/C)
1.1
1.2
1.4
VOL/T (mV/C)
0.4
0.6
VBB/T (mV/C)
0.6
0.8
1.0
VOH/VEE (mV/V)
20
VOL/VEE (mV/V)
10
30
VBB/VEE (mV/V)
20
min
typ
max
VOH/T (mV/C)
0.15
0.15
VOL/T (mV/C)
0.30
0.30
VBB/T (mV/C)
0.20
0.20
VOH/VEE (mV/V)
20
VOL/VEE (mV/V)
10
30
VBB/VEE (mV/V)
20
100E
10E
0.8
NMHIGH (mV)
NMLOW (mV)
100E
min
typ
min
typ
150
150
240
280
140
145
210
230
1.0
1.165, 1.035
1.475, 1.035
1.2
0C to 85C
1.4
1.165, 1.610
1.475, 1.610
1.6
1.8
OR
NOR
VEE = 4.20V TO 5.46V
2.0
1.8
1.6
1.4
1.2
1.0 0.8
111
MOTOROLA
Electrical Characteristics
AC Characteristics
Parameter Definitions
The device data sheets in Section 3 contain specifications
for the propagation delays and rise/fall times for each of the
devices in the ECLinPS family. In addition, where applicable,
skew, setup/hold, maximum toggle frequencies (fMAX), reset
recovery and minimum pulse width specifications are
included. The waveforms and terminologies used in
describing the propagation delays and rise/fall times of the
ECLinPS family are depicted in Figure 2.4 below.
80%
20%
Vout
tf
tr
50%
Skew Times
In the design of high speed systems skew plays nearly as
important a role as propagation delay. The majority of the
devices in the ECLinPS family have the skew between outputs
specified. This skew specification represents the typical
difference between the delays of similar paths on a single chip.
No maximum value for skew is specified due to the difficulty
in the production testing of this parameter. The user is
encouraged to contact an ECLinPS application engineer to
obtain actual evaluation data if this parameter is critical in their
designs.
Set-Up and Hold Times
Motorola defines the setup time of a device as the minimum
time, prior to the transition of the clock, that an input must be
stable to ensure that the device operates properly. The hold
time, on the other hand, is defined as the minimum time that
an input must remain stable after the transition of the clock to
ensure that the device operates properly. Figure 2.5 illustrates
the way in which Motorola defines setup and hold times.
Vin
50%
Tpd + +
Tpd
Data
ts
th
50%
Vout
50%
Tpd
Vout
Vin
xpt
Vin
Vout
Tpd
Vout
xpt
Vout
DIFFERENTIAL PROPAGATION DELAY
MOTOROLA
Tpd + +
Release Times
Release times are defined as the minimum amount of time
an input must wait to be clocked after an enable, master reset
or set signal is deactivated to ensure proper operation.
Because more times than not this specification is in reference
to a master reset operation, this parameter is often called reset
recovery time. Figure 2.6 illustrates the definition of release
time in the Motorola data sheets.
112
Electrical Characteristics
50%
Master Reset
trr
Data
50%
Clock
Clock
fMAX Measurement
In general fMAX is measured in the manner shown in Figure
2.7 with the fail criterion being either a swing of 600mV or less,
or a miscount. However, in some cases, the feedback method
of testing can lead to a pessimistic value of fMAX because the
feedback path delay is such that the setup times of the device
are violated. If this is the case, it is necessary to have two free
running signal generators to ensure that the setup times are
observed. This parameter, along with fSHIFT and fCOUNT,
represents the maximum frequency at which a particular flip
flop, shift register or counter can be clocked with the divide,
shift or count operation guaranteed. This number is generated
from worst case operating conditions, thus, under nominal
operating conditions, the maximum toggle frequency is higher.
CHANNEL A
50 COAX
50
PULSE
GENERATOR
DEVICE
UNDER
TEST
50 COAX
VEE
VCCO**
(+2.0V)
OSCILLOSCOPE
0.01F
VCC
(+2.0V)
CHANNEL B
50 W COAX
0.01F
20F
20F
50
3.2V*
* VEE = 3.2V FOR 10Exxx, 2.5V FOR 100Exxx
** MULTIPLE VCCOs EXIST ON MOST PARTS
113
MOTOROLA
Electrical Characteristics
To further standardize testing, any unused outputs should
be loaded with 50 to ground.
Because the power supplies are shifted, the input levels
must also be shifted by an equal amount. Table 2.3 gives the
typical input levels for the ECLinPS family and their
corresponding +2.0V shifted levels.
10Exxx
Typical
Shifted
VIL
1.75V
+ 0.25V
VIH
0.90V
+1.10V
100Exxx
Typical
Shifted
VIL
1.70V
+ 0.30V
VIH
0.95V
+1.05V
MOTOROLA
114
MOTOROLA
SECTION 6
Engineering Evaluation Board
for 28-Pin ECL Devices in the PLCC Package
Part # ECLPSBD28
DESCRIPTION
This board is designed to provide a low cost characterization tool for evaluating ECL devices in the ECLinPS Product Family.
The board provides a high bandwidth 50 controlled impedance environment. The board is universal and can be configured by
the user for any of the 28-pin PLCC devices in the family depending on the input, output, and power pinout layout of the device.
The table below indicates common input/output/power devices.
Group
Base Device
CONF1
CONF2
CONF3
CONF4
CONF5
CONF6
CONF7
CONF8
CONF9
CONF10
CONF11
CONF12
CONF13
CONF14
CONF15
E196
E142
E337
E212
E156
E158
E154
E101
E112
E431
E111
E164
E451
E163
E193
E195
E016,E141,E143,E241
E336
E104,E107,E150,E151
E155,E167,E171,E256
E116,E122,E175,E416
E452
E131,E157,E404
E457
E160
E166
The board is designed to test devices using the fly-by (Kelvin contact) test method, therefore one input force trace and one
input sense trace exist for each input pin. This allows termination of the input and output signals into the highly accurate 50 ohm
impedance of an oscilloscope. The layout is engineered to have equal length traces from the device under test (DUT) socket to
the sense outputs which simplifies the calibration requirements for accurate AC measurements.
The kit provides a printed circuit board with an attached surface mount socket as well as assembly instructions. For superior
impedance control from the cable to the board, Motorola recommends the use of SMA coaxial connectors.
115
MOTOROLA
C. 10 F
CAPACITORS
LOCATIONS
A. LOCATION OF
SENSE RING
FOR SMAs
B. VIAS TO THE
POWER PLANES
MOTOROLA
116
Group
Part(s)
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
CONF1
E196
VEE
VB
NC
NC
VCC
CONF2
E142
VEE
VCC
VCC
CONF3
E337
VEE
VCC
NC
NC
VCC
CONF4
E212
VEE
VCC
VCC
CONF5
E156
VEE
VCC
VCC
CONF6
E158
VEE
I/VB
VCC
VCC
VCC
CONF7
E154
VEE
I/VB
VCC
CONF8
E101
VEE
VCC
CONF9
E112
VEE
NC
VCC
VCC
CONF10
E431
VEE
I/VB
I/VB
VCC
CONF11
E111
VCC
VB
NC
VCC
CONF12
E164
VEE
VCC
CONF13
E451
VEE
NC
VCC
VCC
CONF14
E163
E193
VEE
VEE
CONF15
VCC
VCC
VCC
P20
P21
P22
P23
P24
P25
P26
P27
P28
# of
Connectors
NC
35
VCC
37
NC
VCC
37
VCC
33
VCC
VCC
40
VCC
VCC
VCC
32
E154
VCC
VCC
38
E101
VCC
VCC
40
E112
VCC
VCC
VCC
26
E431
VCC
I/VB
I/VB
44
E111
VCC
VCC
VEE
25
E164
VCC
VCC
44
E451
VCC
VCC
VB
37
E163
NC
42
VCC
O
VCC
VCC
E193
VCC
38
Part(s)
(contd)
P15
P16
P17
P18
P19
E196
VCC
VCC
E142
VCC
NC
E337
VCC
E212
VCC
E156
E158
KEY:
I
O
VEE
VCC
NC
VB
designates an input
designates an output
designates the lower voltage rail
designates the upper voltage rail
designates a no connect
designates VBB output which should
not be terminated into 50 ohms
117
MOTOROLA
Table 2 indicates the number of SMA connectors needed to populate an evaluation board for a given configuration. Depending on
the device and the parameters of interest, it may not be necessary to install the full complement of SMA connectors. For example,
some devices have two clock inputs or common clocks and individual clocks. Figure 1 is the frontview of the ECLinPS evaluation
board. Item A points to the inner ring which connects to the sense traces of the DUT. The outer ring connects to the force traces. An
input requires one SMA connector for the force and one SMA connector for the sense, while an output only requires a connection to
the sense trace. Insert all the SMA connectors into the board and solder to the board. A simple assembly technique is to place a stiff
piece of cardboard (8 7 or larger) on top of all the connectors and hold the board and cardboard together. Invert the board, place
on a level surface, and all the connectors will be seated properly and can be soldered in place.
II. Connecting Power Planes to DUT Socket
There are four voltage planes on the ECLPSBD28. One is dedicated to ground and the other three, B1, B2, B3, are uncommitted.
These planes are accessible through a power connection and sets of four vias that are adjacent to each sense trace. This is
identified as Item B in Figure 1. For standard parts, B1 can be assigned VCC, B2 can be assigned to VEE, and B3 can be assigned to
ground. Table 2 indicates which pins need to be connected to the various supply voltages. On the front side of the board, solder a
jumper wire from the closest VEE or VCC via to the sense trace for each VCC, VCCO, and VEE pin. Near the DUT there are sets of
ground/bias plane vias that accommodate power supply decoupling capacitors. These are identified as Item C. On the front side of
the board install 10 F capacitors and on the back side install a 0.01 F high frequency capacitor in parallel to decouple the VEE and
VCC planes.
III. Cutting Force Traces for Outputs
Because of the design of the board, all force traces for output pins will appear as transmission line stubs connected to the output
pin. On the back side of the board, cut the force traces associated with the outputs using a razor blade knife. It is important to cut
the trace very close to the DUT area to minimize the stub length. Also cut the force traces that are connected to VCC, VCCO, and
VEE pins.
IV. Installing the Chip Capacitors for the VCC/VCCO Pins
In the kit are 0.01 F chip capacitors for use in decoupling the VCC and VCCO pins to the ground plane. This is critical because the
power pins are not directly connected to the VCC plane as in an actual board layout. On the back side of the board beneath the DUT
socket are pads for each pin which allow connection of chip capacitors to the center island (GND) for each VCC and VCCO pin. Stand
the chip capacitors on edge when soldering them in place so that adjacent pins are not shorted together.
MOTOROLA
118
EF Johnson
299 Johnson Ave. P.O. Box 1249
Waseca, Minnesota 56093
(800) 247-8343 or (507) 835-6222
119
MOTOROLA
MOTOROLA
120
21
MOTOROLA
Symbol
Rating
Unit
VEE
8 to 0
Vdc
VI
0 to 6V
Vdc
Iout
50
100
mA
TA
Operating Range2
C
0 to + 85
0 to + 85
VEE
5.7 to 4.2
Characteristic
25C
75C
85C
Min
Max
Min
Max
Min
Max
Min
Max
Unit
VOH
1020
840
980
810
920
735
910
720
mV
VOL
1950
1630
1950
1630
1950
1600
1950
1595
mV
VIH
1170
840
1130
810
1070
735
1060
720
mV
VIL
1950
1480
1950
1480
1950
1450
1950
1445
mV
IIL
0.5
0.5
0.3
0.3
1. 10E series circuits are designed to meet the dc specifications shown in the table, after thermal equilibrium has been established. The circuit is
in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. Outputs are terminated through
a 50 resistor to 2.0 volts, except bus outputs which, where specified, are terminated into 25.
Characteristic
Min
Typ
Max
Unit
Conditions
VOH
1025
955
880
mV
VIN = VIH(max)
VOL
1810
1705
1620
mV
or VIL(min)
Loading with
VOHA
1035
50 to 2.0V
VOLA
VIH
VIL
IIL
mV
VIN = VIH(min)
1610
mV
or VIL(max)
1165
880
mV
1810
1475
mV
0.5
VIN = VIL(min)
This table replaces the three tables at different supply voltages in the previous edition and in ECL 100K literature. The same DC parametric values
at VEE = 4.5V now apply across the full VEE range of 4.2 to 5.46V.
MOTOROLA
22
MOTOROLA
MC10E016
MC100E016
8-BIT SYNCHRONOUS
BINARY UP COUNTER
8-Bit
Fully Synchronous Counting and TC Generation
Asynchronous Master Reset
Extended 100E VEE Range of 4.2V to 5.46V
75k Input Pulldown Resistors
FUNCTION TABLE
Pinout: 28-Lead PLCC (Top View)
PE
CE
P7
P6
P5
VCCO
TC
25
24
23
22
21
20
19
MR
26
18
Q7
CLK
27
17
Q6
TCLD
28
16
VCC
VEE
15
Q5
NC
14
VCCO
P0
13
Q4
P1
12
Q3
10
11
P2
P3
P4
VCCO
Q0
Q1
Q2
CE
PE
TCLD
MR
CLK
Function
X
L
L
H
X
X
L
H
H
H
X
X
X
L
H
X
X
X
L
L
L
L
L
H
Z
Z
Z
Z
ZZ
X
PIN NAMES
Pin
P0 P7
Q0 Q7
CE
PE
MR
CLK
TC
TCLD
Function
Parallel Data (Preset) Inputs
Data Outputs
Count Enable Control Input
Parallel Load Enable Control Input
Master Reset
Clock
Terminal Count Output
TC-Load Control Input
* All VCC and VCCO pins are tied together on the die.
12/93
23
REV 2
MC10E016 MC100E016
Q1
Q0
Q7
PE
TCLD
Q0M
MASTER
CE
Q0M
SLAVE
Q0
CE
CE
Q
Q1 0
Q2
Q3
Q4
Q5
Q6
P7
BIT 1
BIT 0
PO
P1
BIT 7
MR
CLK
BITS 26
TC
Note that this diagram is provided for understanding of logic operation only.
It should not be used for propagation delays as many gate functions are achieved internally without incurring a full gate delay.
MOTOROLA
24
MC10E016 MC100E016
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
Characteristic
IIH
IEE
min
typ
25C
max
min
typ
150
85C
max
min
typ
150
max
Unit
150
Condition
mA
151
151
181
181
151
151
181
181
151
174
181
208
Characteristic
min
typ
fCOUNT
700
900
tPLH
tPHL
600
600
550
625
725
775
775
775
ts
Setup Time
Pn
CE
PE
TCLD
150
600
600
500
Hold Time
Pn
CE
PE
TCLD
tRR
tPW
th
tr
tf
25C
min
typ
700
900
600
600
550
625
725
775
775
775
30
400
400
300
150
600
600
500
350
0
0
100
100
400
400
300
900
700
400
Rise/Fall Times
20 - 80%
300
max
85C
max
min
typ
700
900
600
600
550
625
725
775
775
775
30
400
400
300
150
600
600
500
30
400
400
300
350
0
0
100
100
400
400
300
350
0
0
100
100
400
400
300
900
700
900
700
max
Unit
Condition
MHz
ps
1000
1000
900
1000
1000
1000
900
1000
1000
1000
1050
1000
ps
ps
ps
400
400
ps
510
800
300
25
510
800
300
510
MOTOROLA
MC10E016 MC100E016
FUNCTION TABLE
Function
Load
Count
Load
Hold
Load On
Terminal
Count
Reset
PE
CE
MR
TCLD
CLK
P7-P4
P3
P2
P1
P0
Q7-Q4
Q3
Q2
Q1
Q0
TC
L
H
H
H
H
L
H
H
H
H
H
H
H
H
X
X
L
L
L
L
X
H
H
L
L
L
L
L
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
L
L
L
L
X
X
X
H
H
H
H
H
H
X
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
X
H
X
X
X
X
H
X
X
H
H
H
H
H
H
X
H
X
X
X
X
H
X
X
L
L
L
L
L
L
X
H
X
X
X
X
H
X
X
H
H
H
H
H
H
X
L
X
X
X
X
L
X
X
H
H
H
H
H
H
X
L
X
X
X
X
L
X
X
L
L
L
L
L
L
X
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
L
L
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
L
L
L
L
L
H
H
H
H
L
L
L
H
L
H
L
L
L
L
H
L
H
L
H
L
L
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
Applications Information
Cascading Multiple E016 Devices
disabling the count operation of the more significant counters
and placing them back into hold modes. Therefore, for an
E016 in the chain to count, all of the lower order terminal count
outputs must be in the low state. The bit width of the counter
can be increased or decreased by simply adding or
subtracting E016 devices from Figure 1 and maintaining the
logic pattern illustrated in the same figure.
The maximum frequency of operation for the cascaded
counter chain is set by the propagation delay of the TC output
and the necessary setup time of the CE input and the
propagation delay through the OR gate controlling it (for 16-bit
counters the limitation is only the TC propagation delay and
the CE setup time). Figure 1 shows EL01 gates used to control
the count enable inputs, however, if the frequency of operation
is lower a slower, ECL OR gate can be used. Using the worst
case guarantees for these parameters from the ECLinPS data
book, the maximum count frequency for a greater than 16-bit
counter is 500MHz and that for a 16-bit counter is 625MHz.
LO
CE
Q0 > Q7
PE
CE
PE
TC
CLK
Q0 > Q7
PE
CLK
TC
P0 > P7
PE
E016
MSB
TC
CLK
TC
EL01
EL01
P0 > P7
CE
E016
E016
E016
LSB
CLK
CE
Q0 > Q7
P0 > P7
P0 > P7
CLOCK
MOTOROLA
26
MC10E016 MC100E016
Applications Information (continued)
where:
P0 = LSB and P7 = MSB
Programmable Divider
PE
CE
TCLD
P7
P6
P5
P4
P3
P2
P1
P0
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Load
1001 0000
1001 0001
Ratio
P7
P6
P5
P4
P3
P2
P1
P0
2
3
4
5
112
113
114
254
255
256
H
H
H
H
H
H
H
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
L
L
L
L
L
H
H
H
H
L
H
H
L
L
L
H
H
H
L
L
H
H
L
L
L
H
L
L
H
L
H
H
H
L
L
L
H
L
H
L
H
L
L
H
L
full clock period. For even divide ratios, twice the desired
divide ratio can be loaded into the E016 and the TC output can
feed the clock input of a toggle flip flop to create a signal
divided as desired with a 50% duty cycle.
A single E016 can be used to divide by any ratio from 2 to
256 inclusive. If divide ratios of greater than 256 are needed
multiple E016s can be cascaded in a manner similar to that
already discussed. When E016s are cascaded to build larger
dividers the TCLD pin will no longer provide a means for
loading on terminal count. Because one does not want to
reload the counters until all of the devices in the chain have
reached terminal count, external gating of the TC pins must be
used for multiple E016 divider chains.
TC
CLK
Q7
Divide
1111 1100
1111 1101
1111 1110
1111 1111
Load
Clock
PE
TC
DIVIDE BY 113
27
MOTOROLA
MC10E016 MC100E016
Applications Information (continued)
EL01
Q0 > Q7
LO
CE
PE
CE
Q0 > Q7
PE
CE
E016
E016
LSB
CLK
Q0 > Q7
TC
CLK
PE
CE
E016
TC
CLK
PO > P7
PE
E016
MSB
TC
EL01
PO > P7
Q0 > Q7
PO > P7
CLK
EL01
TC
PO > P7
CLOCK
MOTOROLA
28
MOTOROLA
MC10E101
MC100E101
QUAD 4-INPUT
OR/NOR GATE
D3b
D3c
D3d VCCO Q3
Q3
25
24
23
22
19
21
20
D2d
26
18
Q2
D2c
27
17
Q2
D2b
28
16
VCC
VEE
15
Q1
D2a
14
Q1
D1d
13
Q0
D1c
12
Q0
D1b
D1a
D0d
D0c
D0b
10
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
11
D0a VCCO
* All VCC and VCCO pins are tied together on the die.
LOGIC DIAGRAM
D0a
D0b
PIN NAMES
Q0
D0c
D0d
Q0
D1a
D1b
D1c
Q1
Function
Pin
D0a D3d
Data Inputs
Q0 Q3
True Outputs
Q0 Q3
Inverting Outputs
Q1
D1d
D2a
D2b
Q2
D2c
D2d
Q2
D3a
D3b
Q3
D3c
D3d
Q3
12/93
29
REV 2
MC10E101 MC100E101
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
Characteristic
IIH
IEE
min
typ
25C
max
min
typ
150
85C
max
min
typ
150
max
Unit
150
Condition
mA
30
30
36
36
30
30
36
36
30
35
36
42
Characteristic
tPLH
tPHL
tSKEW
tSKEW
Within-Device Skew
Within-Gate Skew
tr
tf
Rise/Fall Time
20 - 80%
25C
85C
min
typ
max
min
typ
max
min
typ
max
200
350
500
200
350
500
200
350
500
Unit
Condition
ps
50
25
50
25
50
25
ps
1
2
ps
300
380
575
300
380
575
300
380
575
MOTOROLA
210
MOTOROLA
MC10E104
MC100E104
QUINT 2-INPUT
AND/NAND GATE
D4b
D4a
NC
VCCO
25
24
23
22
21
20
19
D3b
26
18
Q4
D2a
27
17
Q4
D2b
28
16
VCC
VEE
15
Q3
D1a
14
Q3
D1b
13
Q2
D0a
12
Q2
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
LOGIC DIAGRAM
5
D0b VCCO
10
11
Q0
Q0
Q1
Q1
VCCO
* All VCC and VCCO pins are tied together on the die.
PIN NAMES
Pin
D0a D4b
Q0 Q4
Q0 Q4
F
F
D0a
Q0
D0b
Q0
D1a
Q1
D1b
Q1
D2a
Q2
D2b
Q2
D3a
Q3
D3b
Q3
D4a
Q4
D4b
Q4
Function
Data Inputs
AND Outputs
NAND Outputs
OR Output
NOR Output
FUNCTION OUTPUTS
F=
12/93
211
REV 2
MC10E104 MC100E104
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
Characteristic
IIH
IEE
min
typ
25C
max
min
typ
85C
max
200
min
typ
200
max
Unit
200
Condition
mA
38
38
46
46
38
38
46
46
38
44
46
53
Characteristic
tPLH
tPHL
tSKEW
Within-Device Skew
D to Q
tr
tf
Rise/Fall Times
20 - 80%
Q
F
25C
85C
min
typ
max
min
typ
max
min
typ
max
225
500
385
725
600
1000
225
500
385
725
600
1000
225
500
385
725
600
1000
Unit
Condition
ps
ps
75
75
75
1
ps
275
300
425
475
700
700
275
300
425
475
700
700
275
300
425
475
700
700
MOTOROLA
212
MOTOROLA
MC10E107
MC100E107
QUINT 2-INPUT
XOR/XNOR GATE
D4b
D4a
NC
VCCO
25
24
23
22
21
20
19
D3b
26
18
Q4
D2a
27
17
Q4
D2b
28
16
VCC
VEE
15
Q3
D1a
14
Q3
D1b
13
Q2
D0a
12
Q2
D0b VCCO
10
11
Q0
Q0
Q1
Q1
VCCO
* All VCC and VCCO pins are tied together on the die.
PIN NAMES
Pin
Function
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
LOGIC DIAGRAM
D0a
Q0
D0b
Q0
D1a
Q1
D1b
Q1
D0a D4b
Data Inputs
Q0 Q4
XOR Outputs
D2a
Q2
Q0 Q4
XNOR Outputs
D2b
Q2
OR Output
NOR Output
D3a
Q3
D3b
Q3
D4a
Q4
D4b
Q4
FUNCTION OUTPUTS
F = (D0a D0b) + (D1a D1b) (D2a D2b) +
(D3a D3b) + (D4a D4b)
12/93
213
REV 2
MC10E107 MC100E107
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
Characteristic
IIH
IEE
min
typ
25C
max
min
typ
200
85C
max
min
typ
200
max
Unit
200
Condition
mA
42
42
50
50
42
42
50
50
42
48
50
58
Characteristic
tPLH
tPHL
tSKEW
Within-Device Skew
D to Q
tr
tf
Rise/Fall Times
20 - 80%
Q
F
25C
85C
min
typ
max
min
typ
max
min
typ
max
250
500
410
725
600
1000
250
500
410
725
600
100
250
500
410
725
600
1000
Unit
Condition
ps
ps
75
75
75
1
ps
275
300
450
475
700
700
275
300
450
475
700
700
275
300
450
475
700
700
MOTOROLA
214
MOTOROLA
MC10E111
MC100E111
Low Skew
Guarateed Skew Spec
Differential Design
VBB Output
Enable
Extended 100E VEE Range of 4.2 to 5.46V
75k Input Pulldown Resistors
1:9 DIFFERENTIAL
CLOCK DRIVER
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
LOGIC SYMBOL
Q0
Q0
PIN NAMES
Pin
Function
IN, IN
EN
Q0, Q0Q8, Q8
VBB
Q1
Q1
Q2
Q2
Q0
Q0
Q1 VCCO Q1
Q2
Q2
25
24
23
20
19
22
21
Q3
Q3
IN
VEE
26
18
Q3
IN
EN
27
17
Q3
EN
IN
28
16
Q4
15
VCCO
VCC
IN
14
Q4
VBB
13
Q5
NC
12
Q5
Q8
Q8
Q7
VCCO Q7
10
11
Q6
Q6
215
Q5
Q5
Q6
Q6
Q7
Q7
VBB
5/95
Q4
Q4
REV 3
Q8
Q8
MC10E111 MC100E111
DC CHARACTERISTICS (VEE = VEE (min) to VEE (max); VCC = VCCO = GND)
40C
Symbol
VBB
Characteristic
Output Reference
Voltage
10E
100E
IIH
Input HIGH
Current
IEE
Power Supply
Current
10E
100E
VPP(DC)
VCMR
Min
Typ
0C
Max
Min
25C
Typ
Max
Min
85C
Typ
Max
Min
Typ
Max
Unit
Cond
V
1.43
1.38
1.30
1.26
1.38
1.38
1.27
1.26
150
1.35
1.38
1.25
1.26
150
1.31
1.38
1.19
1.26
150
150
A
mA
48
48
Input Sensitivity
50
Commom Mode
Range
1.6
60
60
48
48
60
60
48
48
50
0.4
60
60
50
1.6
0.4
48
55
60
69
50
1.6
0.4
1.6
0.4
mV
1. Differential input voltage required to obtain a full ECL swing on the outputs.
2. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level
must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to VPP(min).
Typ
0C
Max
Min
680
780
900
900
460
410
450
450
Typ
25C
Max
Min
560
610
850
850
480
430
450
450
Typ
85C
Characteristic
Min
Max
Min
580
630
850
850
510
460
450
450
Typ
Max
Unit
Cond
tPLH
tPHL
Propagation Delay to
Output
IN (Diff)
IN (SE)
Enable
Disable
380
280
400
400
ts
tH
Setup Time
EN to IN
250
200
200
200
ps
Hold Time
IN to EN
50
200
200
200
200
ps
tR
tskew
Release Time EN to IN
350
100
300
100
300
100
300
100
ps
ps
VPP(AC)
tr, tf
250
mV
Rise/Fall Time
250
ps
Within-Device Skew
25
75
25
50
250
450
650
275
25
50
250
375
600
275
610
660
850
850
25
50
250
375
600
275
375
600
1
2
3
3
ps
1. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals. See Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 112).
2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. See
Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 112).
3. Enable is defined as the propagation delay from the 50% point of a negative transition on EN to the 50% point of a positive transition on Q
(or a negative transition on Q). Disable is defined as the propagation delay from the 50% point of a positive transition on EN to the 50% point
of a negative transition on Q (or a positive transition on Q).
4. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device.
5. The setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than
75 mV to that IN/IN transition (see Figure 1).
6. The hold time is the minimum time that EN must remain asserted after a negative going IN or a positive going IN to prevent an output response
greater than 75 mV to that IN/IN transition (see Figure 2).
7. The release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets
the specified IN to Q propagation delay and output transition times (see Figure 3).
8. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited
for the E111 as a differential input as low as 50 mV will still produce full ECL levels at the output.
MOTOROLA
216
MC10E111 MC100E111
IN
IN
ts
EN
50%
75mV
Q
Q
75mV
IN
IN
th
EN
50%
75mV
Q
Q
75mV
IN
IN
tr
EN
50%
Q
Q
217
MOTOROLA
MOTOROLA
Quad Driver
MC10E112
MC100E112
QUAD DRIVER
Q3a
Q3b
25
24
23
21
20
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
Q2a
19
VCCO
26
18
Q2b
D3
27
17
Q2a
D2
28
16
VCC
VEE
15
Q1b
D1
14
Q1a
D0
13
Q1b
EN
12
Q1a
LOGIC DIAGRAM
Q0a
D0
Q0b
Q0a
Q0b
Q1a
5
NC
VCCO Q0a
10
Q0b
Q0a
D1
Q1b
11
Q1a
Q1b
Q0b VCCO
Q2a
* All VCC and VCCO pins are tied together on the die.
D2
Q2b
Q2a
PIN NAMES
Pin
D0 D 3
Q2b
Function
Q3a
Data Inputs
D3
Q3b
EN
Enable Input
Qna, Qnb
True Outputs
Q3a
Qna, Qnb
Inverting Outputs
Q3b
EN
12/93
218
REV 2
MC10E112 MC100E112
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
IIH
IEE
Characteristic
min
typ
25C
max
min
typ
85C
max
min
typ
max
Unit
Condition
200
200
200
200
200
200
mA
47
47
56
56
47
47
56
56
47
54
56
65
25C
85C
Characteristic
min
typ
max
min
typ
max
min
typ
max
tPLH
tPHL
200
275
400
450
600
675
200
275
400
450
600
675
200
275
400
450
600
675
tSKEW
Within-Device Skew
Dn to Qn, Qn
Qna to Qnb
tr
tf
Rise/Fall Times
20 - 80%
Unit
Condition
ps
ps
80
40
80
40
80
40
1
2
ps
275
425
700
275
425
700
275
425
700
219
MOTOROLA
MOTOROLA
MC10E116
MC100E116
QUINT DIFFERENTIAL
LINE RECEIVER
Active current sources plus a deep collector feature of the MOSAIC III
process provide the receivers with excellent common-mode noise
rejection. Each receiver has a dedicated VCCO supply lead, providing
optimum symmetry and stability.
The receiver design features clamp circuitry to cause a defined state if
both the inverting and non-inverting inputs are left open; in this case the Q
output goes LOW, while the Q output goes HIGH. This feature makes the
FN SUFFIX
device ideal for twisted pair applications.
PLASTIC PACKAGE
If both inverting and non-inverting inputs are at an equal potential of
CASE 776-02
> 2.5V, the receiver does not go to a defined state, but rather
current-shares in normal differential amplifier fashion, producing output
voltage levels midway between HIGH and LOW, or the device may even
oscillate.
The device VBB output is intended for use as a reference voltage for single-ended reception of ECL signals to that device only.
When using for this purpose, it is recommended that VBB is decoupled to VCC via a 0.01F capacitor. Please refer to the interface
section of the design guide for information on using the E116 in specialized applications.
The E116 features input pull-down resistors, as does the rest of the ECLinPS family. For applications which require
bandwidths greater than that of the E116, the E416 device may be of interest.
Pinout: 28-Lead PLCC (Top View)
PIN NAMES
Pin
D0, D0 D4, D4
Q0, Q0 Q4, Q4
VBB
D3
D4
D4
VCCO
Q4
Q4
VCCO
25
24
23
22
21
20
19
D3
26
18
Q3
D2
27
17
Q3
D2
28
16
VCC
VEE
15
Q2
VBB
14
Q2
D0
13
VCCO
D0
12
Q1
Function
Differential Input Pairs
Differential Output Pairs
Reference Voltage Output.
10
11
D1
D1
VCCO
Q0
Q0
VCCO
Q1
* All VCC and VCCO pins are tied together on the die.
5/95
220
REV 3
MC10E116 MC100E116
LOGIC DIAGRAM
D0
Q0
D0
Q0
D1
Q1
D1
Q1
D2
Q2
D2
Q2
D3
Q3
D3
Q3
D4
Q4
D4
Q4
VBB
Characteristic
Output Reference
Voltage
10E
100E
IIH
Input HIGH
Current
IEE
Power Supply
Current
10E
100E
VPP(DC)
VCMR
Min
Typ
0C
Max
Min
Typ
25C
Max
Min
Typ
85C
Max
Min
Typ
Max
Unit
Cond
V
1.43
1.38
1.30
1.26
1.38
1.38
1.27
1.26
200
1.35
1.38
1.25
1.26
200
1.31
1.38
1.19
1.26
200
200
A
mA
29
29
Input Sensitivity
150
Commom Mode
Range
2.0
35
35
29
29
35
35
150
0.6
2.0
29
29
35
35
29
29
150
0.6
35
40
150
2.0
0.6
2.0
0.6
mV
1. Differential input voltage required to obtain a full ECL swing on the outputs.
2. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level
must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to VPP(min).
0C to 85C
Characteristic
Min
Typ
Max
Min
Typ
Max
tPLH
tPHL
150
150
300
300
500
550
200
150
300
300
450
500
tskew
tskew
Within-Device Skew
VPP(AC)
tr/tf
150
Rise/Fall Time
250
Unit
Condition
ps
50
50
10
tPLH tPHL
10
150
375
625
275
375
575
ps
ps
mV
ps
2080%
221
MOTOROLA
MOTOROLA
9Bit Buffer
The MC10E/100E122 is a 9-bit buffer. The device contains nine
non-inverting buffer gates.
MC10E122
MC100E122
9-BIT BUFFER
NC
NC
25
24
23
VCCO NC
22
21
Q8
VCCO
20
19
D7
26
18
Q7
D6
27
17
Q6
D5
28
16
VCC
VEE
15
Q5
D4
14
Q4
D3
13
VCCO
D2
12
Q3
10
11
D1
D0
VCCO
Q0
Q1
VCCO
Q2
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
LOGIC DIAGRAM
* All VCC and VCCO pins are tied together on the die.
PIN NAMES
Pin
D0
Q0
D1
Q1
D2
Q2
D3
Q3
Function
D0 D 8
Data Inputs
D4
Q4
Q0 Q8
Data Outputs
D5
Q5
D6
Q6
D7
Q7
D8
Q8
12/93
222
REV 2
MC10E122 MC100E122
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
Characteristic
IIH
IEE
min
typ
25C
max
min
85C
typ
max
200
min
typ
200
max
Unit
200
Condition
mA
41
41
49
49
41
41
49
49
41
47
49
57
Characteristic
tPLH
tPHL
tSKEW
Within-Device Skew
D to Q
tr
tf
Rise/Fall Times
20 - 80%
25C
85C
min
typ
max
min
typ
max
min
typ
max
150
350
500
150
350
500
150
350
500
Unit
Condition
ps
ps
75
75
75
1
ps
300
425
800
300
425
800
300
425
800
223
MOTOROLA
MOTOROLA
4Bit D FlipFlop
MC10E131
MC100E131
4-BIT
D FLIP-FLOP
D2
CE2
R2
VCCO
Q3
Q3
25
24
23
22
21
20
19
LOGIC DIAGRAM
S
CE3
26
18
Q2
D3
D3
27
17
Q2
CE3
R
S12
28
16
VCC
VEE
15
Q1
CC
14
Q1
S03
13
Q0
D0
12
Q0
10
11
CE0
R0
D1
CE1
R1
NC
VCCO
* All VCC and VCCO pins are tied together on the die.
Pin
D0 D3
CE0 CE3
R0 R3
CC
S03, S12
Q0 Q3
Q0 Q3
D2
S
D
CE2
R
Q3
Q2
Q2
Q1
Q1
Q0
Q0
R2
S03
S12
CC
R1
CE1
D
Function
Data Inputs
Clock Enables (Individual)
Resets
Common Clock
Sets (paired)
True Outputs
Inverting Outputs
R0
R
CE0
D0
7/96
Q3
R3
D1
PIN NAMES
224
REV 3
MC10E131 MC100E131
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
40C
Symbol
IIH
IIEE
Characteristic
Input HIGH
Current
Min
Typ
0C
Max
Min
Typ
25C
Max
Min
Typ
85C
Max
Min
Typ
Max
Unit
Cond
A
350
450
300
150
CC
S
R, CE
D
Power Supply
Current
10E
100E
350
450
300
150
350
450
300
150
350
450
300
150
mA
58
58
70
70
58
58
70
70
58
58
70
70
58
67
70
81
0C to 85C
Characteristic
Min
Typ
fMAX
tPLH
tPHL
1000
1400
CE
CC
R
S
310
275
300
300
600
600
625
550
tS
tH
Setup Time
200
20
150
20
ps
Hold Time
225
20
175
20
ps
tRR
tPW
450
150
400
150
ps
tSKEW
tr/tf
Within-Device Skew
Rise/Fall Time
CLK
R, S
Max
750
725
775
775
400
400
Min
Typ
1100
1400
360
325
350
350
500
500
550
550
460
700
675
725
725
300
Condition
ps
ps
60
725
Unit
MHz
400
400
60
275
Max
480
675
ps
ps
2080%
225
MOTOROLA
MOTOROLA
MC10E136
MC100E136
6-BIT UNIVERSAL
UP/DOWN COUNTER
The CLOUT output will pulse LOW for one clock cycle one count
before the E136 reaches terminal count. The COUT output will pulse
LOW for one clock cycle when the counter reaches terminal count. For
more information on utilizing the look-ahead-carry features of the device
please refer to the applications section of this data sheet. The differential
COUT output facilitates the E136s use in programmable divider and
self-stopping counter applications.
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
Unlike the H136 and other similar universal counter designs the E136
carry out and look-ahead-carry out signals are registered on chip. This
design alleviates the glitch problem seen on many counters where the carry out signals are merely gated. Because of this
architecture there are some minor functional differences between the E136 and H136 counters. The user, regardless of
familiarity with the H136, should read this data sheet carefully. Note specifically (see logic diagram) the operation of the carry out
outputs and the look-ahead-carry in input when utilizing the master reset.
When left open all of the input pins will be pulled LOW via an input pulldown resistor. The master reset is an asynchronous
signal which when asserted will force the Q outputs LOW.
The Q outputs need not be terminated for the E136 to function properly, in fact if these outputs will not be used in a system it is
recommended to save power and minimize noise that they be left open. This practice will minimize switching noise which can
reduce the maximum count frequency of the device or significantly reduce margins against other noise in the system.
PIN NAMES
Pin
Function
D0 D 5
Q0 Q5
S1, S2
MR
CLK
COUT, COUT
CLOUT
CIN
CLIN
S2
CIN
MR
CLK
Function
L
L
L
H
H
H
X
L
H
H
L
L
H
X
X
L
H
L
H
X
X
L
L
L
L
L
L
H
Z
Z
Z
Z
Z
Z
X
D3
D4
D5
VCCO
Q5
Q4
VCCO
25
24
23
22
21
20
19
D2
26
18
Q3
S2
27
17
Q2
S1
28
16
VCC
15
VCCO
VEE
CLK
14
COUT
CIN
13
COUT
CLIN
12
CLOUT
226
10
11
D1
MR
D0 VCCO Q0
Q1 VCCO
* All VCC and VCCO pins are tied together on the die.
5/95
REV 2
S1
S2
QM0
CIN
CLIN
D Q
RQ
D Q
RQ
D Q
S
D Q
SQ
COUT
COUT
D Q
CLOUT
D Q
RQ
Bits 2 4
S
QM1
QM0
MR
CLK
D0
Q0 D1
Q1
D2 D4
Q2 Q4 D5
Q5
MOTOROLA
MC10E136 MC100E136
Note that this diagram is provided for understanding of logic operation only. It should not be used for propagation delays as many gate functions
are achieved internally without incurring a full gate delay.
MC10E136 MC100E136
DC CHARACTERISTICS
Characteristic
25C
85C
Symbol
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IIH
150
150
150
IEE
125
125
150
150
125
125
150
150
125
140
150
170
AC CHARACTERISTICS
mA
Characteristic
25C
85C
Symbol
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
fCOUNT
550
650
550
650
550
650
MHz
tPLH
tPHL
850
850
800
825
1150
1150
1150
1150
1450
1450
1300
1400
850
850
800
825
1150
1150
1150
1150
1450
1450
1300
1400
850
850
800
825
1150
1150
1150
1150
1450
1450
1300
1400
1000
800
150
800
650
400
0
400
1000
800
150
800
650
400
0
400
1000
800
150
800
650
400
0
400
150
150
300
150
200
250
0
250
150
150
300
150
200
250
0
250
150
150
300
150
200
250
0
250
1000
700
1000
700
1000
700
700
400
700
400
700
400
275
300
600
700
275
300
600
700
275
300
600
700
Setup Time
S1, S2
D
CLIN
CIN
ts
Hold Time
S1, S2
D
CLIN
CIN
th
tRR
tPW
Rise/Fall Times
COUT
Other
MOTOROLA
Condition
tr
tf
Condition
ps
ps
ps
ps
ps
ps
228
20% - 80%
MC10E136 MC100E136
EXPANDED TRUTH TABLE
Function
S1
S2
MR
CIN
CLIN
CLK
D5
D4
D3
D2
D1
D0
Q5
Q4
Q3
Q2
Q1
Q0
COUT
CLOUT
Preset
Down
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
H
L
L
L
H
L
L
L
H
L
L
L
H
H
L
L
H
L
H
L
H
H
H
L
H
H
L
H
H
Preset
Up
L
L
L
L
L
L
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
L
L
L
L
H
H
L
L
H
H
L
H
L
H
L
H
H
L
H
H
H
H
L
H
H
H
H
Hold
H
H
H
H
L
L
X
X
X
X
Z
Z
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
H
H
L
L
H
H
H
H
Down
Hold
Down
Hold
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
H
H
L
L
L
L
L
L
L
H
H
L
Z
Z
Z
Z
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
H
H
L
H
H
H
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
L
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
X
L
L
H
L
H
H
L
L
X
L
L
L
L
L
H
L
Z
Z
Z
Z
Z
Z
Z
Z
Z
X
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
L
H
H
H
H
H
H
L
L
H
L
L
H
H
H
H
L
H
H
H
H
L
H
H
L
H
H
H
L
H
H
H
H
H
Up
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
H
H
H
H
H
H
H
H
Reset
Hold
Hold
Preset
Up
Hold
Up
Hold
Hold
229
MOTOROLA
MC10E136 MC100E136
APPLICATIONS INFORMATION
result of the terminal count signal of the lower order counters
having to ripple through the entire counter chain. As a result
past counters of this type were not widely used in large bit
counter applications.
Overview
The MC10E/100E136 is a 6-bit synchronous, presettable,
cascadable universal counter. Using the S1 and S2 control
pins the user can select between preset, count up, count
down and hold count. The master reset pin will reset the
internal counter, and set the COUT, CLOUT, and CLIN
flip-flops. Unlike previous 136 type counters the carry out
outputs will go to a high state during the preset operation. In
addition since the carry out outputs are registered they will
not go low if terminal count is loaded into the register. The
look-ahead-carry out output functions similarly.
Q0 > Q5
CLOCK
Q0 > Q5
CLK
Q0 > Q5
Q0 > Q5
CLK
CLK
CLK
MSB
LSB
LO
CIN
COUT
LO
CLIN
CLOUT
LO
CIN
COUT
CIN
COUT
CIN
COUT
CLIN
CLOUT
CLIN
CLOUT
CLIN
CLOUT
D0 > D5
111101
D0 > D5
111110
D0 > D5
111111
000000
D0 > D5
000001
CLK
CLOUT
COUT
MOTOROLA
230
MC10E136 MC100E136
CIN
ACTIVE
LOW
CLIN
CLK
Q0 > Q5
CLK
LO
Divide
S1
COUT
COUT
D0 > D5
231
Ratio
D5
D4
D3
D2
D1
D0
2
3
4
5
36
37
38
62
63
64
L
L
L
L
H
H
H
H
H
H
L
L
L
L
L
L
L
H
H
H
L
L
L
L
L
L
L
H
H
H
L
L
L
H
L
H
H
H
H
H
L
H
H
L
H
L
L
L
H
H
H
L
H
L
H
L
H
H
L
H
MOTOROLA
MC10E136 MC100E136
LOAD
100100
100011
100010
000011
000010
000001
000000
LOAD
CLOCK
S1
COUT
DIVIDE BY 37
Q0 > Q5
CLOCK
CLK
Q0 > Q5
CLK
S1
Q0 > Q5
CLK
S1
Q0 > Q5
S1
CLK
LSB
S1
MSB
LO
CIN
COUT
LO
CLIN
CLOUT
D0 > D5
LO
CIN
COUT
CIN
COUT
CIN
COUT
CLIN
CLOUT
CLIN
CLOUT
CLIN
CLOUT
D0 > D5
D0 > D5
D0 > D5
MOTOROLA
232
MOTOROLA
MC10E137
MC100E137
8-BIT RIPPLE
COUNTER
A_Start
EN1
EN2
Q0
Q0
Q1
CLK
CLK
Q
CLK
CLK
CLK
CLK
Q
Q
CLK
CLK
Q
Q
D
R
VBB
Q
Q
R
7/96
233
CLK
CLK
D
MR
Q7
Q1
REV 2
Q7
MC10E137 MC100E137
Pinout: 28-Lead PLCC (Top View)
Q7
Q7
Q6
Q6
VCCO
Q5
Q5
25
24
23
22
21
20
19
A_Start
26
18
Q4
EN1
27
17
Q4
EN2
28
16
VCC
VEE
15
Q3
CLK
14
Q3
CLK
13
Q2
VBB
12
Q2
10
11
MR
VCCO
Q0
Q0
Q1
Q1
VCCO
* All VCC and VCCO pins are tied together on the die.
EN1
EN2
A_Start
MR
CLK
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Reset
Count
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
H
Stop
H
H
L
L
L
L
L
L
Z
Z
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
Asynch Start
H
H
L
L
L
L
H
H
H
L
L
L
Z
Z
Z
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
L
H
L
H
L
Count
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
L
H
L
L
H
L
H
Stop
L
L
H
H
L
L
L
L
Z
Z
L
L
L
L
L
L
L
L
H
H
L
L
L
L
H
H
Synch Start
H
H
H
H
H
H
L
L
L
L
L
L
Z
Z
Z
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
L
H
H
H
L
L
H
L
Stop
H
H
L
L
L
L
L
L
Z
Z
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
Count
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
L
H
H
H
L
H
Reset
MOTOROLA
234
MC10E137 MC100E137
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
VBB
Characteristic
Output Reference Voltage
10E
100E
IIH
IEE
Min
Typ
25C
Max
Min
Typ
85C
Max
Min
Typ
Max
Unit
Condition
V
1.38
1.38
1.27
1.27
1.35
1.38
1.25
1.26
150
1.31
1.38
1.19
1.26
150
150
A
mA
121
121
145
145
121
121
145
145
121
139
145
167
Characteristic
Min
Typ
25C
Max
Min
Typ
1800
2200
1300
1600
1950
2275
2625
2950
3250
3575
950
700
1700
2050
2450
2775
3150
3475
3800
4125
1325
1000
85C
Max
Min
Typ
1800
2200
1350
1650
2025
2350
2700
3050
3375
3700
950
700
1750
2100
2500
2850
3225
3550
3925
4250
1325
1000
Max
Unit
fCOUNT
1800
2200
tPLH
tPHL
1300
1600
1950
2275
2625
2950
3250
3575
950
700
1700
2025
2425
2750
3125
3450
3775
4075
1325
1000
ts
150
150
150
ps
th
300
150
300
150
300
150
ps
tRR
400
200
400
200
400
200
400
VPP
0.25
1.0
0.25
1.0
0.25
1.0
VCMR
0.4
2.0
0.4
2.0
0.4
2.0
tr
tf
Rise/Fall Times
Q0,Q1
Q2 to Q7
150
275
400
600
150
275
400
600
150
275
400
600
tPW
Condition
MHz
ps
2150
2500
2925
3350
3750
4150
4450
4800
1700
1300
2150
2500
2925
3350
3750
4150
4450
4800
1700
1300
2200
2550
3000
3425
3825
4250
4600
4950
1700
1300
ps
ps
400
400
ps
Note 1
20%80%
1. Minimum input swing for which AC parameters are guaranteed. Full DC ECL output swings will be generated with only 50mV input swings.
235
MOTOROLA
MOTOROLA
MC10E141
MC100E141
8-BIT SHIFT
REGISTER
8-Bit
Full-Function, Bi-Directional
Asynchronous Master Reset
Pin-Compatible with E241
Extended 100E VEE Range of 4.2V to 5.46V
75k Input Pulldown Resistors
The select pins, SEL0 and SEL1, select one of four modes of
operation: Load, Hold, Shift Left, Shift Right, according to the Function
Table.
Input data is accepted a set-up time before the positive clock edge. A
HIGH on the Master Reset (MR) pin asynchronously resets all the
registers to zero.
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
DL
D7
D6
D5
VCCO
Q7
25
24
23
22
21
20
19
SEL1
26
18
Q6
CLK
27
17
Q5
MR
28
16
VCC
VEE
15
NC
DR
14
VCCO
D0
13
Q4
D1
4
6
10
11
D2
D3
D4
VCCO
Q0
Q1
Q2
SEL0
SEL1
L
L
H
H
L
H
L
H
Function
Load
Shift Right (Dn to Dn+1)
Shift Left (Dn to Dn 1)
Hold
PIN NAMES
Pin
Q3
12
5
FUNCTION TABLE
Function
D0 D7
DL, DR
SEL0, SEL1
CLK
Q0 Q7
MR
* All VCC and VCCO pins are tied together on the die.
DL
DR
SEL0
SEL1
MR
CLK
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Load
Shift Right
X
X
X
L
L
L
L
H
L
L
Z
Z
D0
L
D1
Q0
D2
Q1
D3
Q2
D4
Q3
D5
Q4
D6
Q5
D7
Q6
Q0
Q1
Q2
Q3
Q4
Q5
Q0
Q1
Q2
Q3
Q4
Q5
Q0
Q1
Q2
Q3
Q4
Q5
Hold
Q0
Q1
Q2
Q3
Q4
Q5
Reset
X
X
X
X
H
X
H
X
L
H
Z
X
Q0
L
Q1
L
Q2
L
Q3
L
Q4
L
Q5
L
L
L
H
L
Shift Left
7/96
236
REV 3
MC10E141 MC100E141
LOGIC DIAGRAM
DL
BITS 1 6
DR
R
D0
Q0
Q D7
Q7
SEL1
SEL0
CLK
MR
Characteristic
IIH
IEE
min
typ
25C
max
min
typ
85C
max
150
min
typ
150
max
150
Unit
Condition
A
mA
131
131
181
181
131
131
181
181
131
151
181
181
Characteristic
min
typ
25C
max
min
typ
700
900
625
600
750
725
85C
max
min
typ
700
900
625
600
750
725
fSHIFT
700
900
tPLH
tPHL
625
600
750
725
ts
Setup Time
D
SEL0
SEL1
175
350
300
25
200
150
175
350
300
25
200
150
175
350
300
25
200
150
Hold Time
D
SEL0
SEL1
200
100
100
25
200
150
200
100
100
25
200
150
200
100
100
25
200
150
tRR
900
700
900
700
900
700
tPW
400
th
tSKEW
Within-Device Skew
tr
tf
Rise/Fall Times
20 - 80%
max
Unit
Condition
MH
z
ps
975
975
975
975
975
975
ps
ps
ps
ps
400
60
400
60
60
ps
ps
300
525
800
300
525
800
300
525
800
237
MOTOROLA
MOTOROLA
MC10E142
MC100E142
9-BIT SHIFT
REGISTER
D8
D7
D6
D5
VCCO
Q8
25
24
23
22
21
20
19
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
MR
26
18
Q7
CLK1
27
17
Q6
CLK2
28
VEE
S-IN
16
VCC
15
Q5
14
VCCO
D0
13
Q4
D1
12
Q3
10
LOGIC DIAGRAM
S-IN
D0
1
0
D1
1
0
D2
1
0
D3
1
0
D8
1
0
Q0
Q1
Q2
Q3
Q8
11
D2
D3
D4 VCCO Q0
Q1
Q2
* All VCC and VCCO pins are tied together on the die.
PIN NAMES
Pin
D0 D 8
S-IN
SEL
CLK1, CLK2
MR
Q0 Q8
Function
Parallel Data Inputs
Serial Data Input
Mode Select Input
Clock Inputs
Master Reset
Data Outputs
SEL
CLK1
CLK2
FUNCTIONS
SEL
L
H
Mode
MR
Load
Shift
12/93
238
REV 2
MC10E142 MC100E142
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
Characteristic
IIH
IEE
min
typ
25C
max
min
typ
85C
max
150
min
typ
150
max
Unit
150
Condition
mA
120
120
145
145
120
120
145
145
120
138
145
165
Characteristic
min
typ
25C
max
min
typ
700
900
600
600
800
800
85C
max
min
typ
700
900
600
600
800
800
fSHIFT
700
900
tPLH
tPHL
600
600
800
800
ts
Setup Time
D
SEL
50
300
100
150
50
300
100
150
50
300
100
150
Hold Time
D
SEL
300
75
100
150
300
75
100
150
300
75
100
150
tRR
900
700
900
700
900
700
tPW
400
th
tSKEW
Within-Device Skew
tr
tf
Rise/Fall Times
20 - 80%
max
Unit
Condition
MH
z
ps
1000
1000
1000
1000
1000
1000
ps
ps
ps
ps
400
75
400
75
75
ps
Note 1
ps
300
525
800
300
525
800
300
525
800
239
MOTOROLA
MOTOROLA
MC10E143
MC100E143
9-BIT HOLD
REGISTER
The SEL (Select) input pin is used to switch between the two modes of
operation HOLD and LOAD. Input data is accepted by the registers a
set-up time before the positive going edge of CLK1 or CLK2. A HIGH on
the Master Reset pin (MR) asynchronously resets all the registers to zero.
Pinout: 28-Lead PLCC (Top View)
SEL
D8
D7
D6
D5
VCCO
Q8
25
24
23
22
21
20
19
MR
26
18
Q7
CLK1
27
17
Q6
CLK2
28
16
VCC
VEE
15
Q5
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
LOGIC DIAGRAM
D0
NC
14
VCCO
D0
13
Q4
D1
12
5
10
11
D1
MUX
MUX
Q0
R
Q1
D
R
Q3
D2
D3
D4 VCCO Q0
Q1
Q2
* All VCC and VCCO pins are tied together on the die.
MUX
Q2
R
D2
D3
MUX
Q3
D
R
PIN NAMES
Pin
D0 D 8
SEL
CLK1, CLK2
MR
Q0 Q8
NC
Function
Parallel Data Inputs
Mode Select Input
Clock Inputs
Master Reset
Data Outputs
No Connection
MUX
D8
SEL
FUNCTIONS
SEL
L
H
Mode
CLK1
CLK2
MR
Load
Hold
12/93
240
REV 2
Q8
D
R
MC10E143 MC100E143
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
Characteristic
IIH
IEE
min
typ
25C
max
min
typ
85C
max
150
min
typ
150
max
Unit
150
Condition
mA
120
120
145
145
120
120
145
145
120
138
145
165
Characteristic
min
typ
fMAX
700
900
tPLH
tPHL
600
600
800
800
ts
Setup Time
D
SEL
50
300
Hold Time
D
SEL
tRR
tPW
th
25C
min
typ
700
900
600
600
800
800
100
150
50
300
300
75
100
150
900
700
400
tSKEW
Within-Device Skew
tr
tf
Rise/Fall Times
20 - 80%
max
85C
max
min
typ
700
900
600
600
800
800
100
150
50
300
100
150
300
75
100
150
300
75
100
150
900
700
900
700
max
Unit
Condition
MHz
ps
1000
1000
1000
1000
1000
1000
ps
ps
ps
ps
400
75
400
75
75
ps
ps
300
525
800
300
525
800
300
525
800
241
MOTOROLA
MOTOROLA
6Bit D Latch
MC10E150
MC100E150
6-BIT D LATCH
LOGIC DIAGRAM
D0
Q0
Q0
D1
Q1
Q1
D2
Q2
Q2
D3
Q3
D
R
D4
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
Q3
Q4
Q4
MR
25
D5
D
R
LEN1
LEN2
LEN2 LEN1
24
23
NC
VCCO
Q5
Q5
22
21
20
19
Q5
D5
26
18
Q4
Q5
D4
27
17
Q4
D3
28
16
VCC
VEE
15
Q3
D2
14
Q3
D1
13
Q2
D0
12
Q2
MR
PIN NAMES
Pin
D0 D5
LEN1, LEN2
MR
Q0 Q5
Q0 Q5
Function
Data Inputs
Latch Enables
Master Reset
True Outputs
Inverting Outputs
10
11
NC
VCCO
Q0
Q0
Q1
Q1
VCCO
* All VCC and VCCO pins are tied together on the die.
12/93
242
REV 2
MC10E150 MC100E150
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
IIH
IEE
Characteristic
min
typ
25C
max
min
typ
85C
max
min
typ
max
Unit
Condition
200
150
200
150
200
150
mA
52
52
62
62
52
52
62
62
52
60
62
72
Characteristic
25C
85C
min
typ
max
min
typ
max
min
typ
max
550
700
750
250
375
450
375
500
625
550
700
750
250
375
450
375
500
625
550
700
750
tPLH
tPHL
250
375
450
375
500
625
ts
Setup Time
D
200
50
200
50
200
50
Hold Time
D
200
50
200
50
200
50
tRR
750
650
750
650
750
650
tPW
400
th
tSKEW
Within-Device Skew
tr
tf
Rise/Fall Times
20 - 80%
Unit
Condition
ps
ps
ps
ps
ps
ps
400
50
400
50
50
ps
ps
300
450
650
300
450
650
300
450
650
243
MOTOROLA
MOTOROLA
6Bit D Register
MC10E151
MC100E151
6-BIT D REGISTER
Q0
Q0
D1
Q1
Q1
D2
Q2
Q2
D3
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
Q3
Q3
D4
Q4
Q4
D5
Q5
Q5
CLK1
CLK2
MR
PIN NAMES
Pin
D0 D5
CLK1, CLK2
MR
Q0 Q5
Q0 Q5
Function
Data Inputs
Clock Inputs
Master Reset
True Outputs
Inverted Outputs
25
CLK2 CLK1
24
VCCO
Q5
Q5
22
21
20
19
D5
26
18
Q4
D4
27
17
Q4
D3
28
16
VCC
VEE
15
Q3
D2
14
Q3
D1
13
Q2
D0
12
Q2
10
11
NC
VCCO
Q0
Q0
Q1
Q1
VCCO
* All VCC and VCCO pins are tied together on the die.
12/93
23
NC
244
REV 2
MC10E151 MC100E151
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
Characteristic
IIH
IEE
min
typ
25C
max
min
typ
150
85C
max
min
typ
150
max
Unit
150
Condition
mA
65
65
78
78
65
65
78
78
65
75
78
90
Characteristic
min
typ
25C
max
min
typ
1100
1400
475
475
650
650
85C
max
min
typ
1100
1400
475
475
650
650
fMAX
1100
1400
tPLH
tPHL
475
475
650
650
ts
Setup TIme
D
175
175
175
Hold Time
D
350
175
350
175
350
175
tRR
750
550
750
550
750
550
tPW
400
th
tSKEW
Within-Device Skew
tr
tf
Rise/Fall Times
20 - 80%
max
Unit
Condition
MH
z
ps
800
850
800
850
800
850
ps
ps
ps
ps
400
65
400
65
65
ps
ps
300
450
700
300
450
700
300
450
700
245
MOTOROLA
MOTOROLA
MC10E154
MC100E154
5-BIT 2:1
MUX-LATCH
D4a
D3b
D3a VCCO
Q4
Q4
25
24
23
22
20
19
21
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
SEL
26
18
Q3
LEN1
27
17
Q3
LEN2
28
16
VCC
LOGIC DIAGRAM
VEE
15
Q2
MR
14
Q2
D0a
13
Q1
D0b
12
Q1
D1a
D1b
D2a
D2b VCCO
D0a
MUX
D0b
SEL
D1a
MUX
D1b
SEL
10
11
D2a
MUX
Q0
Q0
D2b
SEL
D3a
MUX
D3b
SEL
D4a
MUX
D4b
SEL
Q
D
EN Q
R
Q0
Q
D
EN Q
R
Q1
Q
D
EN Q
R
Q2
Q
D
EN Q
R
Q3
Q
D
EN Q
R
Q4
Q0
Q1
Q2
* All VCC and VCCO pins are tied together on the die.
PIN NAMES
Pin
D0a D4a
D0b D4b
SEL
LEN1, LEN2
MR
Q0 Q4
Q0 Q4
Function
Input Data a
Input Data b
Data Select Input
Latch Enables
Master Reset
True Outputs
Inverted Outputs
SEL
LEN1
LEN2
TRUTH TABLE
SEL
Data
H
L
a
b
MR
12/93
Q3
246
REV 2
Q4
MC10E154 MC100E154
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
Characteristic
IIH
IEE
min
typ
25C
max
min
85C
typ
max
150
min
typ
150
max
Unit
150
Condition
mA
76
76
91
91
76
76
91
91
76
87
91
105
Characteristic
25C
85C
min
typ
max
min
typ
max
min
typ
max
700
925
750
800
325
475
350
450
500
650
500
600
700
925
750
800
325
475
350
450
500
650
500
600
700
925
750
800
tPLH
tPHL
325
475
350
450
500
650
500
600
ts
Setup Time
D
SEL
300
500
100
250
300
500
100
250
300
500
100
250
Hold Time
D
SEL
300
200
100
250
300
200
100
250
300
200
100
250
tRR
800
600
800
600
800
600
tPW
400
th
tSKEW
Within-Device Skew
tr
tf
Rise/Fall Times
20 - 80%
Unit
Condition
ps
ps
ps
ps
ps
400
50
400
50
50
ps
ps
300
475
800
300
475
800
300
475
800
247
MOTOROLA
MOTOROLA
MC10E155
MC100E155
6-BIT 2:1
MUX-LATCH
D4b
D4a
D3b
D3a
NC
VCCO
25
24
23
22
21
20
19
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
D5b
26
18
Q5
LEN1
27
17
Q4
LEN2
28
16
VCC
D0a
MUX
VEE
15
Q3
D0b
SEL
14
Q2
D1a
MUX
MR
SEL
13
VCCO
D0a
12
Q1
D0b
D1a
D1b
D2a
10
D2b VCCO
LOGIC DIAGRAM
11
PIN NAMES
Pin
D0a D04
D0b D4b
SEL
LEN1, LEN2
MR
Q0 Q4
Function
Input Data a
Input Data b
Data Select Input
Latch Enables
Master Reset
Outputs
TRUTH TABLE
SEL
Data
H
L
a
b
D1b
SEL
D2a
MUX
D2b
SEL
D3a
MUX
D3b
SEL
D4a
MUX
D4b
SEL
D5a
MUX
D5b
SEL
LEN1
LEN2
MR
5/95
248
REV 3
Q1
Q2
Q3
Q4
Q5
D
EN
R
D
EN
R
D
EN
R
D
EN
R
D
EN
SEL
Q0
EN
Q0
* All VCC and VCCO pins are tied together on the die.
Q
D
MC10E155 MC100E155
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
Characteristic
IIH
IEE
min
typ
25C
max
min
typ
85C
max
150
min
typ
150
max
Unit
150
Condition
mA
85
85
102
102
85
85
102
102
85
98
102
117
Characteristic
25C
85C
min
typ
max
min
typ
max
min
typ
max
700
925
750
850
325
475
350
450
500
675
500
600
700
925
750
850
325
475
350
450
500
675
500
600
700
925
750
850
tPLH
tPHL
325
475
350
450
500
675
500
600
ts
Setup Time
D
SEL
300
500
100
250
300
500
100
250
300
500
100
250
Hold TIme
D
SEL
300
0
100
250
300
0
100
250
300
0
100
250
tRR
800
650
800
650
800
650
tPW
400
th
tSKEW
Within-Device Skew
tr
tf
Rise/Fall Times
20 - 80%
Unit
Condition
ps
ps
ps
ps
ps
400
75
400
75
75
ps
ps
300
450
800
300
450
800
300
450
800
249
MOTOROLA
MOTOROLA
MC10E156
MC100E156
3-BIT 4:1
MUX-LATCH
D1a
D2d
D2c
D2b
D2a VCCO
25
24
23
22
21
20
19
SEL0
26
18
Q2
SEL1
27
17
Q2
MR
28
16
VCC
VEE
15
Q1
LEN1
14
Q1
LEN2
13
VCCO
D1c
12
4
5
D1d
D0a
D0b
D0c
10
D0d VCCO
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
LOGIC DIAGRAM
D0a
D0b
D0c
D0d
Q0
4:1
MUX
Q0
EN
R
Q0
Q1
EN
R
Q1
Q2
11
D1a
D1b
Q0
D1c
D1d
* All VCC and VCCO pins are tied together on the die.
4:1
MUX
PIN NAMES
Pin
Function
D0x D3x
SEL0, SEL1
LEN1, LEN2
MR
Q0 Q2
Q0 Q2
Input Data
Select Inputs
Latch Enables
Master Reset
True Outputs
Inverted Outputs
D2a
D2b
D2c
D2d
SEL0
FUNCTION TABLE
SEL1
SEL0
Data
L
L
H
H
L
H
L
H
a
b
c
d
SEL1
LEN1
LEN2
MR
7/96
250
REV 3
4:1
MUX
EN
R
Q2
MC10E156 MC100E156
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
Characteristic
IIH
IEE
min
typ
25C
max
min
85C
typ
max
150
min
typ
150
max
Unit
150
Condition
mA
75
75
90
90
75
75
90
90
75
86
90
103
25C
85C
Characteristic
min
typ
max
min
typ
max
min
typ
max
tPLH
tPHL
400
550
450
350
350
600
775
650
500
600
900
1050
900
800
825
400
550
450
350
350
600
775
650
500
600
900
1050
900
800
825
400
550
450
350
350
600
775
650
500
600
900
1050
900
800
825
ts
Setup Time
D
SEL0
SEL1
400
700
600
275
300
400
400
700
600
275
300
400
400
700
600
275
300
400
Hold Time
D
SEL0
SEL1
300
100
200
275
300
400
300
100
200
275
300
400
300
100
200
275
300
400
tRR
800
600
800
600
800
600
tPW
th
tSKEW
Within-Device Skew
tr
tf
Rise/Fall Times
20 - 80%
Unit
Condition
ps
ps
ps
ps
ps
400
400
50
400
50
50
ps
ps
275
475
700
275
475
700
275
475
700
251
MOTOROLA
MOTOROLA
MC10E157
MC100E157
QUAD 2:1
MULTIPLEXER
NC
D3a
D3b VCCO
Q3
Q3
25
24
23
22
20
19
21
D2b
26
18
Q2
D2a
27
17
Q2
SEL2
28
16
VCC
VEE
15
Q1
SEL1
14
Q1
D1a
13
Q0
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
LOGIC DIAGRAM
D0a
MUX
D0b
D1b
12
Q0
10
11
SEL0
SEL0
D0a
D0b
NC
NC
NC
VCCO
D1a
* All VCC and VCCO pins are tied together on the die.
Q0
1
MUX
D1b
Q0
Q1
Q1
SEL1
D2a
PIN NAMES
MUX
Pin
D0a D3a
D0b D3b
SEL0 SEL3
Q0 Q3
Q0 Q3
Function
Input Data a
Input Data b
Select Inputs
True Outputs
Inverted Outputs
D2b
Q2
SEL2
D3a
1
MUX
TRUTH TABLE
D3b
SEL
Data
H
L
a
b
SEL3
12/93
Q2
252
REV 2
Q3
Q3
MC10E157 MC100E157
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
IIH
IEE
Characteristic
min
typ
25C
max
min
typ
85C
max
min
typ
max
Unit
Condition
200
150
200
150
200
150
mA
32
32
38
38
32
32
38
38
32
37
38
44
Characteristic
tPLH
tPHL
tSKEW
Within-Device Skew
tr
tf
Rise/Fall Times
20 - 80%
25C
85C
min
typ
max
min
typ
max
min
typ
max
220
425
380
600
550
800
220
425
380
600
550
800
220
425
380
600
550
800
Unit
Condition
ps
70
70
70
ps
ps
275
400
650
275
400
650
275
400
650
253
MOTOROLA
MOTOROLA
MC10E158
MC100E158
5-BIT 2:1
MULTIPLEXER
D3b
D3a VCCO
Q4
Q4
VCCO
25
24
23
21
20
19
22
D4b
26
18
Q3
D2a
27
17
Q3
D2b
28
16
VCC
VEE
15
Q2
SEL
14
Q2
D0a
13
VCCO
D0b
12
Q1
5
D1a
D1b VCCO
10
11
Q0
Q0
VCCO
Q1
* All VCC and VCCO pins are tied together on the die.
PIN NAMES
Pin
D0a D4a
D0b D4b
SEL
Q0 Q4
Q0 Q4
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
LOGIC DIAGRAM
D0a
MUX
Q0
D0b
SEL
Q0
D1a
MUX
Q1
D1b
SEL
Q1
D2a
MUX
Q2
D2b
SEL
Q2
D3a
MUX
Q3
D3b
SEL
Q3
D4a
MUX
Q4
D4b
SEL
Q4
Function
Input Data a
Input Data b
Select Input
True Outputs
Inverted Outputs
FUNCTION TABLE
SEL
Data
H
L
a
b
SEL
12/93
254
REV 2
MC10E158 MC100E158
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
IIH
IEE
Characteristic
min
typ
25C
max
min
typ
85C
max
min
typ
max
Unit
Condition
200
150
200
150
200
150
mA
33
33
40
40
33
33
40
40
33
38
40
46
Characteristic
tPLH
tPHL
tSKEW
Within-Device Skew
tr
tf
Rise/Fall Time
20 - 80%
25C
85C
min
typ
max
min
typ
max
min
typ
max
225
400
385
600
550
775
225
400
385
600
550
775
225
400
385
600
550
775
Unit
Condition
ps
60
60
60
ps
ps
275
425
650
275
425
650
275
425
650
255
MOTOROLA
MOTOROLA
12Bit Parity
MC10E160
Generator/Checker
MC100E160
12-BIT PARITY
GENERATOR/CHECKER
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
D3
D2
D1
D0
EN
VCCO
25
24
23
22
21
20
19
D5
26
18
D6
27
17
D7
28
16
VCC
VEE
15
D8
14
D9
13
VCCO
D10
12
NC
10
11
PIN NAMES
Pin
D0 D11
S-IN
EN
HOLD
SHIFT
CLK1, CLK2
R
Q, Q
Y, Y
LOGIC DIAGRAM
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
0
MUX
1 SEL
EN
HOLD
Function
Data Inputs
Serial Data Input
Enable, active LOW
Hold, active LOW
Shift, active HIGH
Clock Inputs
Reset Inputs
Direct Output
Register Output
S-IN
SHIFT
CLK1
CLK2
R
12/93
256
REV 2
0
MUX
1 SEL
D
R
MC10E160 MC100E160
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
IIH
IEE
Characteristic
min
typ
25C
max
min
85C
typ
max
min
typ
max
Unit
Condition
200
300
150
200
300
150
200
300
150
mA
82
82
98
98
82
82
98
98
82
94
98
113
25C
85C
Characteristic
min
typ
max
min
typ
max
min
typ
max
tPLH
tPHL
400
300
275
275
650
550
500
500
950
750
700
725
400
300
275
275
650
550
500
500
950
750
700
725
400
300
275
275
650
550
500
500
950
750
700
725
ts
Setup Time
D
HOLD
S-IN
SHIFT
1200
600
350
500
900
300
150
250
1200
600
350
500
900
300
150
250
1200
600
350
500
900
300
150
250
Hold Time
D
HOLD
S-IN
SHIFT
400
100
300
200
900
300
150
250
400
100
300
200
900
300
150
250
400
100
300
200
900
300
150
250
300
450
300
450
300
450
th
tr
tf
Rise/Fall Time
20 - 80%
Unit
Condition
ps
ps
ps
ps
650
650
650
1. Within a device skew is guaranteed for identical transitions on similar paths through a device.
257
MOTOROLA
MOTOROLA
MC10E163
MC100E163
2-BIT
8:1 MULTIPLEXER
Differential Outputs
Extended 100E VEE Range of 4.2V to 5.46V
75k Input Pulldown Resistors
Pinout: 28-Lead PLCC (Top View)
B2
B3
B4
B5
B6
B7
VCCO
25
24
23
22
21
20
19
B1
26
18
QB
B0
27
17
QB
SEL0
28
16
VCC
VEE
15
NC
SEL1
14
VCCO
SEL2
13
QA
A0
12
QA
10
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
LOGIC DIAGRAM
11
A1
A2
A3
A4
A5
A6
A7
* All VCC and VCCO pins are tied together on the die.
A0
A1
A2
FUNCTION TABLE
SEL2
SEL1
SEL0
A/B
Data
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
0
1
2
3
4
5
6
7
A3
QA
QA
A4
A5
A6
A7
SEL0
SEL1
PIN NAMES
Pin
A0 A7
B0 B7
SEL0, 1, 2
QA, QB
QA, QB
SEL2
Function
A Data Inputs
B Data Inputs
Select Inputs
True Outputs
Inverting Outputs
To Side B
12/93
258
REV 2
MC10E163 MC100E163
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
Characteristic
IIH
IEE
min
typ
25C
max
min
typ
150
85C
max
min
typ
150
max
Unit
150
Condition
mA
73
73
88
88
73
73
88
88
73
83
88
100
Characteristic
tPLH
tPHL
tSKEW
Within-Device Skew
An, Bn to Q
An, Am to QA
Bn, Bm to QB
tr
tf
Rise/Fall Time
20 - 80%
min
0C
typ
max
min
25C
typ
max
min
85C
typ
max
400
525
425
350
550
725
625
525
800
950
850
725
400
525
425
350
550
725
625
525
800
950
850
725
400
525
425
350
550
725
625
525
800
950
850
725
Unit
Condition
ps
ps
40
30
30
40
30
30
40
30
30
ps
275
375
575
275
375
575
275
375
575
1. Within-device skew is defined as identical transitions on similar paths through a device; n = 0-7, m n, m = 0-7.
259
MOTOROLA
MOTOROLA
16:1 Multiplexer
MC10E164
MC100E164
16:1 MULTIPLEXER
Differential Output
Extended 100E VEE Range of 4.2V to 5.46V
Internal 75k Input Pulldown Resistors
A11
A12
A13
A14
A15 VCCO
25
24
23
22
21
20
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
19
A9
26
18
NC
A8
27
17
NC
SEL3
28
16
VCC
VEE
15
SEL2
14
SEL0
13
VCCO
SEL1
12
A0
10
11
A7
A6
A5
A4
A3
A2
A1
* All VCC and VCCO pins are tied together on the die.
LOGIC DIAGRAM
A0
A1
16:1
Q
A14
A15
PIN NAMES
Pin
A0 A15
SEL[0:3]
Q, Q
Function
SEL0
Data Inputs
Select Inputs
Output
SEL1
SEL2
SEL3
12/93
260
REV 2
MC10E164 MC100E164
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
Characteristic
IIH
IEE
min
typ
25C
max
min
typ
150
85C
max
min
typ
150
max
Unit
150
Condition
mA
59
59
71
71
59
59
71
71
59
68
71
81
Characteristic
tPLH
tPHL
tSKEW
tr
tf
Rise/Fall Times
20 - 80%
25C
85C
min
typ
max
min
typ
max
min
typ
max
350
500
400
400
400
600
700
675
675
550
850
900
900
900
700
350
500
400
400
400
600
700
675
675
550
850
900
900
900
700
350
500
400
400
400
600
700
675
675
550
850
900
900
900
700
Unit
Condition
ps
50
50
50
ps
ps
275
400
550
275
400
550
275
400
550
1. Within Device skew is defined as the difference in the A to Q delay between the 16 different A inputs.
FUNCTION TABLE
SEL3
SEL2
SEL1
SEL0
Data
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
261
MOTOROLA
MOTOROLA
MC10E166
MC100E166
9-BIT MAGNITUDE
COMPARATOR
B1
A1
B0
A0
VCCO
25
24
23
22
21
20
19
A3
26
18
A=B
B3
27
17
NC
NC
28
16
VCC
VEE
15
B>A
A4
14
VCCO
B4
13
A>B
A5
12
NC
10
11
B5
A6
B6
A7
B7
A8
B8
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
LOGIC DIAGRAM
A0 A8
* All VCC and VCCO pins are tied together on the die.
B0 B8
PIN NAMES
Pin
A0 A8
B0 B8
A>B
B>A
A=B
Function
A Data Inputs
B Data Inputs
A Greater than B Output
B Greater than A Output
A Equal to B Output
(active-LOW)
7/96
262
REV 3
COMPARATOR
B2
A>B
A=B
B>A
MC10E166 MC100E166
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
Characteristic
IIH
IEE
min
typ
25C
max
min
typ
150
85C
max
min
typ
150
max
Unit
150
Condition
mA
113
113
156
156
113
113
156
156
113
130
156
156
Characteristic
25C
85C
min
typ
max
min
typ
max
min
typ
max
tPLH
tPHL
500
500
750
850
1100
1400
500
500
750
850
1100
1400
500
500
750
850
1100
1400
tr
tf
Rise/Fall Time
20 - 80%
300
450
800
300
450
800
300
450
800
Unit
Condition
ps
ps
263
MOTOROLA
MOTOROLA
MC10E167
MC100E167
6-BIT 2:1
MUX-REGISTER
D4b
D4a
D3b
D3a
NC
VCCO
25
24
23
22
21
20
19
D5b
26
18
Q5
CLK1
27
17
Q4
CLK2
28
16
VCC
VEE
15
Q3
MR
14
Q2
SEL
13
VCCO
D0a
12
Q1
D0b
D1a
D1b
D2a
10
D2b VCCO
Pin
D0a D5a
D0b D5b
SEL
CLK1, CLK2
MR
Q0 Q5
Function
Input Data a
Input Data b
Select Input
Clock Inputs
Master Reset
Data Outputs
MUX
D0b
SEL
D1a
MUX
11
D1b
SEL
Q0
D2a
MUX
D2b
SEL
D3a
MUX
D3b
SEL
D4a
MUX
D4b
D5a
D5b
FUNCTIONS
SEL
H
L
LOGIC DIAGRAM
D0a
* All VCC and VCCO pins are tied together on the die.
PIN NAMES
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
Data
a
b
SEL
CLK1
CLK2
MR
12/93
264
REV 2
SEL
Q0
Q1
Q2
Q3
Q4
Q5
R
D
R
D
R
D
R
D
SEL
MUX
R
D
R
MC10E167 MC100E167
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
Characteristic
IIH
IEE
min
typ
25C
max
min
typ
150
85C
max
min
typ
150
max
Unit
150
Condition
mA
94
94
113
113
94
94
113
113
94
108
113
130
Characteristic
min
typ
25C
max
min
typ
1000
1400
450
450
650
650
85C
max
min
typ
1000
1400
450
450
650
650
fMAX
1000
1400
tPLH
tPHL
450
450
650
650
ts
Setup Time
D
SEL
100
275
50
125
100
275
50
125
100
275
50
125
Hold Time
D
SEL
300
75
50
125
300
75
50
125
300
75
50
125
tRR
750
550
750
550
750
550
tPW
400
th
tSKEW
Within-Device Skew
tr
tf
Rise/Fall Times
20 - 80%
max
Unit
Condition
MHz
ps
800
850
800
850
800
850
ps
ps
ps
ps
400
75
400
75
75
ps
ps
300
450
800
300
450
800
300
450
800
265
MOTOROLA
MOTOROLA
MC10E171
MC100E171
3-BIT 4:1
MULTIPLEXER
D1a
D2d
D2c
D2b
D2a VCCO
25
24
23
22
21
20
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
19
SEL1A
26
18
Q2
SEL1B
27
17
Q2
SEL2
28
16
VCC
VEE
15
Q1
D0a
2:1
MUX
NC
14
Q1
D0b
SEL
NC
13
VCCO
D0c
D1c
12
Q0
2:1
MUX
D0d
SEL
D1a
2:1
MUX
D1b
D1c
D1d
D0a
D0b
D0c
10
D0d VCCO
Q0
PIN NAMES
Function
D0x D2x
SEL1A, SEL1B
SEL2
Q0 Q2
Q0 Q2
Data Inputs
First-stage Select Inputs
Second-stage Select Input
True Output
Inverted Output
FUNCTION TABLE
Pin
SEL2
SEL1A
SEL1B
H
H
H
2:1
MUX
Q1
2:1
MUX
SEL
Q1
SEL
2:1
MUX
Q2
2:1
MUX
SEL
2:1
MUX
D2b
D2d
SEL1A
SEL2
12/93
266
SEL
D2a
SEL1B
Q0
SEL
Operation
Output c/d data
Input d data
Input b data
Q0
SEL
D1d
D2c
State
2:1
MUX
11
* All VCC and VCCO pins are tied together on the die.
Pin
LOGIC DIAGRAM
REV 2
SEL
Q2
MC10E171 MC100E171
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
Characteristic
IIH
IEE
min
typ
25C
max
min
typ
150
85C
max
min
typ
150
max
Unit
150
Condition
mA
56
56
67
67
56
56
67
67
56
65
67
77
Characteristic
tPLH
tPHL
tSKEW
Within-Device Skew
Dnm, Dnm to Qn
Da, Db, Dc, Dd to Q
tr
tf
Rise/Fall Time
20 - 80%
25C
85C
min
typ
max
min
typ
max
min
typ
max
275
450
350
480
650
550
650
850
700
275
450
350
480
650
550
650
850
700
275
450
350
480
650
550
650
850
700
Unit
Condition
ps
ps
60
40
60
40
60
40
ps
300
475
650
300
475
650
300
475
650
1. Within-device skew is defined as identical transitions on similar paths through a device; n = 0,1,2 m = a,b,c,d.
267
MOTOROLA
MOTOROLA
MC10E175
MC100E175
9-BIT LATCH
WITH PARITY
9-Bit Latch
Parity Detection/Generation
800ps Max. D to Output
Reset
Extended 100E VEE Range of 4.2V to 5.46V
Internal 75k Input Pulldown Resistors
D7
D8
VCCO
Q8
Q7
VCCO
25
24
23
22
21
20
19
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
26
18
Q6
D4
27
17
Q5
D3
28
16
VCC
VEE
15
Q4
LEN
14
Q3
MR
13
VCCO
D2
12
Q2
10
11
D1
D0
VCCO
ODDPAR
D5
Q0
VCCO
Q1
LOGIC DIAGRAM
D0
D
EN
Q0
Q8
ODDPAR
BITS
17
D
D8
EN
* All VCC and VCCO pins are tied together on the die.
PIN NAMES
Pin
D0 D8
LEN
MR
Q0 Q8
ODDPAR
Function
EN
Data Inputs
Latch Enable
Master Reset
Data Outputs
Parity Output
R
LEN
MR
12/93
268
REV 2
MC10E175 MC100E175
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
Characteristic
IIH
IEE
min
typ
25C
max
min
typ
150
85C
max
min
typ
150
max
Unit
150
Cond
mA
110
110
132
132
110
110
132
132
110
127
132
152
Characteristic
min
typ
25C
max
min
typ
85C
max
min
tPLH
tPHL
450
850
525
525
525
525
600
1150
700
700
700
700
ts
Setup Time
D (Q)
D (ODDPAR)
275
900
100
700
275
900
275
900
Hold Time
D (Q)
D (ODDPAR)
175
300
100
70
175
300
175
300
850
600
850
th
max
Unit
Cond
ps
800
1450
900
900
900
900
450
850
525
525
525
525
600
1150
700
700
700
700
800
1450
900
900
900
900
450
850
525
525
525
525
600
1150
700
700
700
700
800
1450
900
900
900
900
ps
ps
tRR
tSKEW
Within-Device Skew
LEN, MR
D to Q
D to ODDPAR
tr
tf
typ
600
850
600
ps
ps
75
75
200
Rise/Fall Times
20 - 80%
75
75
200
75
75
200
ps
300
500
800
300
500
800
300
500
800
FUNCTION TABLE
D
EN
MR
H
L
X
X
L
L
H
X
L
L
L
H
H
L
Q0
L
ODDPAR
H if odd no. of Dn HIGH
H if odd no. of Dn HIGH
Q0
L
269
MOTOROLA
MOTOROLA
Error Detection/Correction
MC10E193
Circuit
MC100E193
ERROR DETECTION/
CORRECTION CIRCUIT
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
B INPUTS
03 6 574 2 1
LOGIC DIAGRAM
B2, B3, B6, B7
P2
EN
P1
25
B4, B5, B6, B7
P4
PGEN
BPAR
EV/OD
24
23
21
20
19
EV/OD
26
18
PARERR
BPAR
27
17
PARERR
B0
28
16
VCC
VEE
15
P5
B1
14
VCCO
B2
13
P4
B3
12
P3
P3
HOLD S-IN
PARERR
10
11
PARERR
B4
B5
B6
B7
VCCO
P1
P2
EN
* All VCC and VCCO pins are tied together on the die.
HOLD
S-IN
SHIFT
CLK
7/96
270
REV 3
MC10E193 MC100E193
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
Characteristic
IIH
IEE
min
typ
25C
max
min
85C
typ
max
150
min
typ
150
max
Unit
150
Condition
mA
112
112
134
134
112
112
134
134
112
129
134
155
Characteristic
25C
85C
min
typ
max
min
typ
max
min
typ
max
1000
1150
850
1450
850
350
400
350
600
300
700
775
650
1000
550
1000
1150
850
1450
850
350
400
350
600
300
700
775
650
1000
550
1000
1150
850
1450
850
tPLH
tPHL
350
400
350
600
300
700
775
650
1000
550
ts
Setup Time
SHIFT
S-IN
HOLD
EN
EV/OD
BPAR
B
400
300
750
500
1300
1300
1700
150
50
350
250
850
850
1100
400
300
750
500
1300
1300
1700
150
50
350
250
850
850
1100
400
300
750
500
1300
1300
1700
150
50
350
250
850
850
1100
Hold Time
SHIFT
S-IN
HOLD
EN
EV/OD
BPAR
B
200
300
100
100
200
200
300
150
50
350
250
850
850
1100
200
300
100
100
200
200
300
150
50
350
250
850
850
1100
200
300
100
100
200
200
300
150
50
350
250
850
850
1100
300
700
300
700
300
700
th
tr
tf
Rise/Fall Times
20 - 80%
Unit
Condition
ps
ps
ps
ps
1100
271
1100
1100
MOTOROLA
MOTOROLA
MC10E195
MC100E195
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
D3
D4
D5
D6
D7
NC
25
26 D1
24
23
22
21
20
19
NC 18
NC 17
27 D0
28 LEN
1 VEE
PIN NAMES
Function
Signal Input
Input Enable
Mux Select Inputs
Signal Output
Latch Enable
Min Delay Set
Max Delay Set
Cascade Signal
Q 14
3 IN
Q 13
4 VBB
VCCO 12
NC
NC
EN
10
CASCADE
IN/IN
EN
D[0:7]
Q/Q
LEN
SET MIN
SET MAX
CASCADE
VCCO 15
2 IN
SET MAX
Pin
VCC 16
Pinout:
28-Lead PLCC
(Top View)
11
CASCADE
D2
SET MIN
PROGRAMMABLE
DELAY CHIP
IN
IN
EN
* 1.25
0
1
0
1
4 GATES
8 GATES
16 GATES
0
1
* 1.5
0
1
Q
Q
CASCADE
LEN
LEN
SET MIN
SET MAX
D0
* DELAYS ARE 25% OR 50% LONGER THAN
* STANDARD (STANDARD 80 PS)
7 BIT LATCH
D1
D2
D3
LATCH
D
D4
D5
D6
D7
12/93
272
REV 2
CASCADE
CASCADE
MC10E195 MC100E195
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
Characteristic
IIH
IEE
Min
Typ
25C
Max
Min
Typ
150
85C
Max
Min
Typ
150
Max
Unit
150
Condition
mA
130
130
156
156
130
130
156
156
130
150
156
179
Characteristic
Min
Typ
tPLH
tPHL
Propagation Delay
IN to Q; Tap = 0
IN to Q; Tap = 127
EN to Q; Tap = 0
D7 to CASCADE
1210
3320
1250
300
1360
3570
1450
450
tRANGE
Programmable Range
tPD (max) tPD (min)
2000
2175
55
115
250
505
1000
17
34
68
136
272
544
1088
D1
D0
Step Delay
D0 High
D1 High
D2 High
D3 High
D4 High
D5 High
D6 High
ts
Setup Time
D to LEN
D to IN
EN to IN
200
800
200
Hold Time
LEN to D
IN to EN
500
0
250
Release Time
EN to IN
SET MAX to LEN
SET MIN to LEN
300
800
800
Jitter
tr
tf
Typ
Max
Min
Typ
Max
Unit
1510
3820
1650
700
1240
3380
1275
300
1390
3630
1475
450
2050
2240
55
115
250
515
1030
17.5
35
70
140
280
560
1120
D1
D0
1540
3880
1675
700
1440
3920
1350
300
1590
4270
1650
450
Notes
2375
2580
65
140
305
620
1240
21
42
84
168
336
672
1344
D1
D0
1765
4720
1950
700
ps
tSKEW
tjit
Min
ps
Linearity
tR
Max
85C
ps
Lin
th
25C
105
180
325
620
1190
30
105
180
325
620
1220
30
120
205
380
740
1450
7
ps
30
1
ps
200
800
200
500
0
250
200
800
200
500
0
250
2
3
ps
4
ps
300
800
800
<5.0
300
800
800
<5.0
<5.0
ps
ps
125
300
225
450
325
650
125
300
225
450
325
650
125
300
225
450
325
650
1. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output.
2. This setup time defines the amount of time prior to the input signal the delay tap of the device must be set.
3. This setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than
75 mV to that IN/IN transition.
4. This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output response
greater than 75 mV to that IN/IN transition.
5. This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets
the specified IN to Q propagation delay and transition times.
6. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations of
asserted delay control inputs will typically realize D0 resolution steps across the specified programmable range.
7. The linearity specification guarantees to which delay control input the programmable steps will be monotonic (i.e. increasing delay steps for
increasing binary counts on the control inputs Dn). Typically the device will be monotonic to the D0 input, however under worst case conditions
and process variation, delays could decrease slightly with increasing binary counts when the D0 input is the LSB. With the D1 input as the LSB
the device is guaranteed to be monotonic over all specified environmental conditions and process variation.
8. The jitter of the device is less than what can be measured without resorting to very tedious and specialized measurement techniques.
273
MOTOROLA
MC10E195 MC100E195
D7
D6
D5
D4
D1
D0
VCCO
Q
VEE
IN
IN
VCCO
E195
Chip #2
VCC
VCCO
Q
VBB
CASCADE
LEN
CASCADE
CASCADE
CASCADE
EN
VBB
SET MIN
IN
SET MAX
VEE
IN
VCC
SET MAX
E195
Chip #1
LEN
EN
D0
SET MIN
D1
INPUT
D3
D2
D7
D6
D5
D4
D3
D2
A7
OUTPUT
Q
VCCO
Chip #1 on the other hand will have both SET MIN and SET
MAX de-asserted so that its delay will be controlled entirely by
the address bus A0A6. If the delay needed is greater than
can be achieved with 31.75 gate delays (1111111 on the
A0A6 address bus) D7 will be asserted to signal the need to
cascade the delay to the next E195 device. When D7 is
asserted the SET MIN pin of chip #2 will be de-asserted and
the delay will be controlled by the A0A6 address bus. Chip #1
on the other hand will have its SET MAX pin asserted resulting
in the device delay to be independent of the A0A6 address
bus.
When the SET MAX pin of chip #1 is asserted the D0 and D1
latches will be reset while the rest of the latches will be set. In
addition, to maintain monotonicity an additional gate delay is
selected in the cascade circuitry. As a result when D7 of chip
#1 is asserted the delay increases from 31.75 gates to 32
gates. A 32 gate delay is the maximum delay setting for the
E195.
To expand this cascading scheme to more devices one
simply needs to connect the D7 input and CASCADE outputs
of the current most significant E195 to the new most significant
E195 in the same manner as pictured in Figure 1. The only
addition to the logic is the increase of one line to the address
bus for cascade control of the second PDC.
TO SELECT MULTIPLEXERS
BIT 0
D0
BIT 1
Q0
D1
BIT 2
Q1
LEN
LEN
Reset Reset
Reset Reset
D2
BIT 3
Q2
LEN
Reset Reset
D3
BIT 4
Q3
D4
BIT 5
Q4
D5
BIT 6
Q5
BIT 7
CASCADE
D6
Q6
D7
Q7
LEN
LEN
LEN
LEN
LEN
Reset Reset
Reset Reset
Reset Reset
Reset Reset
Reset Reset
CASCADE
SET MIN
SET MAX
MOTOROLA
274
MOTOROLA
MC10E196
MC100E196
PROGRAMMABLE
DELAY CHIP
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
PIN NAMES
Pin
Function
IN/IN
EN
D[0:7]
Q/Q
LEN
SET MIN
SET MAX
CASCADE
FTUNE
Signal Input
Input Enable
Mux Select Inputs
Signal Output
Latch Enable
Min Delay Set
Max Delay Set
Cascade Signal
Linear Voltage Input
FTUNE
11
IN
IN
EN
* 1.25
0
1
0
1
4 GATES
8 GATES
16 GATES
0
1
* 1.5
0
1
CASCADE
LEN
LEN
SET MIN
SET MAX
D0
* DELAYS ARE 25% OR 50% LONGER THAN
* STANDARD (STANDARD 80 PS)
7 BIT LATCH
D1
D2
D3
D5
D6
D7
12/93
275
LINEAR
RAMP
LATCH
D
D4
Q
Q
REV 2
CASCADE
CASCADE
MC10E196 MC100E196
D3
D4
D5
D6
D7
NC
25
24
23
22
21
20
19
18
FTUNE
D0
27
17
NC
LEN
28
16
VCC
VEE
15
VCCO
IN
14
IN
13
VBB
12
VCCO
NC
NC
EN
10
11
CASCADE
CASCADE
SET MAX
26
SET MIN
D1
Characteristic
IIH
IEE
Min
Typ
25C
Max
Min
Typ
150
85C
Max
Min
Typ
150
Max
150
Unit
Condition
A
mA
130
130
156
156
130
130
156
156
130
150
156
179
25C
85C
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
tPLH
tPHL
Propagation Delay
IN to Q; Tap = 0
IN to Q; Tap = 127
EN to Q; Tap = 0
D7 to CASCADE
1210
3320
1250
300
1360
3570
1450
450
1510
3820
1650
700
1240
3380
1275
300
1390
3630
1475
450
1540
3880
1675
700
1440
3920
1350
300
1590
4270
1650
450
1765
4720
1950
700
tRANGE
Programmable Range
tPD (max) tPD (min)
2000
2175
2050
2240
2375
2580
55
115
250
505
1000
17
34
68
136
272
544
1088
55
115
250
515
1030
17.5
35
70
140
280
560
1120
65
140
305
620
1240
21
42
84
168
336
672
1344
D1
D0
D1
D0
D1
D0
Step Delay
D0 High
D1 High
D2 High
D3 High
D4 High
D5 High
D6 High
Lin
Linearity
tSKEW
MOTOROLA
Unit
Notes
ps
ps
ps
105
180
325
620
1190
105
180
325
620
1220
120
205
380
740
1450
7
ps
30
30
276
30
MC10E196 MC100E196
AC CHARACTERISTICS (continued) (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
ts
th
tR
Characteristic
Min
Typ
Setup Time
D to LEN
D to IN
EN to IN
200
800
200
Hold Time
LEN to D
IN to EN
500
0
250
Release Time
EN to IN
SET MAX to LEN
SET MIN to LEN
300
800
800
25C
Max
Min
Typ
200
800
200
500
0
250
85C
Max
Min
Typ
200
800
200
500
0
250
Max
Unit
Notes
ps
2
3
ps
tjit
Jitter
tr
tf
4
ps
300
800
800
<5.0
300
800
800
<5.0
<5.0
ps
ps
125
300
225
450
325
650
125
300
225
450
325
650
125
300
225
450
325
650
1. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output.
2. This setup time defines the amount of time prior to the input signal the delay tap of the device must be set.
3. This setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than
75 mV to that IN/IN transition.
4. This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output response
greater than 75 mV to that IN/IN transition.
5. This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets
the specified IN to Q propagation delay and transition times.
6. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations of
asserted delay control inputs will typically realize D0 resolution steps across the specified programmable range.
7. The linearity specification guarantees to which delay control input the programmable steps will be monotonic (i.e. increasing delay steps for
increasing binary counts on the control inputs Dn). Typically the device will be monotonic to the D0 input, however under worst case conditions
and process variation, delays could decrease slightly with increasing binary counts when the D0 input is the LSB. With the D1 input as the LSB
the device is guaranteed to be monotonic over all specified environmental conditions and process variation.
8. The jitter of the device is less than what can be measured without resorting to very tedious and specialized measurement techniques.
100
90
PROPAGATION DELAY (ps)
120
100
80
60
40
80
70
60
50
40
30
20
20
0
4.5
10
3.5
2.5
1.5
0
5
0.5
277
MOTOROLA
MC10E196 MC100E196
USING THE FTUNE ANALOG INPUT
The analog FTUNE pin on the E196 device is intended to
enhance the 20 ps resolution capabilities of the fully digital
E195. The level of resolution obtained is dependent on the
number of increments applied to the appropriate range on the
FTUNE pin.
To provide another level of resolution the FTUNE pin must
be capable of adjusting the delay by greater than the 20 ps
digital resolution. From the provided graphs one sees that this
requirement is easily achieved as over the entire FTUNE
voltage range a 100 ps delay can be achieved. This extra
analog range ensures that the FTUNE pin will be capable even
under worst case conditions of covering the digital
resolution.Typically the analog input will be driven by an
external DAC to provide a digital control with very fine analog
output steps. The final resolution of the device will be
dependent on the width of the DAC chosen.
To determine the voltage range necessary for the FTUNE
input, the graphs provided should be used. As an example if a
range of 40 ps is selected to cover worst case conditions and
ensure coverage of the digital range, from the 100E196 graph
a voltage range of 3.25 V to 4.0 V would be necessary on the
FTUNE pin. Obviously there are numerous voltage ranges
which can be used to cover a given delay range, users are
given the flexibility to determine which one best fits their
designs.
Cascading Multiple E196s
To increase the programmable range of the E196 internal
cascade circuitry has been included. This circuitry allows for
the cascading of multiple E196s without the need for any
external gating. Furthermore this capability requires only one
more address line per added E196. Obviously cascading
multiple PDCs will result in a larger programmable range,
however, this increase is at the expense of a longer minimum
delay.
Figure 1 illustrates the interconnect scheme for cascading
two E196s. As can be seen, this scheme can easily be
VEE
IN
IN
VCC0
D7
D6
D5
D3
D4
E196
Chip #2
VCC
VCC0
Q
VBB
CASCADE
CASCADE
EN
VBB
CASCADE
IN
SET MIN
INPUT
SET MAX
VEE
IN
LEN
CASCADE
VCC
VCC0
SET MAX
E196
Chip #1
FTUNE
SET MIN
D0
EN
LEN
D1
FTUNE
D1
D0
D2
D7
D6
D5
D4
D3
D2
A7
OUTPUT
VCC0
MOTOROLA
278
MC10E196 MC100E196
TO SELECT MULTIPLEXERS
BIT 0
D0
BIT 1
Q0
D1
BIT 2
Q1
D2
BIT 3
Q2
D3
BIT 4
Q3
D4
BIT 5
Q4
D5
BIT 6
Q5
BIT 7
CASCADE
D6
Q6
LEN
LEN
LEN
LEN
LEN
LEN
LEN
Reset Reset
Reset Reset
Reset Reset
Reset Reset
Reset Reset
Reset Reset
Reset Reset
D7
Q7
CASCADE
LEN
Reset Reset
SET MIN
SET MAX
279
MOTOROLA
MOTOROLA
Advance Information
Data Separator
MC10E197
DATA SEPARATOR
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
REFCLK
CAP1
CAP2
VCOIN
EXTVCO
INTERNAL
VCO
PHASE
DETECTOR
MUX
VCO
MUX
DATA
PHASE
DETECTOR
ENVCO
RAWD
ACQ
TYPE
PUMPDN
RSETDN
CLOCK &
DATA
BUFFER
ACQUISITION
CIRCUITRY
12/93
280
PUMPUP
RSETUP
This document contains information on a new product. Specifications and information herein are subject to
change without notice.
CHARGE
PUMP
CURRENTSOURCES
REV 2
RDATA
RDCLK
MC10E197
VCOIN
NC
VCCVCO
CAP2
CAP1
VCCVCO
VCCO0
25
24
23
22
21
20
19
RDCLK
ENVCO
28
16
VCC
VEE
15
RSDATA
ACQ
14
RSDATA
TYPE
13
PUMPUP
RDEN
12
RSETDN
10
11
VCCO1
17
RSETUP
27
PUMPDN
EXTVCO
RAWD
RDCLK
RAWD
18
RFFCLK
26
RFFCLK
TEST
PIN DESCRIPTIONS
REFCLK
RDEN
Enable data synchronizer when HIGH. When LOW enable the phase/frequency detector steered by REFCLK.
RAWD
VCOIN
CAP1/CAP2
ENVCO
VCO select pin. LOW selects the internal VCO and HIGH selects the external VCO input. Pin floats LOW when left open.
EXTVCO
ACQ
Acquisition circuitry select pin. This pin must be driven HIGH at the end of the data sync field for some sync field types.
TYPE
Selects between the two types of commonly used sync fields. When LOW it selects a sync field interspersed with 3 zeroes
(2:7 RLL code). When HIGH it selects a sync field interspersed with 2 zeroes (1:7 RLL code).
TEST
Input included to initialize the clock flip-flop for test purposes only. Pin should be left open (LOW) in actual application.
PUMPUP
PUMPDN
RSETUP
RSETDN
RDATA
RDCLK
VCC, VCCO,
VCCVCO
Most positive supply rails. Digital and analog supplies are independent on chip
VEE, VEEVCO
Most negative supply rails. Digital and analog supplies are independent on chip
281
MOTOROLA
MC10E197
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND or VCC = 4.75V to 5.25V; VEE = GND)
0C
Symbol
Characteristic
min
IIH
IIL
IEE
90
ISET
0.5
IOUT
VACT
PUMPUP/PUMPDN
Active Voltage Range
25C
typ
max
min
85C
typ
max
150
0.5
180
90
0.5
max
Unit
Condition
150
0.5
150
180
90
0.5
1
VCC 2.5
typ
150
0.5
150
min
150
180
mA
mA
VCC
VCC
VCC 2.5
VCC
VCC 2.5
Characteristic
min
25C
typ
max
min
typ
85C
max
min
typ
max
Unit
VOH
1020
840
980
810
910
720
mV
VOL
1950
1630
1950
1630
1950
1595
mV
VIH
1170
840
1130
810
1060
720
mV
VIL
1950
1480
1950
1480
1950
1445
mV
Condition
Characteristic
min
typ
25C
typ
85C
max
min
max
min
max
Unit
VOH
3980
4160
4020
4190
4090
typ
4280
mV
VOL
3050
3370
3050
3370
3050
3405
mV
VIH
3830
4160
3870
4190
3940
4280
mV
VIL
Input LOW Voltage
3050
1. *VOH and VOL levels will vary 1:1 with VCC
3520
3050
3050
3050
3555
mV
Condition
AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND or VCC = 4.75V to 5.25V; VEE = GND)
0C
Symbol
Characteristic
min
25C
max
min
85C
Unit
Condition
ts
TVCO 550
TVCO 500
TVCO 500
ps
4,7
tH
TVCO
TVCO
TVCO
ps
4,7
tSKEW
fVCO
150
Tuning Ratio
1.53
300
max
300
150
1.87
min
1.53
max
300
150
1.87
1.53
ps
MHz
1.87
5
6
MOTOROLA
282
MC10E197
RDATA
RDATA
RDCLK
tH
tS
RDCLK
APPLICATIONS INFORMATION
General Operation
Operation
The E197 is a phase-locked loop circuit consisting of an
internal VCO, a Data Phase detector with associated
acquisition circuitry, and a Phase/Frequency detector (Figure
1). In addition, an enable pin(ENVCO) is provided to disable
the internal VCO and enable the external VCO input. Hence,
the user has the option of supplying the VCO signal.
The E197 contains two phase detectors: a data phase
detector for synchronizing to the non-periodic pulses in the
read data stream during the data read mode of operation, and
a phase/ frequency detector for frequency (and phase) locking
to an external reference clock during the idle mode of
operation. The read enable (RDEN) pin muxes between these
two detectors.
Data Read Mode
The data pins (RAWD) are enabled when the RDEN pin is
placed at a logic high level, thus enabling the Data Phase
detector (Figure1) and initiating the data read mode. In this
mode, the loop is servoed by the timing information taken from
the positive edges of the input data pulses. This phase
detector samples positive edges from the RAWD signal and
generates both a pump up and pump down pulse from any
edge of the input data pulse. The leading edge of the pump up
pulse is time modulated by the leading edge of the data signal,
whereas the rising edge of the pump up pulse is generated
synchronous to the VCO clock. The falling edge of the pump
down pulse is synchronous to the falling edge of the VCO
clock and the rising edge of the pump down signal is
synchronous to the rising edge of the VCO clock. Since both
edges of the VCO are used the internal clock a duty cycle of
50%. This pulse width modulation technique is used to
generate the servoing signal which drives the VCO. The pump
down signal is a reference pulse which is included to provide
an evenly balanced differential system, thereby allowing the
synthesis of a VCO input control signal after appropriate signal
processing by the loop filter.
283
MOTOROLA
MC10E197
Idle Mode
In the absence of data or when the drive is writing to the disk,
PLL servoing is accomplished by pulling the read enable line
(RDEN) low and providing a reference clock via the REFCLK
pins. The condition whereby RDEN is low selects the
Phase/Frequency detector (Figure 1) and the 10E197 is said
to be operating in the idle mode. In order to function as a
frequency detector the input waveform must be periodic. The
pump up and pump down pulses from the Phase/Frequency
detector will have the same frequency, phase and pulse width
only when the two clocks that are being compared have their
positive edges aligned and are of the same frequency.
As with the data phase detector, by using suitable external
filter circuitry, a VCO input control signal can be generated by
inverting the pump down signal, summing the inverted signal
with the pump up signal and averaging the result. The polarity
PHASE
DETECTOR
Kf
Fi
Xi(s)
Xe(s)
A(s)
Ko
s
Fo
Xo(s)
K Ko F(s)
s
1 + K Ko F(s)
s
where:
K =
Ko=
(s)
VCO
LOOP FILTER
F(s)
Gain Constants
The transfer function for this closed loop system is
Xo(s)
Xi(s)
A(s)
1 + A(s)(s)
MOTOROLA
284
MC10E197
Kfc = K1 * Kl * Kd
Loop Filter
Code Sequence
00
01
1000
0100
100
101
111
001000
100100
000100
1100
1101
00001000
00100100
The two major functions of the loop filter are to remove any
noise or high frequency components present in the phase
detector output signal and, more importantly, to control the
characteristics which determine the dynamic response of the
phase lock loop; i.e. capture range, loop bandwidth, capture
time, and transient response.
Although a variety of loop filter configurations exist, this
section will only describe a filter capable of performing the
signal processing as described in the Data Read Mode and
the Idle Mode sections. The loop filter consists of a differential
summing amplifier cascaded with an augmenting integrator
which drives the VCOIN input to the 10E197 through a resistor
divider network (Figure 3).
The transfer function and the element values for the loop
filter are derived by dividing the filter into three cascaded
subsections: filter input, augmenting integrator, and the
voltage divider network (Figure 4).
Code Sequence
00
01
10
X01
010
X00
1100
1101
1110
1111
010001
X00000
X00001
010000
Read Mode
Idle Mode
2:7
121 mV/radian
484 mV/radian
1:7
161 mV/radian
483 mV/radian
The open loop transfer function of the phase lock loop is the
product of each individual filter subsection, as well as the
phase detector and VCO. Thus, the open loop filter transfer
function is:
Fo(s) = K * Ko * F1(s) * Fl(s) * Fd(s)
s
where:
1
F1(s) = K1 *
*
(s + p1)
Fl(s) = Kl *
1
s
Fd(s) = Kd *
1
(s + p2)
R1
eqt. 2
R1
RIA
RA
1
2 ]
[s2 + (2 o1) s + o1
(s + z)
2
[s + (2o2 ) s + 2o2 ]
CA
PUMPUP
CIN
RV
MC34182
MC34182
VEEVCO
RO
R3
R1
PUMPDN
CIN
VEEVCO
CO
VO
DB
VCCVCO
R1
VEEVCO
VEEVCO
VCCVCO
285
MOTOROLA
MC10E197
Fi(s)
FILTER
INPUT
F1(s)
AUGMENTNG
INTEGRATOR
FI(s)
VOLTAGE
DIVIDER
FO(s)
F(s)=F1(s)Fi(s)Fd(s)
1
1
F1(s) = K1 *
*
2
2
[s
+
(2
(s + p1)
o1) s + o1]
K1 = A1 *
R1
VEEVCO
eqt. 3
where:
A1= op-amp gain constant for the
selected pole positions.
CIN = phase detector shunt capacitor.
The real pole is a function of the input resistance to the
op-amp and the shunt capacitors connected to the phase
detector output. For stability the real pole must be placed
beyond the unity gain frequency; hence, this pole is typically
placed midway between the unity crossover and phase
detector sampling frequency, which should be about ten
times greater.
R1
IPUMPUP
VEEVCO
1
CIN
MC34182
RSETDN
RSETUP
R1
CIN
IPUMPDN
VEEVCO
VEEVCO
V01
464
464
464
464
R1
VCCVCO
VEEVCO
ELECTRONIC SWITCH
Filter Input
VEEVCO
MOTOROLA
286
MC10E197
the poles lie beyond the crossover frequency and they are
positioned for near unity gain operation. Performing a root
locus analysis on the op-amp open loop configuration and
adhering to the two constraints yields the pole positions
contributed by the op-amp.
Determination of Element Values
Since the difference amplifier is configured to operate as a
differential summer the resistor values associated with the
amplifier are of equal value. Further, the typical input
resistance to the summing amplifier is 1k; thus, the op-amp
resistors are set at 1 k. Having set the input resistance to the
op-amp and selected the position of the real pole, the value of
the shunt capacitors is determined using the following
relationship:
p1 =
1
2R1CIN
eqt. 4
Augmenting Integrator
The augmenting integrator consists of an active filter with a
lag-lead network in the feedback path (Figure 7).
RIA
CA
RA
VIN
1
2RACA
eqt. 6
MC34182
VO2
RIA
VCCVCO
1
s
Voltage Divider
(s + z)
[s2 + (2o2 ) s + 2o2 ]
eqt. 5
where:
Al =
eqt. 7
RO
Cd
DB
VO
287
MOTOROLA
MC10E197
In addition, a shunt filter capacitor connected between the
VCOIN input pin and VEE provides the voltage divider
subsection with a single time constant transfer function that
adds a pole to the overall loop filter. The transfer function for
the voltage divider network is:
1
Fd(s) = Kd *
(s + p2)
The gain constant, Kd, is defined as:
Kd =
1
Rv Cd
eqt. 9
Kd =
Kol
K * Ko * K1 * Kl
Ro
R o + Rv
eqt. 10
The gain constant Kd is set such that the output from the
integrator circuit is within the range 1.3V +VEE to 2.6V +VEE.
MOTOROLA
Kd
2 p2
1
Rv Kd
eqt. 9a
288
MC10E197
Static Poles
Dynamic Zero
Finally, the zero is positioned much less than one decade
before the crossover frequency; for this design the zero is
placed at:
z = 311Hz
Once the dynamic pole and zero positions have been
determined, the phase margin is determined using a Bode
plot; if the phase margin is not sufficient, the dynamic poles
may be moved to improve the phase margin. Finally, a root
locus analysis is performed to obtain the optimum closed loop
pole positions for the dynamic characteristics of interest.
Component Values
P*1a = 0.1Hz
P2 = 3.06MHz
P*1b = 11.2Hz
z = 311Hz
P1 = 573kHz
Rearranging Equation 4:
V
V
CIN =
1
2 R1 p1
and substituting 573 kHz for the pole position and 1 k for
the resistor value yields:
CIN = 278 pF
Dynamic Poles
Rearranging Equation 6:
1
2 z
CA
and substituting 311Hz for the zero position and 0.1F for the
capacitor value yields:
P*1 = 1.24MHz
RA = 5.11k
RA =
289
MOTOROLA
MC10E197
From Equation 7 the value for the other resistors associated
with the integrator op-amp are set equal to RA:
RlA = RA = 5.11k
V
mA sec3
Cd = 98pF
Note that the voltage divider section can be used to set the
gain, but the designer is cautioned to be sure the input
value to VCOIN is within the correct range.
Component Scaling
As mentioned, these design equations were developed for
a data rate of 23 Mbit/sec. If the data rate is different from the
nominal design value the reactive elements must be scaled
accordingly. The following equations are provided to facilitate
scaling and were derived with the assumptions that a 2:7
coding scheme is used and that the RDCLK signal is twice the
frequency of the data clock.
CIN = 278 *
From Equation 3
1
CIN
K1 = A1 *
Cd = 98 *
K1 = 8.90 e21
V
mA sec
From Equation 5
Kl = Al *
RA
RlA
46
f
(pF)
eqt. 11
(pF)
eqt. 12
V
V
Kl = 2.48 e15
Cd = 205pF
Thus the element values for the filter are:
Filter Input Subsection:
CIN = 581pF
R1 = 1k
Ro
R o + Rv
Integrator Subsection:
CA = 0.1F
RA = 5.11k
P2 = 3.06MHz
Hence, Rv is selected to be:
RlA = 5.11k
Voltage Divider Subsection:
Rv = 2.15k
Cd = 205pF
Rv = 2.15k
Ro = 700
MOTOROLA
46
f
Kd
2 p2
eqt. 8a
Kd =
1
Rv Kd
Ro = 700k
290
MC10E197
Note, the poles P1 and P2 are now located at:
P1 = 274kHz
P2 = 1.47MHz
Dynamic Zero
Component Values
Having determined the closed loop pole and zero positions
the component values are calculated. From the root locus
analysis the dynamic pole and zero positions are:
Static Poles
As in the 2:7 coding example, an MC34182D op-amp is
employed, hence the pole set is:
P1 = 541kHz
P2 = 2.73MHz
z = 311Hz
Rearranging Equation 4
V
V
CIN =
Since the op-amps introduce a set of complex conjugate
poles, a total of four poles are introduced by the op-amp. In
addition, the integrator and the VCO each contribute a pole at
the origin for a total of six static poles.
Dynamic Poles
1
2 R1 p1
and substituting 541kHz for the pole position and 1.0k for
the resistor value yields:
CIN = 294 pF
Rearranging Equation 6
RA =
1
2 z CA
and substituting 311Hz for the zero position and 0.1F for the
capacitor value yields:
RA = 5.11k
P*2 = 2.28MHz
RlA = RA = 5.11k
291
MOTOROLA
MC10E197
Finally, using Equation 8a:
MA
SEC3
From Equation 3:
K1 = A1 *
1
CIN
Cd =
1
Rv Kd
eqt. 8a
Component Scaling
As mentioned, these design equations were developed for
a data rate of 20Mbit/sec. If the data rate is different from the
nominal design value the reactive elements must be scaled
accordingly. The following equations provided are to facilitate
scaling and were derived with the assumptions that a 1:7
coding scheme is used and that the RDCLK signal is twice the
frequency of the data clock:
CIN = 294 *
30
f
(pF)
eqt. 13
Cd = 156 *
30
f
(pF)
eqt. 14
RA
RlA
V
V
Kd = 2.98 e6 sec 1
Having determined the gain constant Kd , the value of Rv, is
selected such that the constraints Rv > Ro and:
Kd
2p2
Ro
=
R o + Rv
R1 = 1.0k
P2 = 2.73MHz
Hence, Rv is selected to be:
Integrator Subsection:
CA = 0.1F
Rv = 2.15k
RA = 5.11k
RlA = 5.11k
Ro = 453
MOTOROLA
292
MC10E197
P1 = 271kHz
P2 = 1.36MHz
And, the open loop filter unity crossover point is at 300kHz.
As in the case of the 2:7 coding scheme, the gain can be
adjusted by changing the value of RlA and the value of Cd.
Varying the gain by changing Cd is not recommended
because this will also move the poles, hence affect the
dynamic performance of the filter.
293
MOTOROLA
MOTOROLA
MC100E210
ECL/PECL Compatible
LOW VOLTAGE
DUAL 1:4, 1:5 DIFFERENTIAL
FANOUT BUFFER
FN SUFFIX
PLASTIC PACKAGE
CASE 77602
MOTOROLA
294
MOTOROLA
MC10E211
MC100E211
1:6 DIFFERENTIAL
CLOCK DISTRIBUTION CHIP
The E211 features a multiplexed clock input to allow for the distribution
of a lower speed scan or test clock along with the high speed system
clock. When LOW (or left open in which case it will be pulled LOW by the
input pulldown resistor) the SEL pin will select the differential clock input.
Both a common enable and individual output enables are provided. When asserted the positive output will go LOW on the next
negative transition of the CLK (or SCLK) input. The enabling function is synchronous so that the outputs will only be
enabled/disabled when the outputs are already in the LOW state. In this way the problem of runt pulse generation during the
disable operation is avoided. Note that the internal flip flop is clocked on the falling edge of the input clock edge, therefore all
associated specifications are referenced to the negative edge of the CLK input.
The output transitions of the E211 are faster than the standard ECLinPS edge rates. This feature provides a means of
distributing higher frequency signals than capable with the E111 device. Because of these edge rates and the tight skew limits
guaranteed in the specification, there are certain termination guidelines which must be followed. For more details on the
recommended termination schemes please refer to the applications information section of this data sheet.
FUNCTION TABLE
CLK
SCLK
SEL
ENx
H/L
X
Z*
X
H/L
Z*
L
H
X
L
L
H
CLK
SCLK
L
295
REV 3
MC10E211 MC100E211
EN4
EN5
VCC0
Q5
Q5
Q4
Q4
25
24
23
22
21
20
19
EN3
26
18
Q3
SEL
27
17
Q3
SCLK
28
16
VCC
VEE
15
Q2
CLK
14
Q2
CLK
13
Q1
VBB
12
Q1
10
11
CEN
EN2
EN1
EN0
VCC0
Q0
Q0
Q0
Q0
EN0
CLK
DQ
BITS 1-4
0
Q1-4
Q1-4
CLK
SCLK
SEL
DQ
EN1-4
CEN
Q5
Q5
EN5
DQ
VBB
Logic Diagram
MOTOROLA
296
MC10E211 MC100E211
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Characteristic
Output Reference Voltage
10E
100E
Symbol
Min
Typ
25C
Max
Min
1.27
1.26
1.35
1.38
Typ
85C
Max
Min
1.25
1.26
1.31
1.38
Typ
Max
VBB
IIH
IEE
Condition
V
1.38
1.38
Unit
150
1.19
1.26
150
150
A
mA
119
119
160
160
119
119
160
160
119
137
160
164
Symbol
tPLH
tPHL
Disable Time
CLK or SCLK to Q
tPHL
ParttoPart Skew
CLK (Diff) to Q
CLK (SE), SCLK to Q
Within-Device Skew
tskew
ts
Hold Time
CLK to ENx, CEN
th
85C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
795
745
650
745
930
930
900
970
1065
1115
1085
1195
805
755
650
755
940
940
910
980
1075
1125
1095
1205
825
775
650
775
960
960
930
1000
1095
1145
1115
1225
600
800
600
800
600
800
Unit
Condition
ps
ps
2
ps
50
Setup Time
ENx to CLK
CEN to CLK
25C
270
370
75
50
270
370
75
270
370
75
1
ps
200
200
100
0
200
200
100
0
200
200
100
0
2
ps
900
600
900
160
900
600
VPP
0.25
1.0
0.25
1.0
0.25
1.0
VCMR
0.4
Note
0.4
Note
0.4
Note
Rise/Fall Times
20 80%
1.
2.
3.
4.
tr
ps
tf
150
400
150
400
150
400
Within-Device skew is defined for identical transitions on similar paths through a device.
Setup, Hold and Disable times are all relative to a falling edge on CLK or SCLK.
Minimum input swing for which AC parameters are guaranteed. Full DC ECL output swings will be generated with only 50mV input swings.
The range in which the high level of the input swing must fall while meeting the VPP spec. The lower end of the range is VEE dependent and
can be calculated as VEE + 2.4V.
297
MOTOROLA
MC10E211 MC100E211
APPLICATIONS INFORMATION
General Description
The MC10E/100E211 is a 1:6 fanout tree designed
explicitly for low skew high speed clock distribution. The
device was targeted to work in conjunction with the E111
device to provide another level of flexibility in the design and
implementation of clock distribution trees. The individual
synchronous enable controls and multiplexed clock inputs
make the device ideal as the first level distribution unit in a
distribution tree. The device provides the ability to distribute a
lower speed scan or test clock along with the high speed
system clock to ease the design of system diagnostics and
self test procedures. The individual enables could be used to
allow for the disabling of individual cards on a backplane in
fault tolerant designs.
Because of lower fanout and larger skews the E211 will
not likely be used as an alternative to the E111 for the bulk of
the clock fanout generation. Figure 1 shows a typical
application combining the two devices to take advantage of
the strengths of each.
E111
Q0
E211
BACKPLANE
Q0
Q8
E111
Q5
Q0
Q8
MOTOROLA
298
MC10E211 MC100E211
APPLICATIONS INFORMATION
Differential versus Single-Ended Use
As can be seen from the data sheet, to minimize the skew
of the E211 the device must be used in the differential mode.
In the single-ended mode the propagation delays are
dependent on the relative position of the VBB switching
reference. Any VBB offset from the center of the input swing
will add delay to either the TPLH or TPHL and subtract delay
from the other. This increase and decrease in delay will lead
to an increase in the duty cycle skew and thus part-to-part
skew. The within-device skew will be independent of the VBB
and therefore will be the same regardless of whether the
device is driven differentially or single-endedly.
IN
0.001F
50
IN
0.01F
VBB
IN
IN
0.01F
VBB
299
MOTOROLA
MOTOROLA
MC10E212
MC100E212
3-BIT SCANNABLE
REGISTERED
ADDRESS DRIVER
26
19
18
Q2b
CLK
27
17
Q2a
D2
28
16
VCC
VEE
15
Q1b
D1
14
Q1a
D0
13
Q1b
S-IN
12
Q1a
24
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
23
22
21
20
10
LOGIC DIAGRAM
S-OUT
Q2b
Q2a
D
Q
D2
Q2a
Q2b
11
Q1b
Q1a
D
Q
D1
Q1a
Q1b
PIN NAMES
Pin
D0 D2
S-IN
LOAD
SHIFT
CLK
MR
S-OUT
Q[0:2]a, Q[0:2]b
Q[0:2]a, Q[0:2]b
Function
Data Inputs
Scan Input
LOAD/HOLD Control
Scan Control
Clock
Reset
Scan Output
True Outputs
Inverting Outputs
Q
D0
Q0a
Q0b
S-IN
LOAD
SHIFT
CLK
MR
12/93
Q0b
Q0a
2100
REV 2
MC10E212 MC100E212
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
Characteristic
IIH
IEE
min
typ
25C
max
min
typ
150
85C
max
min
typ
150
max
Unit
150
Condition
mA
80
80
96
96
80
80
96
96
80
92
96
110
Characteristic
25C
85C
min
typ
max
min
typ
max
min
typ
max
1025
1025
1025
575
575
575
800
800
800
1025
1025
1025
575
575
575
800
800
800
1025
1025
1025
Unit
Condition
tPLH
tPHL
575
575
575
800
800
800
ts
Setup Time
D
SHIFT
LOAD
S-IN
175
150
225
150
25
50
50
50
175
150
225
150
25
50
50
50
175
150
225
150
25
50
50
50
Hold Time
D
SHIFT
LOAD
S-IN
250
300
225
300
25
100
0
100
250
300
225
300
25
100
0
100
250
300
225
300
25
100
0
100
tRR
Reset Recovery
600
350
600
350
600
350
ps
tSKEW
Within-Device Skew
100
100
100
ps
tSKEW
Within-Gate Skew
50
50
50
ps
tr
tf
Rise/Fall Times
20 - 80%
th
ps
ps
ps
ps
275
425
650
275
425
650
275
425
650
FUNCTION TABLE
LOAD
SHIFT
MR
MODE
L
H
X
X
L
L
H
X
L
L
L
H
Load
Hold
Shift
Reset
2101
MOTOROLA
MOTOROLA
MC10E241
MC100E241
8-BIT SCANNABLE
REGISTER
NC
D7
D6
D5
VCCO
Q7
25
24
23
22
21
20
19
SEL1
26
18
Q6
CLK
27
17
Q5
MR
28
16
VCC
VEE
15
NC
S-IN
14
VCCO
D0
13
Q4
D1
12
Q3
10
11
D2
D3
D4
VCCO
Q0
Q1
Q2
LOGIC DIAGRAM
S-IN
D Q
D0
D Q
D1 D6
* All VCC and VCCO pins are tied together on the die.
Q0
Q1 Q6
R
BITS 16
PIN NAMES
Pin
D0 D7
S-IN
SEL0
SEL1
CLK
MR
Q0 Q7
Function
D Q
D7
HOLD/LOAD
SHIFT
CLK
MR
7/96
2102
REV 3
Q7
MC10E241 MC100E241
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
Characteristic
IIH
IEE
min
typ
25C
max
min
typ
150
85C
max
min
typ
150
max
Unit
150
Condition
MA
125
125
150
150
125
125
150
150
125
144
150
173
Characteristic
min
typ
25C
max
min
typ
700
900
625
600
750
725
85C
max
min
typ
700
900
625
600
750
725
fSHIFT
700
900
tPLH
tPHL
625
600
750
725
ts
Setup Time
D
SEL0 (SHIFT)
SEL1 (HOLD/LOAD)
S-IN
175
350
400
125
25
200
250
100
175
350
400
125
25
200
250
100
175
350
400
125
25
200
250
100
Hold Time
D
SEL0 (SHIFT)
SEL1 (HOLD/LOAD)
S-IN
200
100
50
300
25
200
250
100
200
100
50
300
25
200
250
100
200
100
50
300
25
200
250
100
tRR
900
600
900
600
900
600
tPW
400
th
tSKEW
Within-Device Skew
tr
tf
Rise/Fall Times
20 - 80%
max
Unit
Condition
MHz
ps
975
975
975
975
975
975
ps
ps
ps
ps
400
60
400
60
60
ps
ps
300
525
800
300
525
800
300
525
800
FUNCTION TABLE
MR
SEL0
SEL1
1
0
0
0
X
1
0
0
X
X
1
0
Function
Outputs LOW
Shift Data
Hold Data
Load Data
2103
MOTOROLA
MOTOROLA
MC10E256
MC100E256
3-BIT 4:1
MUX-LATCH
D1a
D2d
D2c
D2b
25
24
23
22
21
D2a VCCO
20
19
SEL1A
26
18
Q2
SEL1B
27
17
Q2
SEL2
28
16
VCC
VEE
15
Q1
LEN
14
Q1
MR
13
VCCO
D1c
12
Q0
D1d
D0a
D0b
D0c
10
D0d VCCO
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
11
Q0
* All VCC and VCCO pins are tied together on the die.
FUNCTION TABLE
Pin
SEL2
SEL1A
SEL1B
State
H
H
H
PIN NAMES
Operation
Output c/d Data
Input d Data
Input b Data
Pin
Function
D0x D2x
SEL1A, SEL1B
SEL2
LEN
MR
Q0, Q0 Q2, Q2
12/93
2104
REV 2
Data Inputs
First-stage Select Inputs
Second-stage Select input
Latch Enable
Master Reset
Data Outputs
MC10E256 MC100E256
LOGIC DIAGRAM
D0a
D0b
D0c
Q0
EN
R
Q0
Q1
EN
R
Q1
Q2
EN
R
Q2
D0d
D1a
D1b
D1c
D1d
D2a
D2b
D2c
D2d
SEL1A
SEL1B
SEL2
LEN
MR
Characteristic
IIH
IEE
min
typ
25C
max
min
typ
150
85C
max
min
typ
150
max
Unit
150
Condition
mA
69
69
83
83
2105
69
69
83
83
69
79
83
96
MOTOROLA
MC10E256 MC100E256
AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
Characteristic
25C
85C
min
typ
max
min
typ
max
min
typ
max
900
1050
900
800
825
400
550
450
350
350
600
775
650
500
600
900
1050
900
800
825
400
550
450
350
350
600
775
650
500
600
900
1050
900
800
825
tPLH
tPHL
400
550
450
350
350
600
775
650
500
600
ts
Setup Time
D
SEL1
SEL2
400
600
500
275
300
250
400
600
500
275
300
250
400
600
500
275
300
250
Hold Time
D
SEL1
SEL2
300
100
200
275
300
250
300
100
200
275
300
250
300
100
200
275
300
250
tRR
700
600
700
600
700
600
tPW
400
th
tSKEW
Within-Device Skew
tr
tf
Rise/Fall Times
20 - 80%
Unit
Condition
ps
ps
ps
ps
ps
400
50
400
50
50
ps
ps
275
475
700
275
475
700
275
475
700
MOTOROLA
2106
MOTOROLA
Product Preview
MC100E310
Fanout Buffer
ECL/PECL Compatible
LOW VOLTAGE
2:8 DIFFERENTIAL
FANOUT BUFFER
FN SUFFIX
PLASTIC PACKAGE
CASE 77602
2107
MOTOROLA
MOTOROLA
MC10E336
MC100E336
3-BIT REGISTERED
24
B2
23
A2
22
NC
21
VCCO
20
Q2
19
26
18
GND
A0
B0
D Q
25 CUTOFF
D
Q
BUSEN2
27
17
BUS2
RXEN
28
16
VCC
VEE
15
Q1
CLK1
14
VCCO
CLK2
13
BUS1
A0
12
5
B0
A1
B1
10
GND
11
Q0
* All VCC and VCCO pins are tied together on the die.
0
A1
B1
50
Q
0
A2
B2
D Q
25 CUTOFF
D
50
Q
TEN1
TEN2
RXEN
BUSEN1
BUSEN2
D Q
12/93
2108
25 CUTOFF
D
CLK1
CLK2
D Q
50
REV 2
BUS0
Q0
BUS1
Q1
BUS2
Q2
MC10E336 MC100E336
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
Characteristic
VCUT
IIH
IEE
min
typ
2.10
25C
max
min
2.03
2.10
85C
typ
max
min
2.03
2.10
typ
max
Unit
2.03
Condition
A
225
150
225
150
225
150
mA
125
125
150
150
125
125
150
150
125
144
150
173
th
tPW
tr
tf
Characteristic
Propagation Delay to Output
Clk to Q
Clk to BUS
Setup Time
BUS, RXEN
BUSEN
A, B Data
TEN
Hold Time
BUS, RXEN
BUSEN
A, B Data
TEN
Minimum Pulse Width
Clk
Rise/Fall Times
20 - 80% (Qn)
20 - 80% (BUSn Rise)
20 - 80% (BUSn Fall)
min
typ
25C
max
min
typ
85C
max
min
typ
max
Unit
Condition
ps
500
825
700
1250
150
100
300
450
450
500
350
200
100
1800
500
825
700
1250
150
200
50
150
150
100
300
450
150
200
50
150
450
500
350
200
1000
1800
500
825
700
1250
150
200
50
150
150
100
300
450
150
200
50
150
150
200
50
150
450
500
350
200
150
200
50
150
1000
1800
ps
ps
ps
400
400
400
ps
300
500
300
450
800
500
700
1000
800
2109
300
500
300
450
800
500
700
1000
800
300
500
300
450
800
500
700
1000
800
MOTOROLA
MOTOROLA
MC10E337
MC100E337
3-BIT SCANNABLE
REGISTERED
BUS TRANSCEIVER
Both drive and receive sides feature the same logic, including a loopback path to hold data. The HOLD/LOAD function is
controlled by Transmit Enable (TEN) and Receive Enable (REN) on the transmit and receive sides respectively, with a HIGH
selecting LOAD. Note that the implementation of the E337 Receive Enable differs from that of the E336.
A synchronous bus enable (SBUSEN) is provided for normal, non-scan operation. The asynchronous bus disable (ABUSDIS)
disables the bus immediately for scan mode.
The SYNCEN input is provided for flexibility when re-enabling the bus after disabling with ABUSDIS, allowing either
synchronous or asynchronous re-enabling. An alternative use is asynchronous-only operation with ABUSDIS, in which case
SYNCEN is tied LOW, or left open. SYNCEN is implemented as an overriding SET control (active-LOW) to the enable flip-flop.
Scan mode is selected by a HIGH at the SCAN input. Scan input data is shifted in through S_IN and output data appears at the
Q2 output.
All registers are clocked on the positive transition of CLK. Additional lead-frame grounding is provided through the Ground pins
(GND) which should be connected to 0V. The GND pins are not electrically connected to the chip.
PIN NAMES
Pin
A0 A2
B0 B2
S-IN
TEN, REN
SCAN
ABUSDIS
SBUSEN
SYNCEN
CLK
BUS0 BUS2
Q0 Q2
Function
Data Inputs A
Data Inputs B
Serial (Scan) Data Input
HOLD/LOAD Controls
Scan Control
Asynchronous Bus Disable
Synchronous Bus Enable
Synchronous Enable Control
Clock
25 Cutoff Bus Outputs
Receive Data Outputs (Q2 serves as SCAN_OUT in scan mode)
12/93
2110
REV 2
MC10E337 MC100E337
24
23
A0 ABUSDIS VCCO Q0
22
21
20
19
SCAN
26
18
GND
S-IN
27
17
BUS0
TEN
28
16
VCC
VEE
15
Q1
REN
14
VCCO
CLK
13
BUS1
A1
12
GND
B1
A2
B2
10
11
Q2
* All VCC and VCCO pins are tied together on the die.
LOGIC DIAGRAM
BUS2
A2
B2
D Q
D Q
Q2/
SCAN_OUT
BUS1
A1
B1
D Q
D Q
Q1
BUS0
A0
B0
S_IN
TEN
REN
SCAN
ABUSDIS
SBUSEN
SYNCEN
CLK
D Q
D Q
Q0
D Q
SET
2111
MOTOROLA
MC10E337 MC100E337
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
Characteristic
VCUT
IIH
IEE
min
typ
2.10
25C
max
min
2.03
2.10
typ
85C
max
min
2.03
2.10
typ
max
Unit
2.03
Condition
A
150
150
150
mA
145
145
174
174
145
145
174
174
145
167
174
200
min
tPLH
tPHL
450
800
500
800
ts
Setup Time
BUS
SBUSEN
Data, S-IN
TEN, REN, SCAN
350
100
400
550
350
100
400
550
350
100
400
550
Hold TIme
BUS
SBUSEN
Data, S-IN
TEN, REN, SCAN
350
500
350
200
350
500
350
200
350
500
350
200
400
400
400
Rise/Fall Times
20 - 80% (Qn)
20 - 80% (BUSn Rise)
20 - 80% (BUSn Fall)
300
500
300
tPW
tr
tf
MOTOROLA
max
min
1000
1800
1500
1800
450
800
500
800
typ
85C
Characteristic
th
typ
25C
max
min
1000
1800
1500
1800
450
800
500
800
typ
max
Unit
Condition
ps
1000
1800
1500
1800
ps
ps
ps
ps
800
1000
800
300
500
300
2112
800
1000
800
300
500
300
800
1000
800
MOTOROLA
MC10E404
MC100E404
QUAD DIFFERENTIAL
AND/NAND
Differential D and Q
700ps Max. Propagation Delay
High Frequency Outputs
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
D2b
26
D2b
27
D2a
28
D3a
D3a
D3b
25
24
23
D3b VCCO Q3
22
21
20
Q3
19
18
Q2
17
Q2
16
VCC
15
Q1
VEE
D2a
14
Q1
D1b
13
Q0
D1b
12
Q0
10
D1a
D1a
D0b
D0b
D0a
LOGIC DIAGRAM
D0a
D0a
D0b
D0b
D1a
D1a
D1b
D1b
11
D2a
D2a
D2b
D2b
D0a VCCO
* All VCC and VCCO pins are tied together on the die.
Q0
Q0
Q1
Q1
Q2
Q2
PIN NAMES
Pin
D3a
D3a
D3b
D3b
Function
D[0:4], D[0:4]
Q[0:4], Q[0:4]
FUNCTION TABLE
Da
Db
Da
Db
L
L
H
H
L
H
L
H
L
L
L
H
L
L
H
H
L
H
L
H
L
H
H
H
12/93
2113
REV 2
Q3
Q3
MC10E404 MC100E404
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
Characteristic
IIH
IEE
VPP(DC)
Input Sensitivity
min
typ
25C
max
min
typ
150
85C
max
min
typ
150
max
Unit
150
Condition
mA
106
106
127
127
50
106
106
127
127
50
106
122
127
146
50
mV
VCMR
Common Mode Range
1.5
0
1.5
0
1.5
0
V
2
1. Differential input voltage required to obtain a full ECL swing on the outputs.
2. VCMR is referenced to the most positive side of the differential input signal. Normal operation is obtained when the input signals are within the
VCMR range and the input swing is greater than VPP MIN and < 1.0V.
Characteristic
25C
85C
min
typ
max
min
typ
max
min
typ
max
350
300
375
325
475
475
500
500
650
700
675
725
350
300
375
325
475
475
500
500
650
700
675
725
350
300
375
325
475
475
500
500
650
700
675
725
tPLH
tPHL
tSKEW
Within-Device Skew
VPP(AC)
150
tr
tf
Rise/Fall Time
20 - 80%
150
Unit
Condition
ps
50
50
50
150
400
150
150
400
150
400
ps
mV
ps
MOTOROLA
2114
MOTOROLA
1:9 DIFFERENTIAL
ECL/PECL RAMBUS
CLOCK BUFFER
The output voltage swing of the E411 is larger than a standard ECL
swing. The 1.2V output swings provide a signal which can be AC coupled
into RAMBus compatible input loads. The larger output swings are
produced by lowering the VOL of the device. With the exception of the
lower VOL, the E411 is identical to the MC10E111. Note that the larger
output swings eliminate the possibility of temperature compensated
outputs, thus the E411 is only available in the 10E style of ECL. In
FN SUFFIX
PLASTIC PACKAGE
addition, because the VOL is lower than standard ECL, the outputs cannot
CASE 776-02
be terminated to 2.0V. This datasheet provides a few termination
alternatives.
The E411 is specifically designed, modeled and produced with low
skew as the key goal. Optimal design and layout serve to minimize gate to
gate skew within a device, and empirical modeling is used to determine
process control limits that ensure consistent tpd distributions from lot to
lot. The net result is a dependable, guaranteed low skew device.
To ensure that the tight skew specification is met it is necessary that both sides of the differential output are terminated, even if
only one side is being used. In most applications, all nine differential pairs will be used and therefore terminated. In the case
where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on the same package side as the
pair(s) being used on that side, in order to maintain minimum skew. Failure to do this will result in small degradations of
propagation delay (on the order of 1020ps) of the output(s) being used which, while not being catastrophic to most designs, will
mean a loss of skew margin.
The MC10E411, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the
E411 to be used for high performance clock distribution in +5.0V systems. Designers can take advantage of the E411s
performance to distribute low skew clocks across the backplane or the board. In a PECL environment, series or Thevenin line
terminations are typically used as they require no additional power supplies. For more information on using PECL, designers
should refer to Motorola Application Note AN1406/D.
11/95
2115
REV 1
MC10E411
Q0
Q0
Q1 VCCO Q1
Q2
Q2
25
24
23
20
19
22
21
VEE
26
18
Q3
NC
27
17
Q3
IN
28
16
Q4
15
VCCO
PIN NAMES
Pins
Function
IN, IN
Q0, Q0Q8, Q8
VBB
VCC
IN
14
Q4
VBB
13
Q5
NC
12
Q5
LOGIC SYMBOL
Q8
Q8
Q7
VCCO Q7
10
11
Q6
Q6
TERMINATION ALTERNATIVES
Q0
Q0
VCC
Q1
Q1
Q2
Q2
RS = ZO
RAMBus Load
Q3
Q3
IN
Q4
Q4
EN
Q5
Q5
IN
300
VEE
Q6
Q6
VCC
Q7
Q7
VBB
MOTOROLA
ZO
ZO
Q8
Q8
2116
RL = ZO
VCC 2.4V
MC10E411
ECL DC CHARACTERISTICS
0C
Symbol
Characteristic
Min
Typ
25C
85C
Max
Min
Typ
Max
Min
Max
Unit
VOH
1.020
0.840
0.980
0.890
0.810
0.910
0.720
VOL
2.420
2.140
2.380
2.250
2.110
2.310
2.020
VIH
1.170
0.840
1.130
0.810
1.060
0.720
VIL
1.950
1.480
1.950
1.480
1.950
1.445
VBB
1.38
1.27
1.35
1.25
1.31
1.19
VEE
4.5
5.5
4.5
5.5
4.5
5.5
IIH
150
IEE
65
mA
Max
Unit
150
55
Typ
150
65
55
65
55
PECL DC CHARACTERISTICS
0C
Symbol
Characteristic
VOH
VOL
VIH
VIL
VBB
VCC
IIH
IEE
Min
Typ
25C
85C
Max
Min
Typ
Max
Min
3.98
4.16
4.02
4.11
4.19
4.09
4.28
2.58
2.86
2.62
2.75
2.89
2.69
2.98
3.83
4.16
3.87
4.19
3.94
4.28
3.05
3.52
3.05
3.52
3.05
3.56
3.62
3.73
3.65
3.75
3.69
3.81
4.5
5.5
4.5
5.5
4.5
5.5
150
65
mA
150
55
65
Typ
150
55
65
55
1. These values are for VCC = 5.0V. Level Specifications will vary 1:1 with VCC.
2. Measured with 300 to VEE output pulldown.
2117
MOTOROLA
MC10E411
AC CHARACTERISTICS (VEE = VEE (min) to VEE (max); VCC = VCCO = GND)
0C
Symbol
tPLH
tPHL
Characteristic
Min
400
350
450
Typ
25C
Max
Min
600
650
850
430
380
450
Typ
85C
Max
Min
630
680
850
500
450
450
Typ
Max
Unit
Condition
ps
700
750
850
Note 1.
Note 2.
ts
Setup Time
EN to IN
200
200
200
ps
Note 3.
tH
Hold Time
IN to EN
200
200
200
ps
Note 4.
tR
Release Time
EN to IN
300
100
300
100
300
100
ps
Note 5.
ps
Note 6.
mV
Note 7.
tskew
Within-Device Skew
Part-to-Part Skew (Diff)
50
200
50
200
VPP
250
VCMR
1.6
0.4
1.6
0.4
1.6
0.4
Note 8.
tr/tf
275
600
275
600
275
600
ps
20%80%
250
50
200
250
1. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals.
2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal.
3. The setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than
75 mV to that IN/IN transition (see Figure 1).
4. The hold time is the minimum time that EN must remain asserted after a negative going IN or a positive going IN to prevent an output response
greater than 75 mV to that IN/IN transition (see Figure 2).
5. The release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets
the specified IN to Q propagation delay and output transition times (see Figure 3).
6. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device.
7. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited
for the E411 as a differential input as low as 50 mV will still produce full ECL levels at the output.
8. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level
must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to VPP(min).
MOTOROLA
2118
MOTOROLA
MC10E416
MC100E416
QUINT DIFFERENTIAL
LINE RECEIVER
2 Stages of Gain
Extended 100E VEE Range of 4.2V to 5.46V
Internal 75k Input Pulldown Resistors
Pinout: 28-Lead PLCC (Top View)
D3
D4
D4
VCCO
Q4
Q4
VCCO
25
24
23
22
21
20
19
18
Q3
27
17
Q3
D2
28
16
VCC
D0
Q0
VEE
15
Q2
D0
Q0
VBB
14
Q2
D1
Q1
D0
13
VCCO
D1
Q1
D0
D2
Q2
D2
Q2
D3
Q3
D3
Q3
D4
Q4
D4
Q4
D3
26
D2
12
5
10
11
D1
D1
VCCO
Q0
Q0
VCCO
Q1
* All VCC and VCCO pins are tied together on the die.
PIN NAMES
Pin
Function
D[0:4], D[0:4]
Q[0:4], Q[0:4]
Q1
LOGIC DIAGRAM
VBB
12/93
2119
REV 2
MC10E416 MC100E416
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
VBB
Characteristic
Output Reference Voltage
10E
100E
IIH
IEE
VPP(DC)
Input Sensitivity
min
typ
25C
max
min
1.27
1.26
1.35
1.38
typ
85C
max
min
1.25
1.26
1.31
1.38
typ
max
Unit
Condition
V
1.38
1.38
150
1.19
1.26
150
150
A
mA
135
135
162
162
50
135
135
162
162
50
135
155
162
186
50
mV
VCMR
Common Mode Range
1.5
0
1.5
0
1.5
0
V
2
1. Differential input voltage required to obtain a full ECL swing on the outputs.
2. VCMR is referenced to the most positive side of the differential input signal. Normal operation is obtained when the input signal are within the
VCMR range and the input swing is greater than VPP MIN and < 1.0V
Characteristic
25C
85C
min
typ
max
min
typ
max
min
typ
max
250
200
350
350
500
550
250
200
350
350
500
550
250
200
350
350
500
550
Unit
Condition
tPLH
tPHL
ps
tSKEW
Within-Device Skew
50
50
50
ps
tSKEW
10
10
10
ps
mV
VPP(AC)
150
tr
tf
Rise/Fall Time
20 - 80%
100
150
200
350
100
150
200
350
100
200
350
ps
MOTOROLA
2120
MOTOROLA
MC10E431
MC100E431
3-BIT DIFFERENTIAL
FLIP-FLOP
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
24
23
D2
D2
R2
S2
22
21
20
19
LOGIC DIAGRAM
CLK1
26
18
Q2
S0
CLK1
27
17
Q2
D0
D0
R1
28
16
VCC
VEE
15
Q1
S1
14
Q1
D1
13
Q0
D1
12
4
5
10
CLK0
CLK0
D0
D0
R0
S0
Pin
D[0:2], D[0:2]
CLK[0:2], CLK[0:2]
S[0:2]
R[0:2]
VBB
Q[0:2], Q[0:2]
Function
Differential Data Inputs
Differential Clock
Edge Triggered Set Inputs
Edge Triggered Reset Input
VBB Reference Output
Differential Data Outputs
2121
Q0
Q1
Q0
11
Q1
Q2
Q2
S1
D1
D1
VCCO
CLK1
R
R1
S2
D2
D2
CLK2
CLK2
R2
VBB
5/95
Q0
R0
* All VCC and VCCO pins are tied together on the die.
PIN NAMES
CLK1
CLK0 CLK0
REV 3
MC10E431 MC100E431
FUNCTION TABLE
Dn
CLKn
Rn
Sn
Qn
L
H
X
X
Z
Z
X
X
L
L
Z
L
L
L
L
Z
L
H
L
H
Characteristic
Output Reference
Voltage
10E
100E
IIH
Input HIGH
Current
IEE
Power Supply
Current
10E
100E
VCMR
Min
Typ
0C
Max
Min
Typ
25C
Max
Min
85C
Typ
Max
Min
Typ
Max
Unit
Cond
V
1.43
1.38
1.30
1.26
1.38
1.38
1.27
1.26
150
Common Mode
Range
1.35
1.38
1.25
1.26
1.31
1.38
150
150
150
1.19
1.26
A
mA
110
110
1.5
132
132
110
110
1.5
132
132
110
110
0
132
132
1.5
110
127
0
132
152
1.5
1. VCMR is referenced to the most positive side of the differential input signal. Normal specified operation is obtained when the input signals are
within the VCMR range and the input swing is greater than VPP.
Characteristic
Min
Typ
fMAX
tPLH
tPHL
1000
1400
CLK (Diff)
CLK (SE)
R
S
410
460
500
500
600
600
725
725
tS
Setup Time
D
R
S
250
1100
1100
250
CLK
400
tH
tPW
Hold Time
tskew
VPP
Within-Device Skew
0C to 85C
Max
Min
Typ
1100
1400
450
400
550
550
600
600
725
725
0
700
700
200
1000
1000
0
700
700
ps
200
ps
790
840
975
975
400
50
150
Unit
Condition
MHz
750
800
925
925
ps
1
1
ps
50
150
Max
ps
mV
tr/tf
Rise/Fall Times
250
450
700
275
450
650
ps
2080%
1. These setup times define the minimum time the CLK or SET/RESET input must wait after the assertion of the RESET/SET input to assure the
proper operation of the flip-flop.
2. Within-device skew is defined as identical transitions on similar paths through a device.
3. Minimum input swing for which AC parameters are guaranteed.
MOTOROLA
2122
MOTOROLA
MC10E445
MC100E445
4-BIT SERIAL/
PARALLEL CONVERTER
SINA SINA
Pin
SINA, SINA
SINB, SINB
SEL
Q0Q3
CLK, CLK
CL/4, CL/4
CL/8, CL/8
MODE
SYNCH
Function
Differential Serial Data Input A
Differential Serial Data Input B
Serial Input Selector Pin
Parallel Data Outputs
Differential Clock Inputs
Differential 4 Clock Output
Differential 8 Clock Output
Conversion Mode 4-Bit/8-Bit
Conversion Synchronizing Input
FUNCTION TABLES
Mode
Conversion
SEL
Serial Input
L
H
4-Bit
8-Bit
H
L
A
B
2123
22
17
SOUT
28
16
VCC
VEE
Q0
CLK
14
Q1
CLK
13
VCCO
VBB
12
Q2
SINB
27
SEL
21
20
10
11
7/96
23
SOUT
26
24
MODE NC VCCO
19
18
SINB
25
RESET
PIN NAMES
SYNC
REV 2
MC10E445 MC100E445
LOGIC DIAGRAM
SINB
SINB
SINA
Q3
Q2
Q1
Q0
SINA
SEL
SOUT
SOUT
4
CL/4
CLK
CL/4
CLK
R
0
1
CL/8
CL/8
R
MODE
RESET
SYNC
MOTOROLA
2124
MC10E445 MC100E445
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
Characteristic
Min
Typ
25C
Max
Min
Typ
150
85C
Max
Min
Typ
150
Max
Unit
150
IIH
VOH
1020
1025
790
830
980
1025
760
830
910
1025
670
830
VBB
1.38
1.38
1.27
1.26
1.35
1.38
1.25
1.26
1.31
1.38
1.19
1.26
IEE
Condition
V
1
1
V
mA
154
154
185
185
154
154
185
185
154
177
185
212
1. The maximum VOH limit was relaxed from standard ECL due to the high frequency output design. All other outputs are specified with the standard
10E and 100E VOH levels.
Min
fMAX
Symbol
2.0
Typ
tPLH
tPHL
1500
800
1100
1100
1800
975
1325
1325
ts
Setup Time
SINA, SINB
SEL
100
0
th
Hold Time
SINA, SINB, SEL
tRR
25C
Max
Min
Typ
Max
2.0
Min
Typ
Max
2.0
Unit
Condition
Gb/s
NRZ
ps
1500
800
1100
1100
1800
975
1325
1325
250
200
100
0
450
300
500
300
tPW
400
tr
tf
Rise/Fall Times
SOUT
Other
100
200
85C
2100
1150
1550
1550
2100
1150
1550
1550
1500
800
1100
1100
1800
975
1325
1325
250
200
100
0
250
200
450
300
450
300
500
300
500
300
2100
1150
1550
1550
ps
ps
ps
ps
400
400
ps
225
425
350
650
100
200
2125
225
425
350
650
100
200
225
425
20%80%
350
650
MOTOROLA
MC10E445 MC100E445
TIMING DIAGRAMS
CLK
SIN
Dn-4
Dn-3
Dn-2
Dn-1
Dn
Dn+1
Dn+2
Dn+3
RESET
Q0
Dn-4
Dn
Q1
Dn-3
Dn+1
Q2
Dn-2
Dn+2
Q3
Dn-1
Dn+3
SOUT
Dn-4
Dn-3
Dn-2
Dn-1
Dn
Dn+1
Dn+2
Dn+3
CL/4
CL/8
CLK
SIN
Dn-4
Dn-3
Dn-2
Dn-1
Dn
Dn+1
Dn+2
Dn+3
Dn+4
RESET
SYNC
Q0
Dn-4
Dn+1
Q1
Dn-3
Dn+2
Q2
Dn-2
Dn+3
Q3
Dn-1
Dn+4
SOUT
Dn-4
Dn-3
Dn-2
Dn-1
Dn
Dn+1
Dn+2
Dn+3
Dn+4
CL/4
CL/8
MOTOROLA
2126
MC10E445 MC100E445
APPLICATIONS INFORMATION
CLOCK
CLOCK
E445a
SERIAL
INPUT
DATA
SIN
SIN
SOUT
SOUT
E445b
SIN
SIN
Q3 Q2 Q1 Q0
Q3 Q2 Q1 Q0
Q7 Q6 Q5 Q4
Q3 Q2 Q1 Q0
SOUT
SOUT
TO SERIAL
MEDIUM
100ps
CLOCK
PARALLEL
DATA
Tpd CLK
to SOUT
SINA
SINA
SINB
SINB
800ps
FROM
SERIAL
MEDIUM
1150ps
CLOCK A
CLOCK B
Tpd CLK
to SOUT
800ps
1150ps
2127
MOTOROLA
MC10E445 MC100E445
frequency up to 1.4GHz. The divide by eight clock of the
second E445 should be used to synchronize the parallel data
to the rest of the system as the parallel data of the two E445s
will no longer be synchronized. This skew problem between
the outputs can be worked around as the parallel information
will be static for eight more clock pulses.
CLOCK
CLOCK
E445a
SERIAL
INPUT
DATA
SIN
SIN
700ps
(1.4GHz)
E445b
SOUT
SOUT
CLOCK A
SIN
SIN
Q3 Q2 Q1 Q0
100ps
CLOCK B
Tpd CLK
to SOUT
Q3 Q2 Q1 Q0
800ps
Q7 Q6 Q5 Q4
1150ps
Q3 Q2 Q1 Q0
CLK
SINa
Dn-4
Dn-3
Dn-2
Dn-1
Dn
Dn+1
Dn+2
Dn+3
Q0
Dn-4
Q1
Dn-3
Q2
Dn-2
Q3
Dn-1
Q4 (Q0 a)
Dn
Q5 (Q1 a)
Dn+1
Q6 (Q2 a)
Dn+2
Q7 (Q3 a)
Dn+3
SOUTa
Dn-4
Dn-3
SOUTb
Dn-2
Dn-1
Dn
Dn+1
Dn+2
Dn+3
Dn-4
Dn-3
Dn-2
Dn-1
Dn
Dn+1
CL/4a
CL/4b
CL/8a
CL/8b
MOTOROLA
2128
MOTOROLA
MC10E446
MC100E446
4-BIT PARALLEL/
SERIAL CONVERTER
The SYNC input will asynchronously reset the internal clock circuitry.
FN SUFFIX
This pin allows the user to reset the internal clock conversion unit and
PLASTIC PACKAGE
thus select the start of the conversion process.
CASE 776-02
The MODE input is used to select the conversion mode of the device.
With the MODE input LOW, or open, the device will function as a 4-bit
converter. When the mode input is driven HIGH the internal load clock will
change on every eighth clock cycle thus allowing for an 8-bit conversion scheme using two E446s. When cascaded in an 8-bit
conversion scheme the devices will not operate at the 1.3Gb/s data rate of a single device. Refer to the applications section of
this data sheet for more information on cascading the E446.
For lower data rate applications a VBB reference voltage is supplied for single-ended inputs. When operating at clock rates
above 500MHz differential input signals are recommended. For single-ended inputs the VBB pin is tied to the inverting differential
input and bypassed via a 0.01F capacitor. The VBB provides the switching reference for the input differential amplifier. The VBB
can also be used to AC couple an input signal, for more information on AC coupling refer to the interfacing section of the design
guide in the ECLinPS data book.
Pinout: 28-Lead PLCC (Top View)
PIN NAMES
Pin
Function
SIN
D0 D3
SOUT, SOUT
CLK, CLK
CL/4, CL/4
CL/8, CL/8
MODE
SYNC
FUNCTION TABLES
Mode
Conversion
L
H
4-Bit
8-Bit
D0
D1
D2
D3 MODE NC
NC
25
24
23
22
CLK
26
19
18
NC
CLK
27
17
NC
VBB
28
16
VCC
VEE
15
SOUT
SIN
14
SOUT
SIN
13
VCCO
SYNC
12
NC
21
20
10
11
7/96
2129
REV 2
MC10E446 MC100E446
LOGIC DIAGRAM
SIN
0
SIN
D3
CLK
0
D
D2
CLK
0
D
D1
CLK
SOUT
D
Q
SOUT
D0
CLK
LOAD PULSE
GENERATOR
CL/8
Mode
1
CL/8
CLK
CLK
Delay
R
CL/4
CL/4
SYNC
MOTOROLA
2130
MC10E446 MC100E446
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
Characteristic
Min
Typ
25C
Max
Min
Typ
150
85C
Max
Min
Typ
150
Max
Unit
150
IIH
VOH
1020
1025
790
830
980
1025
760
830
910
1025
670
830
VBB
1.38
1.38
1.27
1.26
1.35
1.38
1.25
1.26
1.31
1.38
1.19
1.26
IEE
151
174
mA
Condition
10E
100E
126
126
151
151
126
126
151
151
126
145
1
1
1. The maximum VOH limit was relaxed from standard ECL due to the high frequency output design. All other outputs are specified with the standard
10E and 100E VOH levels.
Characteristic
Min
Typ
1.3
1.6
25C
Max
Min
Typ
1.3
1.6
1020
650
800
650
1200
850
1050
850
85C
Max
Min
Typ
1.3
1.6
1020
650
800
650
1200
850
1050
850
Max
Unit
FMAX
tPLH
tPHL
1020
650
800
650
1200
850
1050
850
ts
Setup Time2
SIN, Dn
-200
-450
-200
450
200
450
ps
th
Hold Time2
SIN, Dn
900
650
900
650
900
650
ps
tRR
500
300
500
300
500
300
ps
tPW
CLK, MR
300
tr
tf
Rise/Fall Times
SOUT
Other
100
200
Condition
Gb/s
NRZ
ps
1480
1050
1300
1100
1480
1050
1300
1100
300
225
425
350
650
100
200
1480
1050
1300
1100
300
225
425
350
650
ps
100
200
225
425
D02
D12
350
650
ps
20% - 80%
Timing Diagrams
CLK
RESET
D0
D01
D02
D1
D11
D12
D2
D21
D22
D3
D31
D32
SOUT
D01
D11
D21
D31
D22
D32
CL/4
CL/8
2131
MOTOROLA
MC10E446 MC100E446
Applications Information
The MC10E/100E446 is an integrated 4:1 parallel to serial
converter. The chip is designed to work with the E445 device
to provide both transmission and receiving of a high speed
serial data path. The E446 can convert 4 bits of data into a
1.3Gb/s NRZ data stream. The device features a SYNC input
which allows the user to reset the internal clock circuitry and
restart the conversion sequence (see timing diagram A).
CLK
CLK
E446B
E446A
SOUT
SOUT
SIN
SIN
Serial
Data
SOUT
SOUT
Q3 Q2 Q1 Q0
Q3 Q2 Q1 Q0
Q7 Q6 Q5 Q4
Q3 Q2 Q1 Q0
Parallel Data
1000ps
600ps
CLOCK
Tpd CLK
to SOUT
1000ps
1600ps
CLK
RESET
D0
D01
D02
D1
D11
D12
D2
D21
D22
D3
D31
D32
D4 (D0B)
D41
D42
D5 (D1B)
D51
D52
D6 (D2B)
D61
D62
D7 (D3B)
D71
D72
SOUT
D01
D11
D21
D31
D41
D51
D61
D71
D02
CL/4
CL/8
MOTOROLA
2132
MOTOROLA
MC10E451
MC100E451
6-BIT D REGISTER
DIFFERENTIAL
DATA AND CLOCK
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
D5
D4
D4
D3
D3
VCCO
25
24
23
22
21
20
19
LOGIC DIAGRAM
26
18
VBB
27
17
Q4
CLK
28
16
VCC
VEE
15
Q3
MR
14
VCCO
NC
13
Q2
D0
12
Q1
CLK
10
Q5
D0
D0
R
D1
D1
D2
D2
D0 D5
D0 D5
CLK
CLK
MR
VBB
Q0 Q5
Function
+Data Input
Data Input
+Clock Input
Clock Input
Master Reset Input
VBB Output
Data Outputs
R
D3
D3
Q3
D
R
D4
D4
Q4
D
R
D5
D5
Q5
D
R
CLK
CLK
MR
VBB
12/93
Q2
PIN NAMES
Pin
Q1
R
11
D0
D1
D1
D2
D2 VCCO Q0
* All VCC and VCCO pins are tied together on the die.
Q0
2133
REV 2
MC10E451 MC100E451
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0C
Symbol
VBB
Characteristic
Output Reference Voltage
10E
100E
IIH
IEE
min
typ
25C
max
min
1.2
7
1.2
6
1.3
5
1.3
8
85C
typ
max
min
typ
1.2
5
1.2
6
1.3
1
1.3
8
max
Unit
Condition
V
1.3
8
1.3
8
150
1.1
9
1.2
6
150
150
mA
84
84
101
101
84
84
101
101
84
97
101
116
VCMR
Common Mode Range
2.0
0.4 2.0
0.4 2.0
0.4
V
2
1. VCMR is referenced to the most positive side of the differential input signal. Normal operation is obtained when the HIGH input is within the
VCMR range and the input swing is greater than VPP MIN and < 1.0V.
Characteristic
min
typ
25C
max
min
typ
1100
1400
475
425
425
650
650
600
85C
max
min
typ
1100
1400
475
425
425
650
650
600
fMAX
1100
1400
tPLH
tPHL
475
425
425
650
650
600
ts
Setup Time
D
150
100
150
100
150
100
Hold Time
D
250
100
250
100
250
100
VPP(AC)
150
tRR
750
tPW
400
th
tSKEW
Within-Device Skew
tr
tf
Rise/Fall Times
20 - 80%
max
Unit
Condition
MHz
ps
800
850
850
800
850
850
800
850
850
ps
ps
150
600
750
159
600
750
mV
600
ps
ps
400
100
400
100
100
ps
ps
275
450
800
275
450
800
275
450
800
MOTOROLA
2134
MOTOROLA
MC10E452
MC100E452
5-BIT DIFFERENTIAL
REGISTER
D3
D4
D4 VCCO Q4
Q4
25
24
23
22
19
21
20
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
MR
26
18
Q3
CLK
27
17
Q3
CLK
28
16
VCC
VEE
15
Q2
VBB
14
Q2
D2
13
Q1
12
Q1
D2
4
5
D1
D1
D0
10
11
D0 VCCO Q0
Q0
* All VCC and VCCO pins are tied together on the die.
LOGIC DIAGRAM
D0
D0
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
R
D1
D1
R
D2
D2
R
D3
D3
PIN NAMES
Pin
D[0:4], D[0:4]
MR
CLK, CLK
VBB
Q[0:4], Q[0:4]
Function
Differential Data Inputs
Master Reset Input
Differential Clock Input
VBB Reference Output
Differential Data Outputs
D4
D4
CLK
CLK
MR
VBB
12/93
2135
REV 2
MC10E452 MC100E452
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
40C
Symbol
VBB
Characteristic
Output Reference
Voltage
10E
100E
IIH
Input HIGH
Current
IEE
Power Supply
Current
10E
100E
VCMR
Min
Typ
0C
Max
Min
Typ
25C
Max
Min
85C
Typ
Max
Min
Typ
Max
Unit
Cond
V
1.43
1.38
1.30
1.26
1.38
1.38
1.27
1.26
150
Common Mode
Range
1.35
1.38
1.25
1.26
150
1.31
1.38
1.19
1.26
150
150
A
mA
74
74
2.0
89
89
74
74
0.4
2.0
89
89
0.4
74
74
2.0
89
89
0.4
74
85
2.0
89
102
0.4
1. VCMR is referenced to the most positive side of the differential input signal. Normal specified operation is obtained when the input signals are
within the VCMR range and the input swing is greater than VPP.
Characteristic
fMAX
tPLH
tPHL
tS
tH
tRR
tPW
tskew
VPP
Within-Device Skew
Min
Typ
0C to 85C
Max
Min
Typ
1100
1400
475
425
425
600
600
625
50
ps
ps
1000
1400
CLK (Diff)
CLK (SE)
MR
425
375
375
600
600
625
Setup Time
175
50
150
Hold Time
225
50
200
50
750
450
700
450
CLK
MR
400
400
850
900
900
50
150
Condition
ps
ps
50
ps
150
2136
Unit
MHz
800
850
850
400
400
tr/tf
Rise/Fall Times
250
475
725
275
1. Within-device skew is defined as identical transitions on similar paths through a device.
2. Minimum input swing for which AC parameters are guaranteed.
MOTOROLA
Max
475
675
mV
ps
2080%
MOTOROLA
MC10E457
MC100E457
TRIPLE DIFFERENTIAL
2:1 MULTIPLEXER
PIN NAMES
Pin
Dn[0:2]; Dn[0:2]
SEL
COMSEL
VBB
Q[0:2], Q[0:2]
Function
Differential Data Inputs
Individual Select Input
Common Select Input
VBB Reference Output
Differential Data Outputs
FUNCTION TABLE
SEL
Data
H
L
a
b
SEL2
D2a
D2a
VBB
D2b
D2b COMSEL
25
24
23
22
21
20
19
SEL1
26
18
Q2
D1a
27
17
Q2
D1a
28
16
VCC
VEE
15
Q1
VBB
14
Q1
D1b
13
Q0
D1b
12
Q0
SEL0
D0a
D0a
VBB
D0b
10
11
D0b VCCO
* All VCC and VCCO pins are tied together on the die.
12/93
2137
REV 2
MC10E457 MC100E457
LOGIC DIAGRAM
D0a
D0a
D0b
D0b
Q0
2:1
MUX
Q0
SEL0
D1a
D1a
D1b
D1b
Q1
2:1
MUX
Q1
SEL1
D2a
D2a
Q2
2:1
MUX
D2b
D2b
Q2
SEL2
COMSEL
VBB
Characteristic
Min
Output Reference
Voltage
10E
100E
1.43
1.38
IIH
Input HIGH
Current
IEE
Power Supply
Current
10E
100E
VPP(DC)
VCMR
Typ
0C
Max
Min
1.30
1.26
1.38
1.38
Typ
25C
Max
Min
1.27
1.26
1.35
1.38
Typ
85C
Max
Min
1.25
1.26
1.31
1.38
Typ
Max
Unit
Cond
150
150
1.19
1.26
150
150
A
mA
92
92
Input Sensitivity
50
Commom Mode
Range
1.5
110
110
92
92
110
110
50
0
1.5
92
92
110
110
50
0
1.5
92
106
110
127
50
0
1.5
mV
1. Differential input voltage required to obtain a full ECL swing on the outputs.
2. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level
must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to VPP(min).
MOTOROLA
2138
MC10E457 MC100E457
AC CHARACTERISTICS (VEE = VEE (min) to VEE (max); VCC = VCCO = GND)
0C
Symbol
Characteristic
Min
tPLH
tPHL
tskew
tskew
Within-Device Skew
VPP(AC)
tr/tf
150
Rise/Fall Time
125
Typ
0C to 85C
Max
Min
Typ
Max
Unit
Condition
ps
325
275
300
325
tPLH tPHL
475
475
500
525
700
750
775
800
375
325
350
375
475
475
500
525
650
700
725
750
40
40
ps
10
10
ps
150
275
500
150
275
450
mV
ps
2080%
2139
MOTOROLA
MOTOROLA
MC10E1651
The latch enable (LENa and LENb) input pins operate from standard
ECL 10KH logic levels. When the latch enable is at a logic high level the
MC10E1651 acts as a comparator, hence Q will be at a logic high level if
V1 > V2 (V1 is more positive than V2). Q is the complement of Q. When
the latch enable input goes to a low logic level, the outputs are latched in
their present state providing the latch enable setup and hold time
constraints are met.
L SUFFIX
CERAMIC PACKAGE
CASE 620-10
LOGIC DIAGRAM
V1a
FUNCTION TABLE
Qa
V2a
Qa
LENa
LEN
V1, V2
Function
H
H
L
V1 > V2
V1 < V2
X
H
L
Latched
V1b
Qb
V2b
LENb
Qb
VEE = 5.2 V
VCC = +5.0 V
12/93
2140
REV 1
MC10E1651
17
16
V1b
V2b
15
14
Qb
19
13
VCC
GND
20
12
NC
NC
11
NC
GND
10
VEE
Qa
VCC
Qa LENa NC
V2a
V1a
GND Qb
16
15
14
13
12
11
10
Qa LENa V2a
GND Qa
V1a VCC
NC
VEE
Characteristic
Min
Typ
Max
12.0
3.7
Unit
V
V
Characteristic
Min
Typ
25C
Max
Min
Max
Min
Max
Unit
VOH
1020
840
980
810
920
735
mV
VOL
1950
1630
1950
1630
1950
1600
mV
II
IIH
65
150
65
150
65
150
ICC
IEE
50
55
50
55
50
55
mA
VCMR
3.0
Hys
Hysteresis
Vskew
Hysteresis Skew
Cin
Input Capacitance
DIP
PLCC
2.0
3.0
Typ
85C
2.0
3.0
Typ
2.0
27
27
30
mV
1.0
1.0
mV
Condition
pF
3
2
3
2
3
2
1. Hysteresis skew (Vskew) is provided to indicate the offset of the hysteresis window. For example, at 25C the nominal hysteresis value is 27mV
and the Vskew value indicates that the hysteresis was skewed from the reference level by 1mV in the negative direction. Hence the hysteresis
window ranged from 14mV below the reference level to 13mV above the reference level. All hysteresis measurements were determined using
a reference voltage of 0mV.
2141
MOTOROLA
MC10E1651
AC CHARACTERISTICS (VEE = 5.2 V 5%; VCC = +5.0 V 5%)
0C
Symbol
Characteristic
25C
85C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
900
750
625
400
775
575
925
750
700
500
850
650
1050
850
tPLH
tPHL
600
400
750
575
ts
Setup Time
V
450
300
450
300
550
350
50
250
50
250
100
250
400
th
tpw
tskew
TDE
Delay Dispersion
(ECL Levels)
TDL
tr
tf
Condition
ps
ps
ps
ps
400
15
400
15
15
ps
ps
100
60
Delay Dispersion
(TTL Levels)
Rise/Fall Times
20-80%
Unit
3, 4
3, 5
ps
350
100
6, 7
5, 6
ps
225
325
475
225
325
475
250
375
500
1. The propagation delay is measured from the crosspoint of the input signal and the threshold value to the crosspoint of the Q and Q output signals.
For propagation delay measurements the threshold level (VTHR) is centered about an 850mV input logic swing with a slew rate of 0.75 V/NS.
There is an insignificant change in the propagation delay over the input common mode range.
2. tskew is the propagation delay skew between comparator A and comparator B for a particular part under identical input conditions.
3. Refer to figure 4 and note that the input is at 850mV ECL levels with the input threshold range between the 20% and 80% points. The delay
is measured from the crosspoint of the input signal and the threshold value to the crosspoint of the Q and Q output signals.
4. The slew rate is 0.25 V/NS for input rising edges.
5. The slew rate is 0.75 V/NS for input rising edges.
6. Refer to Figure 5 and note that the input is at 2.5 V TTL levels with the input threshold range between the 20% and 80% points. The delay is
measured from the crosspoint of the input signal and the threshold value to the crosspoint of the Q and Q output signals.
7. The slew rate is 0.3 V/NS for input rising edges.
APPLICATIONS INFORMATION
The timing diagram (Figure 3) is presented to illustrate the
MC10E1651s compare and latch features. When the signal
on the LEN pin is at a logic high level, the device is operating
in the compare mode, and the signal on the input arrives at
the output after a nominal propagation delay (tPHL, tPLH). The
input signal must be asserted for a time, ts, prior to the
negative going transition on LEN and held for a time, th, after
the LEN transition. After time th, the latch is operating in the
latch mode, thus transitions on the input do not appear at
the output. The device continues to operate in the latch
mode until the latch is asserted once again. Moreover, the
LEN pulse must meet the minimum pulse width (tpw)
requirement to effect the correct input-output relationship.
Note that the LEN waveform in Figure 3 shows the LEN
signal swinging around a reference labeled VBBINT; this
waveform emphasizes the requirement that LEN follow
typical ECL 10KH logic levels because VBBINT is the
MOTOROLA
2142
MC10E1651
VBBINT
LEN
tpw
ts
V
VIN
th
VOD
VTHR
tPLH(LEN)
tPHL
Q
DELAY DISPERSION
Under a constant set of input conditions comparators have
a specified nominal propagation delay. However, since
propagation delay is a function of input slew rate and input
voltage overdrive the delay dispersion parameters, TDE and
TDT, are provided to allow the user to adjust for these
variables (where TDE and TDT apply to inputs with standard
ECL and TTL levels, respectively).
Figure 4 and Figure 5 define a range of input conditions
which incorporate varying input slew rates and input voltage
overdrive. For input parameters that adhere to these
constraints the propagation delay can be described as:
TNOM TDE (or TDT)
0.9 V
1.07 V
2.5 V
2.0 V
INPUT
THRESHOLD
RANGE
SLEW RATE =
0.25 V/NS
INPUT
THRESHOLD
RANGE
1.58 V
1.75 V
SLEW RATE =
0.30 V/NS
SLEW RATE = 0.75 V/NS
0.5 V
0V
2143
MOTOROLA
MOTOROLA
MC10E1652
The latch enable (LENa and LENb) input pins operate from standard
ECL 10H logic levels. When the latch enable is at a logic high level the
MC10E1652 acts as a comparator, hence Q will be at a logic high level if
V1 > V2 (V1 is more positive than V2). Q is the complement of Q. When
the latch enable input goes to a low logic level, the outputs are latched in
their present state, providing the latch enable setup and hold time
constraints are met. The level of input hysteresis is controlled by applying
a bias voltage to the HYS pin.
FN SUFFIX
PLASTIC PACKAGE
CASE 775-02
L SUFFIX
CERAMIC PACKAGE
CASE 620-10
LOGIC DIAGRAM
FUNCTION TABLE
V1a
Qa
V2a
Qa
LENa
LEN
V1, V2
Function
H
H
L
V1 > V2
V1 < V2
X
H
L
Latched
HYS
V1b
Qb
V2b
LENb
Qb
VEE = 5.2 V
VCC = +5.0 V
12/93
2144
REV 1
MC10E1652
Pinout: 20-Lead PLCC (Top View)
Qb LENb NC
18
17
16
V1b
V2b
15
14
Qb
19
13
VCC
GND
20
12
HYS
NC
11
NC
GND
10
VEE
VCC
Qa
3
4
Qa LENa NC
V2a
V1a
GND Qb
16
15
14
13
12
11
10
GND Qa
Qa LENa V2a
V1a VCC
VEE
Characteristic
Min
Typ
Max
12.0
3.7
Unit
V
V
Characteristic
Min
Typ
25C
Max
Min
Max
Min
Max
Unit
VOH
1020
840
980
810
920
735
mV
VOL
1950
1630
1950
1630
1950
1600
mV
II
IIH
65
150
65
150
65
150
ICC
IEE
50
55
50
55
50
55
mA
VCMR
Hys
Hysteresis
Vskew
Hysteresis Skew
Cin
Input Capacitance
DIP
PLCC
2.0
3.0
Typ
85C
2.0
3.0
Typ
2.0
3.0
Condition
27
27
30
mV
1.0
1.0
mV
pF
3
2
3
2
3
2
1. The HYS pin programming characterization information is shown in Figure 2, The hysteresis values indicated in the data sheet are for the
condition in which the voltage on the HYS pin is set to VEE.
2. Hysteresis skew (Vskew) is provided to indicate the offset of the hysteresis window. For example, at 25C the nominal hysteresis value is 27
mV and the Vskew value indicates that the hysteresis was skewed from the reference level by 1 mV in the negative direction. Hence the
hysteresis window ranged from 14 mV below the reference level to 13 mV above the reference level. All hysteresis measurements were
determined using a reference voltage of 0 mV. The hysteresis skew values apply over the programming range shown in Figure 2.
2145
MOTOROLA
MC10E1652
40
1.0
HYSTERESIS, (mV)
0.8
HYSTERESIS
1.2
1.4
1.6
1.8
20 16 12 8
4 Vref
12
16
30
20
Characteristic
Min
Typ
600
400
750
575
ts
Setup Time
V
450
50
400
tpw
tskew
TDE
Delay Dispersion
(ECL Levels)
TDL
tr
tf
25C
Max
900
750
Min
Typ
625
400
775
575
300
450
0.1
0.2
0.3
0.4
0.5
250
50
85C
Max
925
750
Min
Typ
700
500
850
650
300
550
350
250
100
250
Max
Unit
Condition
ps
1050
850
ps
ps
ps
400
15
400
15
15
ps
ps
100
60
Delay Dispersion
(TTL Levels)
Rise/Fall Times
20-80%
0.0
tPLH
tPHL
th
0.1
0C
Symbol
T = 0C
AC CHARACTERISTICS
T=
85C
10
0
0.2
20
T=
25C
3, 4
3, 5
ps
350
100
6, 7
5, 6
ps
225
325
475
225
325
475
250
375
500
1. The propagation delay is measured from the crosspoint of the input signal and the threshold value to the crosspoint of the Q and Q output signals.
For propagation delay measurements the threshold level (VTHR) is centered about an 850 mV input logic swing with a slew rate of 0.75 V/NS.
There is an insignificant change in the propagation delay over the input common mode range.
2. tskew is the propagation delay skew between comparator A and comparator B for a particular part under identical input conditions.
3. Refer to Figure 4 and note that the input is at 850 mV ECL levels with the input threshold range between the 20% and 80% points. The delay
is measured from the crosspoint of the input signal and the threshold value to the crosspoint of the Q and Q output signals.
4. The slew rate is 0.25 V/NS for input rising edges.
5. The slew rate is 0.75 V/NS for input rising edges.
6. Refer to Figure 5 and note that the input is at 2.5 V TTL levels with the input threshold range between the 20% and 80% points. The delay is
measured from the crosspoint of the input signal and the threshold value to the crosspoint of the Q and Q output signals.
7. The slew rate is 0.3 V/NS for input rising edges.
APPLICATIONS INFORMATION
The timing diagram (Figure 3) is presented to illustrate the
MC10E1652s compare and latch features. When the signal
on the LEN pin is at a logic high level, the device is operating
in the compare mode, and the signal on the input arrives at
the output after a nominal propagation delay (tPHL, tPLH). The
input signal must be asserted for a time, ts, prior to the
MOTOROLA
negative going transition on LEN and held for a time, th, after
the LEN transition. After time th, the latch is operating in the
latch mode, thus transitions on the input do not appear at
the output. The device continues to operate in the latch
mode until the latch is asserted once again. Moreover, the
LEN pulse must meet the minimum pulse width (tpw)
2146
MC10E1652
requirement to effect the correct input-output relationship.
Note that the LEN waveform in Figure 3 shows the LEN
signal swinging around a reference labeled VBBINT; this
waveform emphasizes the requirement that LEN follow
typical ECL 10KH logic levels because VBBINT is the
internally generated reference level, hence is nominally at
the ECL VBB level.
Finally, VOD is the input voltage overdrive and represents
the voltage level beyond the threshold level (VTHR) to which
the input is driven. As an example, if the threshold level is set
on one of the comparator inputs as 80 mV and the input
VBBINT
LEN
tpw
ts
V
VIN
th
VOD
VTHR
tPLH(LEN)
tPHL
Q
DELAY DISPERSION
Under a constant set of input conditions comparators have
a specified nominal propagation delay. However, since
propagation delay is a function of input slew rate and input
voltage overdrive the delay dispersion parameters, TDE and
TDT, are provided to allow the user to adjust for these
variables (where TDE and TDT apply to inputs with standard
ECL and TTL levels, respectively).
Figure 4 and Figure 5 define a range of input conditions
which incorporate varying input slew rates and input voltage
overdrive. For input parameters that adhere to these
constraints the propagation delay can be described as:
TNOM TDE (or TDT)
0.9 V
1.07 V
INPUT
THRESHOLD
RANGE
2.5 V
2.0 V
SLEW RATE =
0.25 V/NS
INPUT
THRESHOLD
RANGE
1.58 V
1.75 V
0.5 V
0V
SLEW RATE =
0.30 V/NS
2147
MOTOROLA
MOTOROLA
2148
31
MOTOROLA
MOTOROLA
Features
275ps Package Gate Delays
2.0GHz+ FlipFlop Toggle Frequencies
Space Efficient SOIC Packages
Choice of ECL Compatibility: MECL 10H (10EL); or ECL
100K (100EL)
FlowThrough Pinouts
Specified Over Industrial Temperature Range: 40C to
+85C
Extended VEE Range for Both 10EL and 100EL Devices
MOTOROLA
32
Symbol
Rating
Unit
VEE
8.0 to 0
VDC
VI
0 to 6.0
VDC
Iout
50
100
mA
TA
40 to +85
VEE
5.7 to 4.2
Output Current
Continuous
Surge
4.20V to 5.50V
4.94V to 5.50V
Characteristic
0C
25C
85C
Min
Max
Min
Max
Min
Max
Min
Max
Unit
VOH
1080
890
1020
840
980
810
910
720
mV
VOL
1950
1650
1950
1630
1950
1630
1950
1595
mV
VIH
1230
890
1170
840
1130
810
1060
720
mV
VIL
1950
1500
1950
1480
1950
1480
1950
1445
mV
IIL
Input LOW Current
0.5
0.5
0.5
0.3
A
1. 10EL circuits are designed to meet the DC specifications shown in the table after thermal equilibrium has been established. The circuit is in
a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. Outputs are terminated through
a 50 resistor to 2.0V except where otherwise specified on the individual data sheets.
Characteristic
0C to 85C
Min
Typ
Max
Min
Typ
Max
Unit
Condition
VOH
1085
1005
880
1025
955
880
mV
VIN = VIH(max)
VOL
1830
1695
1555
1810
1705
1620
mV
or VIL(min)
VOHA
1095
1035
mV
VIN = VIH(max)
VOLA
1555
1610
mV
or VIL(min)
VIH
1165
880
1165
880
mV
VIL
1810
1475
1810
1475
mV
IIL
Input LOW Current
0.5
0.5
A
VIN = VIL(max)
1. This table replaces the three tables traditionally seen in ECL 100K data books. The same DC parameter values at VEE = 4.5V now apply across
the full VEE range of 4.2V to 5.5V. Outputs are terminated through a 50 resistor to 2.0V except where otherwise specified on the individual
data sheets.
33
MOTOROLA
Applications Information
Introduction
The ECLinPS Lite family of products is very similar in
design and performance as the multigate ECLinPS family.
As a result the design guide and application notes written in
support of the ECLinPS family are equally applicable to the
new ECLinPS Lite family. The reader is encouraged to read
through the ECLinPS data book to answer any general
questions they may have concerning the ECLinPS Lite
family. The following paragraphs will be used to describe
behavior that is unique to the ECLinPS Lite family or which
has not been thoroughly documented in the existing
literature.
1000
Maximum Frequency/Bandwidth
400
200
500
1000
1500
2000
2500
3000
3500
4000
FREQUENCY (MHz)
1000
FLIPFLOP
800
600
400
200
0
500
1000
1500
2000
2500
3000
3500
4000
FREQUENCY (MHz)
MOTOROLA
600
BUFFER
800
34
Package Information
0.001F
IN
OUT
50
EL16
OUT
0.01F
50
VBB
50
VTT
0.050 TYP
0.045 0.005
0.160 0.005
0.245 MIN
3
0.030 0.005
0.050 TYP
0.045 0.005
0.325 0.005
0.420 MIN
0.030 0.005
35
MOTOROLA
225
200
JA ( C/W)
175
8LEAD
150
125
16LEAD
100
75
20LEAD
50
0
100
200
300
400
500
600
700
800
MOTOROLA
36
MOTOROLA
4Input OR/NOR
MC10EL01
MC100EL01
8
1
D0 1
8 VCC
D1 2
7 Q
D2 3
6 Q
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
PIN DESCRIPTION
D3 4
5 VEE
PIN
FUNCTION
D0D3
Q
Data Inputs
Data Outputs
Characteristic
Min
IEE
VEE
IIH
4.75
4.20
0C
Typ
Max
14
14
17
17
5.2
4.5
5.5
5.5
Min
4.75
4.20
25C
Typ
Max
14
14
17
17
5.2
4.5
5.5
5.5
150
Min
4.75
4.20
85C
Typ
Max
14
14
17
17
5.2
4.5
5.5
5.5
150
Min
4.75
4.20
Typ
Max
Unit
14
16
17
20
mA
5.2
4.5
5.5
5.5
150
150
Characteristic
0C
25C
85C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
tPLH
tPHL
Propagation Delay to
Output
70
220
370
120
220
320
130
230
330
150
250
350
ps
tr
tf
100
225
350
100
225
350
100
225
350
100
225
350
ps
12/93
37
REV 2
MOTOROLA
2Input AND/NAND
MC10EL04
MC100EL04
8
1
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
NC 1
8 VCC
D0 2
7 Q
PIN DESCRIPTION
D1 3
6 Q
NC 4
5 VEE
PIN
FUNCTION
D0, D1
Q
Data Inputs
Data Outputs
Characteristic
Min
IEE
VEE
IIH
4.94
4.20
0C
Typ
Max
14
14
17
17
5.2
4.5
5.5
5.5
D0
D1
Min
4.94
4.20
25C
Typ
Max
14
14
17
17
5.2
4.5
5.5
5.5
250
150
Min
4.75
4.20
85C
Typ
Max
14
14
17
17
5.2
4.5
5.5
5.5
250
150
Min
4.75
4.20
Typ
Max
Unit
14
16
17
20
mA
5.2
4.5
5.5
5.5
250
150
250
150
Characteristic
0C
25C
85C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
tPLH
tPHL
Propagation Delay to
Output
70
235
410
120
235
360
130
240
370
155
265
395
ps
tr
tf
100
225
350
100
225
350
100
225
350
100
225
350
ps
12/93
38
REV 2
MOTOROLA
MC10EL05
MC100EL05
The MC10EL/100EL05 is a 2-input differential AND/NAND gate. The
device is functionally equivalent to the E404 device with higher
performance capabilities. With propagation delays and output transition
times significantly faster than the E404 the EL05 is ideally suited for those
applications which require the ultimate in AC performance.
Because a negative 2-input NAND is equivalent to a 2-input OR
function, the differential inputs and outputs of the device allows the EL05
to also be used as a 2-input differential OR/NOR gate.
The differential inputs employ clamp circuitry so that under open input
conditions (pulled down to VEE) the input to the AND gate will be HIGH. In
this way, if one set of inputs is open, the gate will remain active to the
other input.
8
1
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
D0 1
8 VCC
D0 2
7 Q
D1 3
6 Q
D1 4
PIN DESCRIPTION
PIN
FUNCTION
D0, D1
Q
Data Inputs
Data Outputs
5 VEE
12/93
39
REV 2
MC10EL05 MC100EL05
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND)
40C
Symbol
IEE
VEE
IIH
Characteristic
Min
4.75
4.20
0C
Typ
Max
18
18
22
22
5.2
4.5
5.5
5.5
Min
4.75
4.20
25C
Typ
Max
18
18
22
22
5.2
4.5
5.5
5.5
150
Min
4.75
4.20
85C
Typ
Max
18
18
22
22
5.2
4.5
5.5
5.5
150
Min
4.75
4.20
Typ
Max
Unit
18
21
22
25
mA
5.2
4.5
5.5
5.5
150
150
Characteristic
0C
25C
85C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
260
440
185
275
390
185
275
390
215
305
420
ps
tPLH
tPHL
Propagation Delay to
Output
135
VPP
150
VCMR
0.4
tr
tf
100
150
225
See2
0.4
350
100
150
225
See2
0.4
350
100
150
225
See2
0.4
350
100
mV
225
See2
350
ps
1. Minimum input swing for which AC parameters are guaranteed. The device has a DC gain of 40.
2. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between VPPmin and 1V. The lower end of the CMR range is dependent on VEE and is
equal to VEE + 3.0V.
MOTOROLA
310
MOTOROLA
2Input XOR/XNOR
MC10EL07
MC100EL07
8
1
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
NC 1
8 VCC
D0 2
7 Q
PIN DESCRIPTION
D1 3
6 Q
NC 4
5 VEE
PIN
FUNCTION
D0, D1
Q
Data Inputs
Data Outputs
Characteristic
Min
IEE
VEE
IIH
4.94
4.20
0C
Typ
Max
14
14
17
17
5.2
4.5
5.5
5.5
D0
D1
Min
4.94
4.20
25C
Typ
Max
14
14
17
17
5.2
4.5
5.5
5.5
250
150
Min
4.75
4.20
85C
Typ
Max
14
14
17
17
5.2
4.5
5.5
5.5
250
150
Min
4.75
4.20
Typ
Max
Unit
14
16
17
20
mA
5.2
4.5
5.5
5.5
250
150
250
150
Characteristic
0C
25C
85C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
tPLH
tPHL
Propagation Delay to
Output
90
250
435
140
250
385
150
260
395
170
280
415
ps
tr
tf
100
225
350
100
225
350
100
225
350
100
225
350
ps
12/93
311
REV 2
MOTOROLA
MC10EL11
MC100EL11
Q0
VCC
Q0
D
PIN DESCRIPTION
Q1
Q1
VEE
PIN
FUNCTION
D
Q0, Q1
Data Inputs
Data Outputs
12/93
312
REV 4
MC10EL11 MC100EL11
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND)
40C
Symbol
IEE
VEE
IIH
Characteristic
Min
0C
Typ
Max
26
26
31
31
5.2
4.5
5.5
5.5
Min
25C
Typ
Max
26
26
31
31
5.2
4.5
5.5
5.5
Min
85C
Typ
Max
26
26
31
31
5.2
4.5
5.5
5.5
Min
Typ
Max
26
30
31
36
5.2
4.5
5.5
5.5
Unit
mA
V
4.75
4.20
4.75
4.20
150
4.75
4.20
150
4.75
4.20
150
150
Characteristic
25C
85C
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
135
260
385
185
260
335
190
265
340
215
290
365
ps
5
5
20
20
5
5
20
20
5
5
20
20
ps
tPLH
tPHL
Propagation Delay to
Output
tSKEW
Within-Device Skew1
Duty Cycle Skew2
VPP
150
VCMR
0.4
tr
tf
100
1.
2.
3.
4.
0C
Min
5
5
150
225
See4
0.4
350
100
150
225
See4
0.4
350
100
150
225
See4
0.4
350
100
mV
225
See4
350
ps
313
MOTOROLA
MOTOROLA
MC10EL12
MC100EL12
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
Qa
VCC
Qb
D0
Qa
D1
Qb
PIN DESCRIPTION
VEE
PIN
FUNCTION
D0, D1
Qa, Qb
Data Inputs
Data Outputs
Characteristic
Min
IEE
VEE
IIH
4.94
4.20
0C
Typ
Max
14
14
17
17
5.2
4.5
5.5
5.5
Min
4.94
4.20
25C
Typ
Max
14
14
17
17
5.2
4.5
5.5
5.5
150
Min
4.94
4.20
85C
Typ
Max
14
14
17
17
5.2
4.5
5.5
5.5
150
Min
4.94
4.20
Typ
Max
Unit
14
16
17
20
mA
5.2
4.5
5.5
5.5
150
150
Characteristic
0C
25C
85C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
tPLH
tPHL
Propagation Delay to
Output
120
280
500
170
280
450
180
290
450
210
320
480
ps
tr
tf
150
350
550
150
350
550
150
350
550
150
350
550
ps
12/93
314
REV 2
MOTOROLA
MC100EL13
20
1
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D04
315
MOTOROLA
MOTOROLA
MC100EL14
20
1
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D-04
MOTOROLA
316
MOTOROLA
MC10EL15
MC100EL15
16
1
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B-05
The common enable (EN) is synchronous so that the outputs will only
be enabled/disabled when they are already in the LOW state. This avoids
any chance of generating a runt clock pulse when the device is
enabled/disabled as can happen with an asynchronous control. The
internal flip flop is clocked on the falling edge of the input clock, therefore
all associated specification limits are referenced to the negative edge of
the clock input.
PIN DESCRIPTION
VCC
EN
16
15
SCLK CLK
14
13
1
CLK
VBB
SEL
VEE
12
11
10
D
Q
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
PIN
FUNCTION
CLK
SCLK
EN
SEL
VBB
Q03
FUNCTION TABLE
CLK
SCLK
SEL
EN
L
H
X
X
X
X
X
L
H
X
L
L
H
H
X
L
L
L
L
H
L
H
L
H
L*
5/95
317
REV 2
MC10EL15 MC100EL15
ABSOLUTE MAXIMUM RATINGS1
Symbol
Characteristic
Rating
Unit
VEE
8.0 to 0
VDC
VI
0 to 6.0
VDC
Iout
Output Current
50
100
mA
TA
40 to +85
Continuous
Surge
VEE
Operating Range1,2
5.7 to 4.2
1. Absolute maximum rating, beyond which, device life may be impaired, unless otherwise specified on an individual data sheet.
2. Parametric values specified at: 100EL Series: 4.20V to 5.50V
10EL Series:
4.94V to 5.50V
10EL SERIES
DC CHARACTERISTICS (VEE = VEE(min) VEE(max); VCC = GND1)
40C
Symbol
Characteristic
Min
0C
Max
Min
25C
Max
Min
85C
Max
Min
Max
Unit
VOH
1080
890
1020
840
980
810
910
720
mV
VOL
1950
1650
1950
1630
1950
1630
1950
1595
mV
VIH
1230
890
1170
840
1130
810
1060
720
mV
VIL
1950
1500
1950
1480
1950
1480
1950
1445
mV
IIL
Input LOW Current
0.5
0.5
0.5
0.3
A
1. 10EL circuits are designed to meet the DC specifications shown in the table after thermal equilibrium has been established. The circuit is in
a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. Outputs are terminated through
a 50 resistor to 2.0V except where otherwise specified on the individual data sheets.
100EL SERIES
DC CHARACTERISTICS (VEE = VEE(min) VEE(max); VCC = GND1)
40C
Symbol
Characteristic
0C to 85C
Min
Typ
Max
Min
Typ
Max
Unit
Condition
VOH
1085
1005
880
1025
955
880
mV
VIN = VIH(max)
VOL
1830
1695
1555
1810
1705
1620
mV
or VIL(min)
VOHA
1095
1035
mV
VIN = VIH(max)
VOLA
1555
1610
mV
or VIL(min)
VIH
1165
880
1165
880
mV
VIL
1810
1475
1810
1475
mV
IIL
Input LOW Current
0.5
0.5
A
VIN = VIL(max)
1. This table replaces the three tables traditionally seen in ECL 100K data books. The same DC parameter values at VEE = 4.5V now apply across
the full VEE range of 4.2V to 5.5V. Outputs are terminated through a 50 resistor to 2.0V except where otherwise specified on the individual
data sheets.
MOTOROLA
318
MC10EL15 MC100EL15
AC/DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND)
40C
Symbol
IEE
Characteristic
Min
Typ
Max
25
25
35
35
1.30
1.26
Min
25C
Typ
Max
25
25
35
35
1.38
1.38
1.27
1.26
Min
Typ
Max
25
25
35
35
Min
Max
Unit
25
25
35
38
mA
IIH
tPLH
tPHL
Propagation Delay
CLK to Q (Diff)
CLK to Q (SE)
SCLK to Q
tSKEW
Part-to-Part Skew
Within-Device Skew1
tS
Setup Time EN
150
150
150
150
ps
tH
HoldTime EN
400
400
400
400
ps
VPP
250
VCMR
Common
CLK3
2.0
Range
150
1.25 1.31
1.26 1.38
Typ
150
1.35
1.38
85C
VBB
Mode
1.43
1.38
0C
150
1.19
1.26
150
ps
460
410
410
660
710
710
470
420
420
610
720
720
200
50
200
50
250
0.4
470
420
420
610
720
720
200
50
250
2.0
0.4
500
450
470
2.0
700
750
750
200
50
250
0.4
2.0
ps
mV
0.4
tr
Output Rise/Fall Times Q
325
575
325
575
325
575
ps
tf
(20% 80%)
1. Skews are specified for identical LOW-to-HIGH or HIGH-to-LOW transitions.
2. Minimum input swing for which AC parameters guaranteed. The device has a DC gain of 40.
3. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between VPPmin and 1V. The lower end of the CMR range is dependent on VEE and is
equal to VEE + 2.5V.
319
MOTOROLA
MOTOROLA
Differential Receiver
MC10EL16
MC100EL16
NC 1
VCC
VBB
VEE
PIN DESCRIPTION
PIN
FUNCTION
D
Q
VBB
Data Inputs
Data Outputs
Ref. Voltage Output
12/93
320
REV 2
MC10EL16 MC100EL16
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND)
40C
Symbol
Characteristic
Min
IEE
Power Supply
Current
10EL
100EL
VBB
Output Reference
Voltage
10EL
100EL
1.43
1.38
VEE
Power Supply
Voltage
10EL
100EL
4.75
4.20
IIH
0C
Typ
Max
18
18
22
22
5.2
4.5
Min
1.30
1.26
1.38
1.38
5.5
5.5
4.75
4.20
25C
Typ
Max
18
18
22
22
5.2
4.5
Min
1.27
1.26
1.35
1.38
5.5
5.5
4.75
4.20
150
85C
Typ
Max
18
18
22
22
5.2
4.5
150
Min
1.25
1.26
1.31
1.38
5.5
5.5
4.75
4.20
Typ
Max
Unit
18
21
22
26
mA
1.19
1.26
5.5
5.5
150
Unit
5.2
4.5
150
0C
25C
85C
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
tPLH
tPHL
Propagation Delay
to Output
(Diff)
(SE)
125
75
250
250
375
425
175
125
250
250
325
375
175
125
250
250
325
375
205
155
280
280
355
405
tSKEW
20
20
20
VPP
VCMR
ps
5
150
0.4
150
See3
150
See3
0.4
0.4
150
See3
0.4
ps
mV
See3
tr
Output Rise/Fall Times Q
100
225
350
100
225
350
100
225
350
100
225
350
ps
tf
(20% 80%)
1. Duty cycle skew is the difference between a TPLH and TPHL propagation delay through a device.
2. Minimum input swing for which AC parameters guaranteed. The device has a DC gain of 40.
3. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between VPPmin and 1V. The lower end of the CMR range is dependent on VEE and is
equal to VEE + 2.5V.
321
MOTOROLA
MOTOROLA
Low-Voltage Quad
Differential Receiver
MC100EL17
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D-04
MOTOROLA
322
MOTOROLA
MC100EL29
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D-04
323
MOTOROLA
MOTOROLA
Triple D Flip-Flop
With Set and Reset
MC100EL30
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D-04
MOTOROLA
324
MOTOROLA
D FlipFlop
With Set and Reset
MC10EL31
MC100EL31
8
1
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
VCC
TRUTH TABLE
Flip Flop
CLK
VEE
325
CLK
L
H
X
X
X
L
L
H
L
H
L
L
L
H
H
Z
Z
X
X
X
L
H
H
L
Undef
12/93
REV 2
MC10EL31 MC100EL31
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND)
40C
Symbol
Characteristic
Min
IEE
Power Supply
Current
10EL
100EL
VEE
Power Supply
Voltage
10EL
100EL
IIH
4.75
4.20
0C
Typ
Max
27
27
32
32
5.2
4.5
5.5
5.5
Min
4.75
4.20
25C
Typ
Max
27
27
32
32
5.2
4.5
5.5
5.5
150
Min
4.75
4.20
85C
Typ
Max
27
27
32
32
5.2
4.5
5.5
5.5
150
Min
4.75
4.20
Typ
Max
Unit
27
31
32
37
mA
5.2
4.5
5.5
5.5
150
Max
Unit
150
Characteristic
Min
Typ
2.0
2.5
315
295
465
455
0C
Max
Min
Typ
2.2
2.8
365
345
465
455
25C
Max
Min
Typ
2.2
2.8
375
355
475
465
85C
Max
Min
Typ
2.2
2.8
430
400
530
510
fMAX
Maximum Toggle
Frequency
tPLH
tPHL
Propagation Delay
to Output
tS
tH
Setup Time
Hold Time
150
250
0
100
150
250
0
100
150
250
0
100
150
250
0
100
ps
tRR
Set/Reset Recovery
400
200
400
200
400
200
400
200
ps
tPW
400
tr
tf
100
MOTOROLA
GHz
ps
CLK
S, R
630
630
580
580
400
225
350
100
590
590
400
225
326
350
100
645
645
400
225
350
100
ps
225
350
ps
MOTOROLA
Divider
MC10EL32
MC100EL32
Reset
CLK
VCC
R
2
CLK
VBB
PIN DESCRIPTION
VEE
PIN
FUNCTION
CLK
Reset
VBB
Q
Clock Inputs
Asynch Reset
Ref Voltage Output
Data Ouputs
5/95
327
REV 3
MC10EL32 MC100EL32
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND)
40C
Symbol
Characteristic
Min
0C
Typ
Max
IEE
Power Supply
Current
10EL
100EL
25
25
30
30
VEE
Power Supply
Voltage
10EL
100EL
5.2
4.5
VBB
IIH
1.43
1.38
Min
4.75
4.20
1.30
1.26
25C
Typ
Max
25
25
30
30
5.2
4.5
5.5
5.5
4.75
4.20
1.27
1.26
1.35
1.38
1.38
1.38
150
Min
85C
Typ
Max
25
25
30
30
5.2
4.5
5.5
5.5
Min
4.75
4.20
Typ
Max
Unit
25
29
30
35
mA
5.2
4.5
5.5
5.5
1.19
1.26
150
Max
Unit
1.25 1.31
1.26 1.38
150
150
Characteristic
Min
Typ
2.2
3.0
500
540
fMAX
Maximum Toggle
Frequency
tPLH
tPHL
Propagation Delay
CLK to Q
Reset to Q
360
390
VPP
150
0C
Max
640
690
Min
Typ
2.6
3.0
410
440
500
540
25C
Max
590
640
150
tr
Output Rise/Fall Times Q
100
225
350
100
tf
(20% 80%)
1. Minimum input swing for which AC parameters are guaranteed.
Min
Typ
2.6
3.0
420
440
510
540
85C
Max
600
640
150
225
350
100
Min
Typ
2.6
3.0
450
450
540
550
GHz
630
650
150
225
350
100
ps
mV
225
350
ps
CLK
RESET
MOTOROLA
328
MOTOROLA
Divider
MC10EL33
MC100EL33
Reset
CLK
VCC
R
4
CLK
VBB
PIN DESCRIPTION
VEE
PIN
FUNCTION
CLK
Reset
VBB
Q
Clock Inputs
Asynch Reset
Ref Voltage Output
Data Ouputs
5/95
329
REV 3
MC10EL33 MC100EL33
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND)
40C
Symbol
Characteristic
Min
0C
Typ
Max
33
33
IEE
Power Supply
Current
10EL
100EL
27
27
VEE
Power Supply
Voltage
10EL
100EL
5.2
4.5
VBB
IIH
1.43
1.38
Min
4.75
4.20
1.30
1.26
25C
Typ
Max
27
27
33
33
5.2
4.5
5.5
5.5
4.75
4.20
1.27
1.26
1.35
1.38
1.38
1.38
150
Min
85C
Typ
Max
27
27
33
33
5.2
4.5
5.5
5.5
Min
4.75
4.20
Typ
Max
Unit
27
31
33
37
mA
5.2
4.5
5.5
5.5
1.19
1.26
150
1.25 1.31
1.26 1.38
150
150
Characteristic
Min
Typ
3.4
4.2
Propagation Delay
CLK to Q
Reset to Q
490
310
630
460
150
fMAX
Maximum Toggle
Frequency
tPLH
tPHL
VPP
0C
Max
770
610
Min
Typ
3.8
4.2
540
360
630
460
25C
Max
720
560
150
tr
Output Rise/Fall Times Q
100
225
350
100
tf
(20% 80%)
1. Minimum input swing for which AC parameters are guaranteed.
Min
Typ
3.8
4.2
550
360
640
460
85C
Max
730
560
150
225
350
100
Min
Typ
3.8
4.2
590
380
670
480
Max
760
580
150
225
350
100
Unit
GHz
ps
mV
225
350
ps
CLK
RESET
MOTOROLA
330
MOTOROLA
2, 4, 8
Clock
MC10EL34
Generation Chip
MC100EL34
16
1
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B-05
PIN DESCRIPTION
PIN
FUNCTION
CLK
EN
MR
VBB
Q0
Q1
Q2
EN
NC
CLK
CLK
VBB
MR
VEE
16
15
14
13
12
11
10
D
Q
EN
MR
Divide
ZZ
Hold Q03
Reset Q03
2
Q
R
4
Q
R
8
Q
R
Q0
Q0
VCC
Q1
Q1
VCC
Q2
Q2
Z = Low-to-High Transition
ZZ = High-to-Low Transition
12/93
331
FUNCTION
CLK
REV 2
MC10EL34 MC100EL34
AC/DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND)
40C
Symbol
Characteristic
Min
Typ
0C
Max
Min
Typ
Max
Min
Typ
Max
Typ
Max
Power Supply
Current
VBB
IIH
150
tPLH
tPHL
Propagation CLKQ0
Delay to
CLKQ1,2
Output
MRQ
960
900
750
tSKEW
Within-Device Skew
tS
Setup Time EN
400
400
400
400
ps
tH
Hold Time EN
250
250
250
250
ps
VPP
250
250
250
250
2.0
0.4
2.0
0.4
2.0
0.4
2.0
0.4
275
525
275
525
275
525
275
525
39
39
1.43
1.38
1.30
1.26
1100
Unit
IEE
10EL
100EL
1100
Min
tr
tf
1100
85C
fMAX
VCMR
1100
25C
39
39
1.38
1.38
1.27
1.26
39
39
1.35
1.38
1.25 1.31
1.26 1.38
150
1200
1140
1060
960
900
750
100
1200
1140
1060
MHz
150
960
900
750
100
1200
1140
1060
970
910
790
100
39
42
mA
1.19
1.26
150
1210
1150
1090
ps
100
ps
mV
V
Internal Clock
Disabled
ps
Internal Clock
Enabled
CLK
Q0
Q1
Q2
EN
The EN signal will freeze the internal clocks to the flipflops on the first falling edge of CLK after its assertion. The internal dividers will maintain their state
during the internal clock freeze and will return to clocking once the internal clocks are unfrozen. The outputs will transition to their next states in the same
manner, time and relationship as they would have had the EN signal not been asserted.
MOTOROLA
332
MOTOROLA
JK FlipFlop
MC10EL35
MC100EL35
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
VCC
CLK
TRUTH TABLE
VEE
CLK
Qn+1
L
L
H
H
X
L
H
L
H
X
L
L
L
L
H
Z
Z
Z
Z
X
Qn
L
H
Qn
L
12/93
333
REV 2
MC10EL35 MC100EL35
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND)
40C
Symbol
Characteristic
Min
0C
Typ
Max
IEE
Power Supply
Current
10EL
100EL
27
27
32
32
VEE
Power Supply
Voltage
10EL
100EL
5.2
4.5
IIH
Min
4.75
4.20
25C
Typ
Max
27
27
32
32
5.2
4.5
5.5
5.5
150
Min
4.75
4.20
85C
Typ
Max
27
27
32
32
5.2
4.5
5.5
5.5
150
Min
4.75
4.20
Typ
Max
Unit
27
32
32
37
mA
5.2
4.5
5.5
5.5
150
150
Characteristic
Min
Typ
1.4
2.0
CLK
MR
290
225
515
450
Setup Time
J, K
150
tH
Hold Time
J, K
tRR
Reset Recovery
tPW
400
tr
tf
100
fMAX
Maximum Toggle
Frequency
tPLH
tPHL
Propagation Delay
to Output
tS
MOTOROLA
0C
Max
Min
Typ
1.8
2.2
340
275
515
450
150
250
100
400
200
740
675
25C
Max
Min
Typ
1.8
2.2
350
275
525
450
150
250
100
400
200
690
625
400
225
350
100
85C
Max
Min
Typ
1.8
2.2
395
350
570
525
150
ps
250
100
250
100
ps
400
200
400
200
ps
700
625
400
225
334
350
100
Max
745
700
400
225
350
100
Unit
GHz
ps
ps
225
350
ps
MOTOROLA
2, 4/6
MC100EL38
20
1
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D-04
335
MOTOROLA
MOTOROLA
2/4, 4/6
Clock
MC100EL39
Generation Chip
For information on the MC100EL39,
please refer to the MC100LVEL39
datasheet on page 4-53 in
Chapter 4 of this book.
20
1
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D-04
MOTOROLA
336
MOTOROLA
MC10EL51
MC100EL51
8
1
R 1
VCC
R
D
TRUTH TABLE
Flip-Flop
CLK
CLK
VEE
CLK
12/93
337
REV 2
MC10EL51 MC100EL51
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND)
40C
Symbol
Characteristic
Min
IEE
Power Supply
Current
10EL
100EL
VEE
Power Supply
Voltage
10EL
100EL
IIH
4.75
4.20
0C
Typ
Max
24
24
29
29
5.2
4.5
5.5
5.5
Min
4.75
4.20
25C
Typ
Max
24
24
29
29
5.2
4.5
5.5
5.5
150
Min
4.75
4.20
85C
Typ
Max
24
24
29
29
5.2
4.5
5.5
5.5
150
Min
4.75
4.20
Typ
Max
Unit
24
30
29
36
mA
5.2
4.5
5.5
5.5
150
150
Characteristic
Min
Typ
1.8
2.8
325
305
465
455
Setup Time
150
tH
Hold Time
tRR
0C
Min
Typ
2.2
2.8
375
355
465
455
150
250
100
Reset Recovery
400
200
tPW
400
VPP
150
VCMR
0.4
tr
tf
100
fMAX
Maximum Toggle
Frequency
tPLH
tPHL
Propagation Delay
to Output
tS
Max
25C
Max
Min
Typ
2.2
2.8
385
355
475
465
150
250
100
400
200
85C
Max
Min
Typ
2.2
2.8
Max
Unit
440
410
530
510
150
ps
250
100
250
100
ps
400
200
400
200
ps
GHz
ps
CLK
R
605
605
555
555
400
400
150
225
See2
0.4
350
100
565
565
400
150
225
See2
0.4
350
100
620
620
ps
150
225
See2
0.4
350
100
mV
225
See2
350
ps
MOTOROLA
338
MOTOROLA
MC10EL52
MC100EL52
8
1
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
PIN DESCRIPTION
D 1
VCC
PIN
FUNCTION
D
CLK
Q
Data Input
Clock Input
Data Output
TRUTH TABLE
D
Flip-Flop
CLK
CLK
339
CLK
VEE
12/93
REV 2
MC10EL52 MC100EL52
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND)
40C
Symbol
Characteristic
Min
IEE
Power Supply
Current
10EL
100EL
VEE
Power Supply
Voltage
10EL
100EL
IIH
4.94
4.20
0C
Typ
Max
21
21
25
25
5.2
4.5
5.5
5.5
Min
4.94
4.20
25C
Typ
Max
21
21
25
25
5.2
4.5
5.5
5.5
150
Min
4.75
4.20
85C
Typ
Max
21
21
25
25
5.2
4.5
5.5
5.5
150
Min
4.75
4.20
Typ
Max
Unit
21
24
25
29
mA
5.2
4.5
5.5
5.5
150
150
Characteristic
0C
Typ
1.8
2.5
225
335
Setup Time
125
tH
Hold Time
150
tPW
400
400
400
400
ps
VPP
150
150
150
150
mV
VCMR
0.4
0.4
0.6
0.8
tr
tf
Maximum Toggle
Frequency
tPLH
tPHL
Propagation Delay
to Output
tS
Min
Typ
2.2
2.8
275
365
125
50
150
515
Max
Min
Typ
2.2
2.8
275
365
125
50
150
85C
Min
fMAX
Max
25C
465
Max
Min
Typ
2.2
2.8
320
410
125
ps
50
150
50
ps
465
Max
Unit
GHz
510
ps
CLK
100
225
1.6
1.2
See3
See3
0.4
0.4
0.6
0.8
350
100
225
1.6
1.2
See3
See3
0.4
0.4
0.6
0.8
350
100
225
1.6
1.2
See3
See3
0.4
0.4
0.6
0.8
350
100
1.6
1.2
See3
See3
225
350
ps
MOTOROLA
340
MOTOROLA
Dual Differential
2:1 Multiplexer
MC100EL56
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D-04
341
MOTOROLA
MOTOROLA
MC10EL57
MC100EL57
16
1
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B-05
15
14
13
12
PIN DESCRIPTION
PIN
FUNCTION
D03
SEL0,1
VBB
Q0
10
4:1
FUNCTION TABLE
D0
D0
D1
D1
D2
D2
D3
D3
SEL1
SEL0
DATA OUT
L
L
H
H
L
H
L
H
D0
D1
D2
D3
Characteristic
Rating
Unit
VEE
8.0 to 0
VDC
VI
0 to 6.0
VDC
Iout
Output Current
50
100
mA
TA
40 to +85
VEE
Operating Range1,2
5.7 to 4.2
Continuous
Surge
1. Absolute maximum rating, beyond which, device life may be impaired, unless otherwise specified on an individual data sheet.
2. Parametric values specified at:
10EL Series:
4.94V to 5.50V
100EL Series:
4.20V to 5.50V
1/95
342
REV 1
MC10EL57 MC100EL57
10EL SERIES
DC CHARACTERISTICS (VEE = VEE(min) VEE(max); VCC = GND1)
40C
Symbol
Characteristic
0C
25C
85C
Min
Max
Min
Max
Min
Max
Min
Max
Unit
VOH
1080
890
1020
840
980
810
910
720
mV
VOL
1950
1650
1950
1630
1950
1630
1950
1595
mV
VIH
1230
890
1170
840
1130
810
1060
720
mV
VIL
1950
1500
1950
1480
1950
1480
1950
1445
mV
IIL
Input LOW Current
0.5
0.5
0.5
0.3
A
1. 10EL circuits are designed to meet the DC specifications shown in the table after thermal equilibrium has been established. The circuit is in
a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. Outputs are terminated through
a 50 resistor to 2.0V except where otherwise specified on the individual data sheets.
100EL SERIES
DC CHARACTERISTICS (VEE = VEE(min) VEE(max); VCC = GND1)
40C
Symbol
Characteristic
Min
Typ
0C to 85C
Max
Min
Typ
Max
Unit
Condition
VOH
1085
1005
880
1025
955
880
mV
VIN = VIH(max)
VOL
1830
1695
1555
1810
1705
1620
mV
or VIL(min)
VOHA
1095
1035
mV
VIN = VIH(max)
VOLA
1555
1610
mV
or VIL(min)
VIH
1165
880
1165
880
mV
VIL
1810
1475
1810
1475
mV
IIL
Input LOW Current
0.5
0.5
A
VIN = VIL(max)
1. This table replaces the three tables traditionally seen in ECL 100K data books. The same DC parameter values at VEE = 4.5V now apply across
the full VEE range of 4.2V to 5.5V. Outputs are terminated through a 50 resistor to 2.0V except where otherwise specified on the individual
data sheets.
Characteristic
Min
Max
Min
Typ
Max
Min
Max
Min
Max
Unit
24
27
mA
1.19
1.26
150
580
710
ps
100
ps
IIH
tPLH
tPHL
Propagation DATAQ/Q
Delay
SELQ/Q
tSKEW
VPP
250
2.0
0.4
2.0
0.4
2.0
0.4
2.0
0.4
125
375
125
375
125
375
125
375
1.30
1.26
1.38
1.38
1.27
1.26
150
350
440
550
690
24
24
Typ
VBB
1.43
1.38
24
24
Typ
85C
Power Supply
Current
tr
tf
24
24
25C
IEE
VCMR
10EL
100EL
Typ
0C
1.35
1.38
150
350
440
550
690
100
1.25 1.31
1.26 1.38
150
360
440
100
560
690
380
460
100
mV
250
250
250
V
343
ps
MOTOROLA
MOTOROLA
2:1 Multiplexer
MC10EL58
MC100EL58
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
NC 1
Da
VCC
SEL
Data
H
L
a
b
MUX
Db
SEL
PIN DESCRIPTION
VEE
PIN
FUNCTION
D0, D1
Q
Data Inputs
Data Outputs
Characteristic
IEE
Power Supply
Current
10EL
100EL
VEE
Power Supply
Voltage
10EL
100EL
IIH
Min
4.94
4.20
0C
Typ
Max
14
14
17
17
5.2
4.5
5.5
5.5
Min
4.94
4.20
25C
Typ
Max
14
14
17
17
5.2
4.5
5.5
5.5
150
Min
4.75
4.20
85C
Typ
Max
14
14
17
17
5.2
4.5
5.5
5.5
150
Min
4.75
4.20
Typ
Max
Unit
14
16
17
19
mA
5.2
4.5
5.5
5.5
150
Unit
150
0C
25C
85C
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
tPLH
tPHL
Propagation Delay
to Output
D to Q
SEL to Q
60
90
220
250
380
410
110
140
220
250
330
360
120
150
230
260
340
370
140
170
250
280
360
390
tr
tf
100
225
350
100
225
350
100
225
350
100
225
350
ps
12/93
344
REV 2
ps
MOTOROLA
MC100EL59
20
1
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D-04
345
MOTOROLA
MOTOROLA
MC10EL89
8
1
Q0
VCC
Q0
Q1
Q1
VEE
PIN DESCRIPTION
PIN
FUNCTION
D
Q0, Q1
Data Inputs
Data Outputs
12/93
346
REV 2
MC10EL89
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND)
40C
Symbol
Characteristic
Min
0C
Typ
Max
23
28
Min
25C
Typ
Max
23
28
Min
85C
Typ
Max
23
Min
Typ
Max
Unit
28
23
28
mA
IEE
VOH
1.23
1.10
0.98
1.17
1.05 0.93
1.13
0.96
0.81
VOL
2.90
2.72
2.58
3.00
2.70 2.56
3.00
2.67
2.51
VEE
4.75
5.5
4.75
5.5
4.75
5.5
5.5
IIH
150
150
150
4.75
150
Characteristic
0C
25C
85C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
200
340
480
250
340
430
260
350
440
310
400
490
ps
20
20
20
20
tPLH
tPHL
Propagation Delay to
Output
tSKEW
Within-Device Skew
VPP
150
VCMR
0.4
tr
tf
205
150
330
See2
0.4
455
205
150
330
See2
0.4
455
205
150
330
See2
0.4
455
205
mV
330
See2
455
ps
1. Minimum input swing for which AC parameters are guaranteed. The device has a DC gain of 40.
2. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between VPPmin and 1V. The lower end of the CMR range is dependent on VEE and is
equal to VEE + 2.5V.
DC BLOCKING CAPACITORS
75
75 COAX
0.1F
75
EL89
75
150
150
0.1F
75 COAX
75
VEE
347
MOTOROLA
MOTOROLA
MC100EL90
20
1
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D-04
MOTOROLA
348
MOTOROLA
MC100EL91
20
1
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D-04
349
MOTOROLA
MOTOROLA
350
MOTOROLA
MC10ELT20
MC100ELT20
NC 1
TTL
VCC
D0
PIN DESCRIPTION
PECL
Q
NC
NC
GND
PIN
FUNCTION
Q
D
VCC
GND
1/95
351
REV 2
MC10ELT20 MC100ELT20
MAXIMUM RATINGS*
Symbol
Parameter
VCC
VIN
Input Voltage
IOUT
TA
TSTG
Value
Unit
7.0
0 to VCC
50
100
mA
40 to 85
55 to +150
Continuous
Surge
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
Recommended Operating Conditions.
Characteristic
Min
Typ
Max
Unit
Condition
IIH
20
VIN = 2.7V
IIHH
100
VIN = 7.0V
IIL
0.6
mA
VIN = 0.5V
1.2
VIK
VIH
VIL
2.0
IIN = 18mA
V
0.8
0C
25C
85C
Characteristic
Min
Max
Min
Max
Min
Typ
Max
Min
Max
Unit
Condition
VOH
3.920
3.915
4.11
4.12
3.980
3.975
4.16
4.12
4.020
3.975
4.10
4.05
4.19
4.12
4.080
3.975
4.27
4.12
VCC = 5.0V
VOL
3.05
3.17
3.350
3.445
3.05
3.19
3.37
3.38
3.05
3.19
3.25
3.30
3.37
3.38
3.05
3.19
3.40
3.35
VCC = 5.0V
16
mA
ICC
Power Supply Current
1. Levels will vary 1:1 with VCC.
16
16
16
Characteristic
0C
25C
85C
Min
Max
Min
Max
Min
Typ
Max
Min
Max
Unit
tPLH
Propagation Delay1
0.6
1.2
0.65
1.45
0.9
1.2
1.5
0.6
1.35
ns
tPHL
Propagation Delay1
0.4
1.0
0.45
1.05
0.5
0.8
1.1
0.7
1.30
ns
tr/tf
0.15
1.5
0.15
1.5
0.15
1.5
0.15
1.5
ns
fMAX
Maximum Input
Frequency
100
100
100
100
Condition
2080%
MHz
MOTOROLA
352
MOTOROLA
MC10ELT21
MC100ELT21
8
1
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
NC 1
VCC
PIN DESCRIPTION
D0
TTL
Q0
PIN
FUNCTION
Q
D
VCC
VBB
GND
TTL Output
Diff PECL Inputs
+5.0V Supply
Reference Output
Ground
PECL
D0
NC
VBB
GND
7/96
353
REV 3
MC10ELT21 MC100ELT21
MAXIMUM RATINGS*
Symbol
Parameter
VCC
TA
TSTG
Value
Unit
7.0
40 to 85
55 to +150
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
Recommended Operating Conditions.
Characteristic
VOH
VOL
ICCH
ICCL
IOS
Min
Typ
Max
Unit
2.4
Condition
IOH = 3.0mA
0.5
IOL = 24mA
20
29
mA
22
32
mA
60
mA
150
Characteristic
Min
Max
0C
Min
25C
Max
150
Min
Typ
Max
Min
Unit
150
Condition
IIL
VCMR
2.2
VPP
Minimum
Peak-to-Peak Input1
200
VIH
Input HIGH
Voltage
10ELT
100ELT
3.770
3.835
4.110
4.120
3.830
3.835
4.16
4.12
3.870
3.835
4.19
4.12
3.930
3.835
4.265
4.120
VCC = 5.0V
VIL
Input LOW
Voltage
10ELT
100ELT
3.05
3.19
3.500
3.525
3.05
3.19
3.520
3.525
3.05
3.19
3.520
3.525
3.05
3.19
3.550
3.525
VCC = 5.0V
VBB
Reference
Output
10ELT
100ELT
3.57
3.62
3.70
3.74
3.62
3.62
3.73
3.74
3.65
3.62
3.75
3.74
3.69
3.62
3.81
3.75
VCC = 5.0V
Condition
0.5
VCC
150
Max
IIH
0.5
150
85C
0.5
2.2
VCC
200
0.5
2.2
VCC
200
2.2
VCC
200
V
mV
Characteristic
0C
25C
Min
Max
Min
Max
Min
tPLH
Propagation Delay1
2.0
5.5
2.0
5.5
tPHL
Propagation Delay1
2.0
5.5
2.0
5.5
MOTOROLA
354
Typ
85C
Max
Min
Max
Unit
2.0
5.5
2.0
5.5
ns
CL = 20pF
2.0
5.5
2.0
5.5
ns
CL = 20pF
MOTOROLA
MC10ELT22
MC100ELT22
8
1
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
Q0 1
VCC
Q0
D0
2
PECL
Q1
Q1
PIN DESCRIPTION
TTL
D1
PIN
FUNCTION
GND
Qn
Dn
VCC
GND
7/96
355
REV 3
MC10ELT22 MC100ELT22
MAXIMUM RATINGS*
Symbol
Parameter
VCC
VIN
Input Voltage
IOUT
TA
TSTG
Value
Unit
7.0
0 to VCC
50
100
mA
40 to 85
55 to +150
Continuous
Surge
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
Recommended Operating Conditions.
Characteristic
Min
Typ
Max
Unit
Condition
IIH
20
VIN = 2.7V
IIHH
100
VIN = 7.0V
IIL
0.6
mA
VIN = 0.5V
1.2
VIK
VIH
VIL
2.0
IIN = 18mA
V
0.8
0C
25C
85C
Characteristic
Min
Max
Min
Max
Min
Typ
Max
Min
Max
Unit
Condition
VOH
3.920
3.915
4.11
4.12
3.980
3.975
4.16
4.12
4.020
3.975
4.10
4.05
4.19
4.12
4.090
3.975
4.28
4.12
VCC = 5.0V
VOL
3.05
3.17
3.350
3.445
3.05
3.19
3.37
3.38
3.05
3.19
3.25
3.30
3.37
3.38
3.05
3.19
3.40
3.35
VCC = 5.0V
22
mA
ICC
Power Supply Current
1. Levels will vary 1:1 with VCC.
22
22
22
Characteristic
0C
25C
85C
Min
Max
Min
Max
Min
Typ
Max
Min
Max
Unit
tPLH
Propagation Delay1
0.6
1.2
0.65
1.45
0.9
1.2
1.5
0.6
1.35
ns
tPHL
Propagation Delay1
0.4
1.0
0.45
1.05
0.5
0.8
1.1
0.7
1.30
ns
tr/tf
0.4
1.6
0.4
1.6
0.4
1.6
0.4
1.6
ns
fMAX
Maximum Input
Frequency
100
100
100
100
Condition
2080%
MHz
MOTOROLA
356
MOTOROLA
MC100ELT23
8
1
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
D0 1
VCC
D0
Q0
2
PECL
TTL
D1
Q1
D1
GND
PIN DESCRIPTION
PIN
FUNCTION
Qn
Dn
VCC
GND
TTL Outputs
Diff PECL Inputs
+5.0V Supply
Ground
7/96
357
REV 3
MC100ELT23
MAXIMUM RATINGS*
Symbol
Parameter
VCC
TA
TSTG
Value
Unit
7.0
40 to 85
55 to +150
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
Recommended Operating Conditions.
Characteristic
VOH
VOL
ICCH
ICCL
IOS
Min
Typ
Max
Unit
2.4
IOH = 3.0mA
0.5
IOL = 24mA
33
mA
36
mA
60
mA
23
26
150
Condition
Characteristic
Min
Max
0C
Min
25C
Max
150
Min
Typ
150
85C
Max
Min
Unit
150
Condition
IIH
IIL
0.5
VCMR
2.2
VPP
Minimum
Peak-to-Peak Input1
200
VIH
Input HIGH
Voltage
10ELT
100ELT
3.770
3.835
4.110
4.120
3.830
3.835
4.16
4.12
3.870
3.835
4.19
4.12
3.930
3.835
4.265
4.120
VCC = 5.0V
VIL
Input LOW
Voltage
10ELT
100ELT
3.05
3.19
3.500
3.525
3.05
3.19
3.520
3.525
3.05
3.19
3.520
3.525
3.05
3.19
3.550
3.525
VCC = 5.0V
Condition
0.5
VCC
150
Max
0.5
2.2
VCC
200
0.5
2.2
VCC
200
2.2
VCC
200
V
mV
Characteristic
0C
25C
Min
Max
Min
Max
Min
Typ
85C
Max
Min
Max
Unit
tPLH
Propagation Delay1
2.0
5.5
2.0
5.5
2.0
5.5
2.0
5.5
ns
CL = 20pF
tPHL
Propagation Delay1
2.0
5.5
2.0
5.5
2.0
5.5
2.0
5.5
ns
CL = 20pF
MOTOROLA
358
MOTOROLA
MC10ELT24
MC100ELT24
8
1
VEE 1
VCC
TTL
D
2
ECL
NC
NC
GND
PIN DESCRIPTION
PIN
FUNCTION
Q
D
VCC
VEE
GND
1/95
359
REV 2
MC10ELT24 MC100ELT24
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
7.0
VEE
8.0
VIN
Input Voltage
IOUT
TA
TSTG
40 to VCC
50
100
mA
40 to 85
55 to +150
Continuous
Surge
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
Recommended Operating Conditions.
TTL INPUT DC CHARACTERISTICS (VCC = 4.5V to 5.5V; VEE = 4.2V to 5.5V 100ELT, 4.94V to 5.5V 10ELT;
TA = 40C to 85C)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
IIH
20
VIN = 2.7V
IIHH
100
VIN = 7.0V
IIL
0.6
mA
VIN = 0.5V
1.2
VIK
VIH
VIL
2.0
0.8
Characteristic
(VCC = 4.5V to 5.5V; VEE = 4.2V to 5.5V 100ELT, 4.94V to 5.5V 10ELT;
TA = 40C to 85C)
40C
Symbol
IIN = 18mA
0C
25C
85C
Min
Max
Min
Max
Min
Typ
Max
Min
Max
Unit
VOH
Output HIGH
Voltage
10ELT
100ELT
1080
1085
890
880
1020
1025
840
880
980
1025
910
1025
720
880
mV
955
810
880
VOL
Output LOW
Voltage
10ELT
100ELT
1950
1830
1650
1555
1950
1810
1630
1620
1950
1810
1630
1620
1950
1810
1595
1620
mV
1705
ICC
4.5
mA
IEE
18
18
12.5
18
18
mA
Condition
AC CHARACTERISTICS (VCC = 4.5V to 5.5V; VEE = 4.2V to 5.5V 100ELT, 4.94V to 5.5V 10ELT; TA = 40C to 85C)
40C
Symbol
Characteristic
0C
25C
85C
Min
Max
Min
Max
Min
Typ
Max
Min
Max
Unit
0.7
1.3
0.65
1.25
0.65
0.95
1.25
0.65
1.25
ns
0.80
1.10
0.70
1.30
ns
1.25
0.25
1.25
ns
tPLH
Propagation Delay1
tPHL
Propagation Delay1
0.4
1.0
0.45
1.05
0.50
tr/tf
0.25
1.25
0.25
1.25
0.25
fMAX
Maximum Input
Frequency
100
100
100
100
Condition
2080%
MHz
MOTOROLA
360
MOTOROLA
MC10ELT25
MC100ELT25
8
1
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
VEE 1
D0
TTL
VCC
Q0
ECL
D0
NC
VBB
GND
PIN DESCRIPTION
PIN
FUNCTION
D
Q
VCC
VEE
VBB
GND
1/95
361
REV 2
MC10ELT25 MC100ELT25
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
7.0
VEE
8.0
VIN
Input Voltage
IOUT
TA
TSTG
0 to VCC
50
100
mA
40 to 85
55 to +150
Continuous
Surge
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
Recommended Operating Conditions.
TTL OUTPUT DC CHARACTERISTICS (VCC = 4.5V to 5.5V; VEE = 4.2V to 5.5V 100ELT, 4.94V to 5.5V 10ELT;
TA = 40C to 85C)
Symbol
Characteristic
VOH
VOL
ICCH
ICCL
IEE
IOS
Min
Max
Unit
2.4
Condition
IOH = 3.0mA
0.5
IOL = 24mA
11
16
mA
13
18
mA
15
21
mA
60
mA
150
(VCC = 4.5V to 5.5V; VEE = 4.2V to 5.5V 100ELT, 4.94V to 5.5V 10ELT;
TA = 40C to 85C)
40C
Symbol
Typ
Characteristic
Min
Max
0C
Min
25C
Max
150
Min
Typ
Max
Min
Max
Unit
150
IIH
IIL
VCMR
VEE +
2.2
VPP
Minimum Peak-to-Peak
Input1
200
VIH
1230
1165
890
880
1170
1165
840
880
1130
1165
810
880
1060
1165
720
880
VIL
1950
1810
1500
1475
1950
1810
1480
1475
1950
1810
1480
1475
1950
1810
1445
1475
VBB
Reference Output
1.43
1.38
1.30
1.26
1.38
1.38
1.27
1.26
1.35
1.38
1.25
1.26
1.31
1.38
1.19
1.26
0.5
10ELT
100ELT
150
85C
0.5
VCC
150
0.5
VEE +
2.2
VCC
200
0.5
VEE +
2.2
VCC
200
Condition
VEE +
2.2
VCC
200
V
mV
AC CHARACTERISTICS (VCC = 4.5V to 5.5V; VEE = 4.2V to 5.5V 100ELT, 4.94V to 5.5V 10ELT; TA = 40C to 85C)
40C
Symbol
0C
25C
Characteristic
Min
Max
Min
Max
Min
tPLH
Propagation Delay
1.7
3.6
1.7
3.6
tPHL
Propagation Delay
2.6
4.1
2.6
4.1
MOTOROLA
362
Typ
85C
Max
Min
Max
Unit
Condition
1.7
3.6
1.7
3.6
ns
CL = 20pF
2.6
4.1
2.6
4.1
ns
CL = 20pF
MOTOROLA
Product Preview
MC10ELT26
MC100ELT26
8
1
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
NC 1
VCC
Q0
Q1
GND
TTL
D
VBB
PECL
PIN
FUNCTION
Qn
D
VCC
VBB
GND
TTL Outputs
Diff PECL Input
+5.0V Supply
Reference Output
Ground
This document contains information on a product under development. Motorola reserves the right to
change or discontinue this product without notice.
1/95
363
REV 2
MOTOROLA
Advance Information
MC10ELT28
MC100ELT28
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
DECL 1
VCC
QTTL
DECL
PECL
PIN DESCRIPTION
TTL
QECL
DTTL
QECL
GND
PIN
FUNCTION
QTTL
DTTL
QECL
DECL
VCC
GND
TTL Output
TTL Inputs
Diff ECL Outputs
Diff ECL Inputs
+5.0V Supply
Ground
MAXIMUM RATINGS*
Symbol
Parameter
VCC
TA
Value
Unit
7.0
40 to 85
TSTG
Storage Temperature Range
55 to +150
C
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
Recommended Operating Conditions.
This document contains information on a new product. Specifications and information herein are subject to
change without notice.
1/95
364
REV 2
MC10ELT28 MC100ELT28
TTL OUTPUT DC CHARACTERISTICS (VCC = 4.75V to 5.25V; TA = 40C to 85C)
Symbol
Characteristic
VOH
VOL
ICCH
ICCL
IOS
Min
Typ
Max
Unit
2.4
Condition
IOH = 3.0mA
0.5
IOL = 24mA
27
40
mA
29
42
mA
60
mA
Max
Unit
20
VIN = 2.7V
150
Characteristic
Min
Typ
Condition
IIH
IIHH
100
VIN = 7.0V
IIL
0.6
mA
VIN = 0.5V
1.2
VIK
VIH
VIL
2.0
IIN = 18mA
V
0.8
0C
25C
85C
Characteristic
Min
Max
Min
Max
Min
Typ
Max
Min
Max
Unit
Condition
VOH
3.920
3.915
4.11
4.12
3.980
3.975
4.16
4.12
4.020
3.975
4.10
4.05
4.19
4.12
4.080
3.975
4.27
4.12
VCC = 5.0V
VOL
3.05
3.17
3.350
3.445
3.05
3.19
3.37
3.38
3.05
3.19
3.25
3.30
3.37
3.38
3.05
3.19
3.40
3.35
VCC = 5.0V
Max
Unit
Condition
150
Characteristic
Min
Max
0C
Min
Max
Min
Typ
Max
Min
IIL
0.5
VCMR
2.2
VPP
Minimum
Peak-to-Peak Input1
200
VIH
Input HIGH
Voltage
10ELT
100ELT
3.770
3.835
4.110
4.120
3.830
3.835
4.16
4.12
3.870
3.835
4.19
4.12
3.930
3.835
4.265
4.120
VCC = 5.0V
VIL
Input LOW
Voltage
10ELT
100ELT
3.05
3.19
3.500
3.525
3.05
3.19
3.520
3.525
3.05
3.19
3.520
3.525
3.05
3.19
3.550
3.525
VCC = 5.0V
tPLH
Prop
Delay
DECL to QTTL
DTTL to QECL
2.0
0.6
5.5
1.2
2.0
0.65
5.5
1.45
2.0
0.9
5.5
1.5
2.0
0.6
5.5
1.35
ns
CL = 20pF
1.2
Prop
Delay
DECL to QTTL
DTTL to QECL
2.0
0.4
5.5
1.0
2.0
0.45
5.5
1.05
2.0
0.5
5.5
1.1
2.0
0.7
5.5
1.3
ns
CL = 20pF
0.8
tr, tf
Rise/Fall Times QECL 0.15
1.5
0.15
1. 200mV input guarantees full logic swing at the output.
1.5
0.15
1.5
0.15
1.5
ns
20% 80%
150
85C
IIH
tPHL
150
25C
0.5
VCC
2.2
150
0.5
VCC
200
2.2
VCC
200
365
0.5
2.2
VCC
200
V
mV
MOTOROLA
MOTOROLA
366
41
MOTOROLA
MOTOROLA
MC100LVE111
LOW-VOLTAGE
1:9 DIFFERENTIAL
ECL/PECL CLOCK DRIVER
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
The MC100LVE111, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows
the LVE111 to be used for high performance clock distribution in +3.3V systems. Designers can take advantage of the LVE111s
performance to distribute low skew clocks across the backplane or the board. In a PECL environment, series or Thevenin line
terminations are typically used as they require no additional power supplies. For systems incorporating GTL, parallel termination
offers the lowest power by taking advantage of the 1.2V supply as a terminating voltage. For more information on using PECL,
designers should refer to Motorola Application Note AN1406/D.
12/94
42
REV 1
MC100LVE111
Q0
Q0
Q1 VCCO Q1
Q2
Q2
25
24
23
20
19
22
21
VEE
26
18
Q3
NC
27
17
Q3
IN
28
16
Q4
15
VCCO
PIN NAMES
Pins
Function
IN, IN
Q0, Q0Q8, Q8
VBB
VCC
IN
14
Q4
VBB
13
Q5
NC
12
Q5
Q8
Q8
Q7
VCCO Q7
10
11
Q6
Q6
LOGIC SYMBOL
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
IN
IN
Q5
Q5
Q6
Q6
Q7
Q7
Q8
Q8
VBB
43
MOTOROLA
MC100LVE111
ECL DC CHARACTERISTICS
40C
Symbol
0C
25C
85C
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
VOH
1.025
0.955
0.880
1.025
0.955
0.880
1.025
0.955
0.880
1.025
0.955
0.880
VOL
1.810
1.705
1.620
1.810
1.705
1.620
1.810
1.705
1.620
1.810
1.705
1.620
VIH
1.165
0.880
1.165
0.880
1.165
0.880
1.165
0.880
VIL
1.810
1.475
1.810
1.475
1.810
1.475
1.810
1.475
VBB
Output Reference
Voltage
1.38
1.26
1.38
1.26
1.38
1.26
1.38
1.26
VEE
3.0
3.8
3.0
3.8
3.0
3.8
3.0
3.8
IIH
150
IEE
78
mA
150
55
150
66
55
150
66
55
66
65
PECL DC CHARACTERISTICS
40C
Symbol
Characteristic
0C
25C
85C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
VOH
2.275
2.345
2.420
2.275
2.345
2.420
2.275
2.345
2.420
2.275
2.345
2.420
VOL
1.490
1.595
1.680
1.490
1.595
1.680
1.490
1.595
1.680
1.490
1.595
1.680
VIH
2.135
2.420
2.135
2.420
2.135
2.420
2.135
2.420
VIL
1.490
1.825
1.490
1.825
1.490
1.825
1.490
1.825
VBB
1.92
2.04
1.92
2.04
1.92
2.04
1.92
2.04
VCC
3.0
3.8
3.0
3.8
3.0
3.8
3.0
IIH
IEE
150
55
150
66
55
150
66
55
66
65
3.8
150
78
mA
1. These values are for VCC = 3.3V. Level Specifications will vary 1:1 with VCC.
Typ
0C
Max
Min
650
700
435
385
Typ
25C
Max
Min
625
675
440
390
Typ
85C
Characteristic
Min
Max
Min
630
680
445
395
Typ
Max
tPLH
tPHL
400
350
tskew
Within-Device Skew
Part-to-Part Skew (Diff)
VPP
500
VCMR
1.5
0.4
1.5
0.4
1.5
0.4
1.5
0.4
tr/tf
200
600
200
600
200
600
200
600
Unit
Condition
ps
50
250
50
200
500
50
200
500
635
685
50
200
500
Note 1
Note 2
ps
Note 3
mV
Note 4
Note 5
ps
20%80%
1. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals. See Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 112).
2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. See
Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 112).
3. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device.
4. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited
for the E111 as a differential input as low as 50 mV will still produce full ECL levels at the output.
5. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level
must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to VPP(min).
MOTOROLA
44
MOTOROLA
MC100LVE164
LOW VOLTAGE
16:1 MULTIPLEXER
NC
A11
A12
A13
A14
A15
VCC
NC
24
23
22
21
20
19
18
17
NC
25
16
NC
A10
26
15
SEL3
A9
27
14
VCC
A8
28
13
A7
29
12
A6
30
11
SEL2
A5
31
10
SEL1
NC
32
SEL0
MC100LVE164
FA SUFFIX
TQFP PACKAGE
CASE 873A02
LOGIC DIAGRAM
A0
NC
VEE
A0
A1
A2
A3
A4
NC
A1
16:1
Q
A14
PIN NAMES
Pin
A0 A15
SEL[0:3]
Q, Q
A15
Function
Data Inputs
Select Inputs
Output
SEL0
SEL1
SEL2
SEL3
6/95
45
REV 1
MC100LVE164
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
40C
Symbol
Characteristic
IIH
IEE
Min
Typ
0C
Max
Min
Typ
150
34
25C
Max
Min
Typ
150
45
34
85C
Max
Min
Typ
150
45
35
45
37
Max
Unit
150
45
mA
Characteristic
tPLH
tPHL
Propagation Delay
to Output
A Input
SEL0
SEL1
SEL2
SEL3
tSKEW
0C
25C
85C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
350
500
400
400
400
600
700
675
675
550
850
900
900
900
700
350
500
400
400
400
600
700
675
675
550
850
900
900
900
700
350
500
400
400
400
600
700
675
675
550
850
900
900
900
700
350
500
400
400
400
600
700
675
675
550
850
900
900
900
700
ps
75
75
50
tr
Rise/Fall Times
20% 80% 275 400 550 275 400 550 275 400
tf
1. Within Device skew is defined as the difference in the A to Q delay between the 16 different A inputs.
50
550
275
400
ps
550
ps
FUNCTION TABLE
SEL3
SEL2
SEL1
SEL0
Data
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
MOTOROLA
46
MOTOROLA
MC100LVE210
MC100E210
ECL/PECL Compatible
The MC100LVE210 is a low voltage, low skew dual differential ECL
fanout buffer designed with clock distribution in mind. The device features
two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device
features fully differential clock paths to minimize both device and system
skew. The dual buffer allows for the fanout of two signals through a single
chip, thus reducing the skew between the two fundamental signals from a
parttopart skew down to an outputtooutput skew. This capability
reduces the skew by a factor of 4 as compared to using two LVE111s to
accomplish the same task. The MC100LVE210 works from a 3.3V
supply while the MC100E210 provides identical function and
performance from a standard 4.5V 100E voltage supply.
LOW VOLTAGE
DUAL 1:4, 1:5 DIFFERENTIAL
FANOUT BUFFER
7/95
47
REV 1
MC100LVE210 MC100E210
Qa0
Qa2
25
24
19
23
22
21
20
VEE
26
18
Qa3
VBB
27
17
Qa3
CLKa
28
16
Qb0
VCC
PIN NAMES
Pinout: 28Lead PLCC
(Top View)
15
VCCO
CLKa
14
Qb0
CLKb
13
Qb1
CLKb
12
Qb1
5
Qb4
10
Pins
Function
CLKa, CLKb
Qa0:4, Qb0:3
VBB
11
Qb2
LOGIC SYMBOL
Qa0
Qa0
CLKa
Qa1
CLKa
Qa1
Qa2
Qa2
Qa3
Qa3
Qb0
Qb0
CLKb
Qb1
CLKb
Qb1
Qb2
Qb2
Qb3
Qb3
Qb4
Qb4
VBB
MOTOROLA
48
MC100LVE210 MC100E210
MC100LVE210
ECL DC CHARACTERISTICS
40C
Symbol
0C
25C
85C
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
VOH
1.085
1.005
0.880
1.025
0.955
0.880
1.025
0.955
0.880
1.025
0.955
0.880
VOL
1.830
1.695
1.555
1.810
1.705
1.620
1.810
1.705
1.620
1.810
1.705
1.620
VIH
1.165
0.880
1.165
0.880
1.165
0.880
1.165
0.880
VIL
1.810
1.475
1.810
1.475
1.810
1.475
1.810
1.475
VBB
Output Reference
Voltage
1.38
1.26
1.38
1.26
1.38
1.26
1.38
1.26
VEE
3.0
3.8
3.0
3.8
3.0
3.8
3.0
3.8
IIH
150
150
150
150
IEE
55
55
55
65
mA
MC100LVE210
PECL DC CHARACTERISTICS
40C
Symbol
Characteristic
0C
25C
85C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
VOH
2.215
2.295
2.42
2.275
2.345
2.420
2.275
2.345
2.420
2.275
2.345
2.420
VOL
1.47
1.605
1.745
1.490
1.595
1.680
1.490
1.595
1.680
1.490
1.595
1.680
VIH
2.135
2.420
2.135
2.420
2.135
2.420
2.135
2.420
VIL
1.490
1.825
1.490
1.825
1.490
1.825
1.490
1.825
VBB
Output Reference
Voltage1
1.92
2.04
1.92
2.04
1.92
2.04
1.92
2.04
VCC
3.0
3.8
3.0
3.8
3.0
3.8
3.0
3.8
IIH
150
150
150
150
IEE
55
55
55
65
mA
1. These values are for VCC = 3.3V. Level Specifications will vary 1:1 with VCC.
MC100LVE210
AC CHARACTERISTICS (VEE = VEE (min) to VEE (max); VCC = VCCO = GND)
40C
Symbol
Characteristic
Min
Typ
0C
Max
Min
675
700
475
400
Typ
25C
Max
Min
675
700
500
450
Typ
85C
Max
Min
700
750
500
450
Typ
Max
tPLH
tPHL
tskew
VPP
500
VCMR
1.5
0.4
1.5
0.4
1.5
0.4
1.5
0.4
tr/tf
200
600
200
600
200
600
200
600
Unit
Condition
ps
475
400
50
50
75
75
200
50
30
75
50
200
500
50
30
75
50
200
500
700
750
50
30
75
50
200
500
Note 1
Note 2
ps
Note 3
mV
Note 4
Note 5
ps
20%80%
1. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals. See Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 112).
2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. See
Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 112).
3. The withindevice skew is defined as the worst case difference between any two similar delay paths within a single device.
4. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited
for the LVE210 as a differential input as low as 50 mV will still produce full ECL levels at the output.
5. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level
must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to VPP(min).
49
MOTOROLA
MC100LVE210 MC100E210
MC100E210
ECL DC CHARACTERISTICS
40C
Symbol
0C
25C
85C
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
VOH
1.085
1.005
0.880
1.025
0.955
0.880
1.025
0.955
0.880
1.025
0.955
0.880
VOL
1.830
1.695
1.555
1.810
1.705
1.620
1.810
1.705
1.620
1.810
1.705
1.620
VIH
1.165
0.880
1.165
0.880
1.165
0.880
1.165
0.880
VIL
1.810
1.475
1.810
1.475
1.810
1.475
1.810
1.475
VBB
Output Reference
Voltage
1.38
1.26
1.38
1.26
1.38
1.26
1.38
1.26
VEE
5.25
4.2
5.25
4.2
5.25
4.2
5.25
4.2
IIH
150
150
150
150
IEE
55
55
55
65
mA
MC100E210
PECL DC CHARACTERISTICS
40C
Symbol
0C
25C
85C
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
VOH
3.915
3.995
4.12
3.975
4.045
4.12
3.975
4.045
4.12
3.975
4.045
4.12
VOL
3.170
3.305
3.445
3.19
3.295
3.38
3.19
3.295
3.38
3.19
3.295
3.38
VIH
3.835
4.12
3.835
4.12
3.835
4.12
3.835
4.12
VIL
3.190
3.525
3.190
3.525
3.190
3.525
3.190
3.525
VBB
Output Reference
Voltage1
3.62
3.74
3.62
3.74
3.62
3.74
3.62
3.74
VCC
4.75
5.25
4.75
5.25
4.75
5.25
4.75
5.25
IIH
150
150
150
150
IEE
55
55
55
65
mA
1. These values are for VCC = 5.0V. Level Specifications will vary 1:1 with VCC.
MC100E210
AC CHARACTERISTICS (VEE = VEE (min) to VEE (max); VCC = VCCO = GND)
40C
Symbol
Characteristic
Min
Typ
0C
Max
Min
675
700
475
400
Typ
25C
Max
Min
675
700
500
450
Typ
85C
Max
Min
700
750
500
450
Typ
Max
tPLH
tPHL
tskew
VPP
500
VCMR
1.5
0.4
1.5
0.4
1.5
0.4
1.5
0.4
tr/tf
200
600
200
600
200
600
200
600
Unit
Condition
ps
475
400
50
50
75
75
200
50
30
75
50
200
500
50
30
75
50
200
500
700
750
50
30
75
50
200
500
Note 1
Note 2
ps
Note 3
mV
Note 4
Note 5
ps
20%80%
1. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals. See Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 112).
2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. See
Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 112).
3. The withindevice skew is defined as the worst case difference between any two similar delay paths within a single device.
4. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited
for the E210 as a differential input as low as 50 mV will still produce full ECL levels at the output.
5. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level
must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to VPP(min).
MOTOROLA
410
MOTOROLA
Product Preview
Low Voltage 1:15 Differential
MC100LVE222
LOW VOLTAGE
1:15 DIFFERENTIAL
ECL/PECL CLOCK DRIVER
This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice.
2/95
411
REV 0
MC100LVE222
VCCO
Qc0
Qc0
Qc1
Qc1
Qc2
Qc2
Qc3
Qc3
VCCO
NC
NC
VCCO
39
38
37
36
35
34
33
32
31
30
29
28
27
VCCO
40
26
Qd0
Qb2
41
25
Qd0
Qb2
42
24
Qd1
Qb1
43
23
Qd1
Qb1
44
22
Qd2
Qb0
45
21
Qd2
Qb0
46
20
Qd3
VCCO
47
19
Qd3
Qa1
48
18
Qd4
Qa1
49
17
Qd4
Qa0
50
16
Qd5
Qa0
51
15
Qd5
VCCO
52
14
VCCO
CLK0
10
11
12
13
VEE
Fselb
Fseld
Fsela
Fselc
MR
VBB
CLK1
CLK1
CLK_Sel
CLK0
VCC
MC100LVE222
LOGIC SYMBOL
MR
CLK0
CLK0
CLK1
CLK1
Qa0:1
Qa0:1
Qb0:2
Qb0:2
Qc0:3
Qc0:3
Qd0:5
Qd0:5
CLK_Sel
VBB
fsela
fselb
fselc
fseld
MOTOROLA
412
MC100LVE222
ECL DC CHARACTERISTICS
40C
Symbol
Characteristic
0C
25C
85C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
VOH
1.085
1.005
0.880
1.025
0.955
0.880
1.025
0.955
0.880
1.025
0.955
0.880
VOL
1.830
1.695
1.555
1.810
1.705
1.620
1.810
1.705
1.620
1.810
1.705
1.620
VIH
1.165
0.880
1.165
0.880
1.165
0.880
1.165
0.880
VIL
1.810
1.475
1.810
1.475
1.810
1.475
1.810
1.475
VBB
Output Reference
Voltage
1.38
1.26
1.38
1.26
1.38
1.26
1.38
1.26
VEE
3.0
5.25
3.0
5.25
3.0
5.25
3.0
5.25
IIH
150
IEE
150
150
80
150
80
80
80
25C
85C
mA
PECL DC CHARACTERISTICS
40C
Symbol
Characteristic
0C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
VOH
2.215
2.295
2.420
2.275
2.345
2.420
2.275
2.345
2.420
2.275
2.345
2.420
VOL
1.470
1.605
1.745
1.490
1.595
1.680
1.490
1.595
1.680
1.490
1.595
1.680
VIH
2.135
2.420
2.135
2.420
2.135
2.420
2.135
2.420
VIL
1.490
1.825
1.490
1.825
1.490
1.825
1.490
1.825
VBB
1.92
2.04
1.92
2.04
1.92
2.04
1.92
2.04
VCC
3.0
5.25
3.0
5.25
3.0
5.25
3.0
5.25
IIH
150
IEE
150
150
80
150
80
80
80
mA
1. These values are for VCC = 3.3V. Level Specifications will vary 1:1 with VCC.
2. Special thermal handling required for VCC > 3.8V.
Characteristic
Min
Typ
0C
Max
Min
Typ
25C
Max
Min
Typ
85C
Max
Min
tPLH
tPHL
tskew
WithinDevice Skew
ParttoPart Skew (Diff)
VPP
500
VCMR
1.5
0.4
1.5
0.4
1.5
0.4
1.5
tr/tf
200
600
200
600
200
600
200
Typ
Max
Unit
Condition
ns
1.0
1.0
1.0
1.0
50
250
1.0
1.0
50
200
500
1.0
1.0
50
200
500
Note 1
Note 2
50
200
ps
Note 3
mV
Note 4
0.4
Note 5
600
ps
20%80%
500
1. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals. See Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 112).
2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. See
Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 112).
3. The withindevice skew is defined as the worst case difference between any two similar delay paths within a single device.
4. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited
for the LVE222 as a differential input as low as 50 mV will still produce full ECL levels at the output.
5. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level
must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to VPP(min).
413
MOTOROLA
MOTOROLA
MC100LVE310
Fanout Buffer
MC100E310
ECL/PECL Compatible
LOW VOLTAGE
2:8 DIFFERENTIAL
FANOUT BUFFER
7/95
414
REV 0.1
MC100LVE310 MC100E310
Q0
Q0
25
24
Q1 VCCO Q1
23
22
21
Q2
Q2
20
19
VEE
26
18
Q3
CLK_SEL
27
17
Q3
CLKa
28
16
Q4
15
VCCO
PIN NAMES
Pins
VCC
CLKa, CLKb
Q0:7
VBB
CLK_SEL
CLKa
14
Q4
VBB
13
Q5
CLK_SEL
CLKb
12
Q5
0
1
CLKb
NC
10
11
Q7 VCCO Q7
Q6
Q6
Function
Differential Input Pairs
Differential Outputs
VBB Output
Input Clock Select
Input Clock
CLKa Selected
CLKb Selected
LOGIC SYMBOL
Q0
Q0
Q1
Q1
Q2
Q2
CLKa
Q3
CLKa
Q3
CLKb
Q4
CLKb
Q4
Q5
CLK_SEL
Q5
Q6
Q6
Q7
Q7
VBB
415
MOTOROLA
MC100LVE310 MC100E310
MC100LVE310
ECL DC CHARACTERISTICS
40C
Symbol
0C
25C
85C
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
VOH
1.085
1.005
0.880
1.025
0.955
0.880
1.025
0.955
0.880
1.025
0.955
0.880
VOL
1.830
1.695
1.555
1.810
1.705
1.620
1.810
1.705
1.620
1.810
1.705
1.620
VIH
1.165
0.880
1.165
0.880
1.165
0.880
1.165
0.880
VIL
1.810
1.475
1.810
1.475
1.810
1.475
1.810
1.475
VBB
Output Reference
Voltage
1.38
1.26
1.38
1.26
1.38
1.26
1.38
1.26
VEE
3.0
3.8
3.0
3.8
3.0
3.8
3.0
3.8
IIH
150
IEE
70
mA
150
55
150
60
55
150
60
55
60
65
MC100LVE310
PECL DC CHARACTERISTICS
40C
Symbol
Characteristic
0C
25C
85C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
VOH
2.215
2.295
2.42
2.275
2.345
2.420
2.275
2.345
2.420
2.275
2.345
2.420
VOL
1.47
1.605
1.745
1.490
1.595
1.680
1.490
1.595
1.680
1.490
1.595
1.680
VIH
2.135
2.420
2.135
2.420
2.135
2.420
2.135
2.420
VIL
1.490
1.825
1.490
1.825
1.490
1.825
1.490
1.825
VBB
Output Reference
Voltage1
1.92
2.04
1.92
2.04
1.92
2.04
1.92
2.04
VCC
3.0
3.8
3.0
3.8
3.0
3.8
3.0
IIH
IEE
150
55
150
60
55
150
60
55
60
65
3.8
150
70
mA
1. These values are for VCC = 3.3V. Level Specifications will vary 1:1 with VCC.
MC100LVE310
AC CHARACTERISTICS (VEE = VEE (min) to VEE (max); VCC = VCCO = GND)
40C
Symbol
Typ
0C
Max
Min
725
750
550
525
Typ
25C
Max
Min
750
775
550
550
Typ
85C
Characteristic
Min
Max
Min
750
800
575
600
Typ
Max
tPLH
tPHL
525
500
tskew
WithinDevice Skew
ParttoPart Skew (Diff)
VPP
500
VCMR
1.5
0.4
1.5
0.4
1.5
0.4
1.5
0.4
tr/tf
200
600
200
600
200
600
200
600
Unit
Condition
ps
75
250
75
200
500
50
200
500
775
850
50
200
500
Note 1
Note 2
ps
Note 3
mV
Note 4
Note 5
ps
20%80%
1. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals. See Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 112).
2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. See
Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 112).
3. The withindevice skew is defined as the worst case difference between any two similar delay paths within a single device.
4. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited
for the LVE310 as a differential input as low as 50 mV will still produce full ECL levels at the output.
5. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level
must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to VPP(min).
MOTOROLA
416
MC100LVE310 MC100E310
MC100E310
ECL DC CHARACTERISTICS
40C
Symbol
0C
25C
85C
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
VOH
1.085
1.005
0.880
1.025
0.955
0.880
1.025
0.955
0.880
1.025
0.955
0.880
VOL
1.830
1.695
1.555
1.810
1.705
1.620
1.810
1.705
1.620
1.810
1.705
1.620
VIH
1.165
0.880
1.165
0.880
1.165
0.880
1.165
0.880
VIL
1.810
1.475
1.810
1.475
1.810
1.475
1.810
1.475
VBB
Output Reference
Voltage
1.38
1.26
1.38
1.26
1.38
1.26
1.38
1.26
VEE
5.25
4.2
5.25
4.2
5.25
4.2
5.25
4.2
IIH
150
IEE
70
mA
150
55
150
60
55
150
60
55
60
65
MC100E310
PECL DC CHARACTERISTICS
40C
Symbol
0C
25C
85C
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
VOH
3.915
3.995
4.12
3.975
4.045
4.12
3.975
4.045
4.12
3.975
4.045
4.12
VOL
3.170
3.305
3.445
3.19
3.295
3.38
3.19
3.295
3.38
3.19
3.295
3.38
VIH
3.835
4.12
3.835
4.12
3.835
4.12
3.835
4.12
VIL
3.190
3.525
3.190
3.525
3.190
3.525
3.190
3.525
VBB
Output Reference
Voltage1
3.62
3.74
3.62
3.74
3.62
3.74
3.62
3.74
VCC
4.75
5.25
4.75
5.25
4.75
5.25
4.75
5.25
IIH
150
IEE
70
mA
150
55
150
60
55
150
60
55
60
65
1. These values are for VCC = 5.0V. Level Specifications will vary 1:1 with VCC.
MC100E310
AC CHARACTERISTICS (VEE = VEE (min) to VEE (max); VCC = VCCO = GND)
40C
Symbol
Typ
0C
Max
Min
725
750
550
525
Typ
25C
Max
Min
750
775
550
550
Typ
85C
Characteristic
Min
Max
Min
750
800
575
600
Typ
Max
tPLH
tPHL
525
500
tskew
WithinDevice Skew
ParttoPart Skew (Diff)
VPP
500
VCMR
1.5
0.4
1.5
0.4
1.5
0.4
1.5
0.4
tr/tf
200
600
200
600
200
600
200
600
Unit
Condition
ps
75
250
75
200
500
50
200
500
775
850
50
200
500
Note 1
Note 2
ps
Note 3
mV
Note 4
note 5
ps
20%80%
1. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals. See Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 112).
2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. See
Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 112).
3. The withindevice skew is defined as the worst case difference between any two similar delay paths within a single device.
4. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited
for the E310 as a differential input as low as 50 mV will still produce full ECL levels at the output.
5. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level
must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to VPP(min).
417
MOTOROLA
MOTOROLA
Low Voltage
1:2 Differential Fanout Buffer
MC100LVEL11
8
1
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
Q0
VCC
Q0
Q1
Q1
VEE
PIN
FUNCTION
D
Q0, Q1
Data Inputs
Data Outputs
Characteristic
Min
IEE
VEE
IIH
IIL
3.0
0C
Typ
Max
24
28
3.3
3.8
Min
3.0
150
Dn
Dn
0.5
600
25C
Typ
Max
24
28
3.3
3.8
Min
3.0
Typ
Max
24
28
3.3
3.8
150
0.5
600
418
Min
3.0
150
0.5
600
1/96
85C
REV 0
0.5
600
Typ
Max
Unit
25
30
mA
3.3
3.8
150
A
A
MC100LVEL11
AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND)
40C
Symbol
Characteristic
Min
Typ
235
0C
Max
Min
385
245
Typ
25C
Max
Min
Typ
Max
Min
395
255
330
405
285
5
5
20
20
tPLH
tPHL
Propagation Delay to
Output
tSKEW
Within-Device Skew1
Duty Cycle Skew2
VPP
200
VCMR
2.1
1.9
0.2
0.2
2.2
2.0
0.2
0.2
2.2
2.0
tr
tf
120
320
120
320
120
5
5
20
20
5
5
85C
20
20
200
200
Typ
5
5
Max
Unit
435
ps
20
20
ps
200
mV
V
220
0.2
0.2
2.2
2.0
0.2
0.2
320
120
320
ps
800
VOUT(PP)(mV)
600
400
200
0
0
200
400
600
800
1000
1200
1400
1600
1800
2000
f (MHz)
419
MOTOROLA
MOTOROLA
MC100LVEL13
MC100EL13
20
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D04
Q1a
Q2a
Q2a
VCC
Q2b
Q2b
Q1b
Q1b
VEE
20
19
18
17
16
15
14
13
12
11
Q0a
Q0a
10
Q0b
Q0b
PIN NAMES
Pins
Function
Qna, Qna
Qnb, Qnb
CLKn, CLKn
MC100LVEL13
DC CHARACTERISTICS (VEE = 3.0V to 3.8V; VCC = GND)
40C
Symbol
Characteristic
IEE
IIH
IINL
Min
0C
Typ
Max
30
38
Min
150
Dn
Dn
0.5
300
25C
Typ
Max
30
38
Min
150
0.5
300
420
Max
30
38
Min
150
0.5
300
4/95
85C
Typ
REV 1
0.5
300
Typ
Max
Unit
32
40
mA
150
A
A
MC100LVEL13 MC100EL13
MC100LVEL13
AC CHARACTERISTICS (VEE = 3.0V to 3.8V; VCC = GND)
40C
Symbol
Characteristic
Min
Typ
0C
Max
Min
600
420
Typ
25C
Max
Min
610
430
Typ
85C
Max
Min
620
450
Typ
Max
tPLH
tPHL
Propagation Delay
CLKQ/Q
tsk(O)
OutputOutput Skew
Any QaQa, Any QbQb
Any QaAny Qb
tsk(DC)
150
1000
150
1000
150
1000
150
1000
VCMR
2.0
1.8
0.4
0.4
2.1
1.9
0.4
0.4
2.1
1.9
0.4
0.4
2.1
1.9
0.4
0.4
tr
tf
230
500
230
500
230
500
230
500
VPP
Unit
ps
410
640
ps
50
75
50
75
50
75
50
75
50
50
50
50
ps
mV
V
ps
1. Minimum input swing for which AC parameters guaranteed. The device has a DC gain of 40.
2. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between VPPmin and 1V. The lower end of the CMR range varies 1:1 with VEE. The
numbers in the spec table assume a nominal VEE = 3.3V. Note for PECL operation, the VCMR(min) will be fixed at 3.3V |VCMR(min)|.
MC100EL13
DC CHARACTERISTICS (VEE = 4.2V to 5.5V; VCC = GND)
40C
Symbol
Characteristic
IEE
IIH
IINL
Min
0C
Typ
Max
30
38
Min
Typ
Max
30
38
150
Dn
Dn
0.5
300
25C
Min
Typ
Max
30
38
150
0.5
300
85C
Min
Typ
Max
Unit
32
40
mA
150
150
0.5
300
0.5
300
MC100EL13
AC CHARACTERISTICS (VEE = 4.2V to 5.5V; VCC = GND)
40C
Symbol
Characteristic
Min
Typ
0C
Max
Min
600
420
Typ
25C
Max
Min
610
430
Typ
85C
Max
Min
620
450
Typ
Max
tPLH
tPHL
Propagation Delay
CLKQ/Q
tsk(O)
OutputOutput Skew
Any QaQa, Any QbQb
Any QaAny Qb
tsk(DC)
150
1000
150
1000
150
1000
150
1000
VCMR
3.2
3.0
0.4
0.4
3.3
3.1
0.4
0.4
3.3
3.1
0.4
0.4
3.3
3.1
0.4
0.4
tr
tf
230
500
230
500
230
500
230
500
VPP
Unit
ps
410
640
ps
50
75
50
75
50
75
50
75
50
50
50
50
ps
mV
V
ps
1. Minimum input swing for which AC parameters guaranteed. The device has a DC gain of 40.
2. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between VPPmin and 1V. The lower end of the CMR range varies 1:1 with VEE. The
numbers in the spec table assume a nominal VEE = 4.5V. Note for PECL operation, the VCMR(min) will be fixed at 5.0V |VCMR(min)|.
421
MOTOROLA
MOTOROLA
MC100LVEL14
MC100EL14
EN
VCC
NC
20
19
18
17
SCLK CLK
16
15
1
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D-04
PIN DESCRIPTION
VCC
20
CLK
VBB
SEL
VEE
14
13
12
11
D
Q
PIN
FUNCTION
CLK
SCLK
EN
SEL
VBB
Q04
FUNCTION TABLE
CLK
SCLK
SEL
EN
L
H
X
X
X
X
X
L
H
X
L
L
H
H
X
L
L
L
L
H
L
H
L
H
L*
10
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
7/95
422
REV 1
MC100LVEL14 MC100EL14
ABSOLUTE MAXIMUM RATINGS1
Symbol
Characteristic
Rating
Unit
VEE
8.0 to 0
VDC
VI
0 to 6.0
VDC
Iout
Output Current
50
100
mA
TA
40 to +85
Continuous
Surge
VEE
Operating Range1,2
5.7 to 4.2
1. Absolute maximum rating, beyond which, device life may be impaired, unless otherwise specified on an individual data sheet.
2. Parametric values specified at: 100EL Series: 4.20V to 5.50V
10EL Series:
4.94V to 5.50V
Characteristic
0C to 85C
Min
Typ
Max
Min
Typ
Max
Unit
Condition
VOH
1085
1005
880
1025
955
880
mV
VIN = VIH(max)
VOL
1830
1695
1555
1810
1705
1620
mV
or VIL(min)
VOHA
1095
1035
mV
VIN = VIH(max)
VOLA
1555
1610
mV
or VIL(min)
VIH
1165
880
1165
880
mV
VIL
1810
1475
1810
1475
mV
IIL
300
0.5
300
0.5
CLK
Others
VIN = VIL(max)
1. This table replaces the three tables traditionally seen in ECL 100K data books. The same DC parameter values at VEE = 4.5V now apply across
the full VEE range of 3.0V to 5.5V. Outputs are terminated through a 50 resistor to 2.0V except where otherwise specified on the individual
data sheets.
423
MOTOROLA
MC100LVEL14 MC100EL14
MC100LVEL14 AC/DC CHARACTERISTICS (VEE = 3.8V to 3.0V; VCC = GND)
40C
Symbol
IEE
Characteristic
Min
0C
Typ
Max
32
32
40
40
Min
25C
Typ
Max
32
32
40
40
Min
85C
Typ
Max
32
32
40
40
Min
Typ
Max
34
34
42
42
Unit
mA
VBB
Output Ref
Voltage
IIH
tPLH
tPHL
Prop
Delay
tSKEW
Part-to-Part Skew
Within-Device Skew1
tS
Setup Time EN
ps
tH
Hold Time EN
ps
VPP
150
150
150
150
mV
VCMR
2.0
1.8
0.4
0.4
2.1
1.9
0.4
0.4
2.1
1.9
0.4
0.4
2.1
1.9
0.4
0.4
tr
tf
230
500
230
500
230
500
230
500
CLK to Q (Diff)
CLK to Q (SE)
SCLK to Q
1.43
1.38
1.30
1.26
1.38
1.38
1.27
1.26
150
520
470
470
720
770
770
1.35
1.38
1.25 1.31
1.26 1.38
150
550
500
500
750
800
800
200
50
150
580
530
530
680
680
680
200
50
780
830
830
630
580
580
200
50
1.19
1.26
150
830
880
880
ps
200
50
ps
ps
Characteristic
Min
0C
Typ
Max
32
32
40
40
Min
25C
Typ
Max
32
32
40
40
Min
85C
Typ
Max
32
32
40
40
Min
Typ
Max
34
34
42
42
Unit
mA
VBB
Output Ref
Voltage
IIH
tPLH
tPHL
Prop
Delay
tSKEW
Part-to-Part Skew
Within-Device Skew1
tS
Setup Time EN
ps
tH
Hold Time EN
ps
VPP
150
150
150
150
mV
VCMR
3.2
3.0
0.4
0.4
3.3
3.1
0.4
0.4
3.3
3.1
0.4
0.4
3.3
3.1
0.4
0.4
tr
tf
230
500
230
500
230
500
230
500
CLK to Q (Diff)
CLK to Q (SE)
SCLK to Q
1.43
1.38
1.30
1.26
1.38
1.38
1.27
1.26
150
520
470
470
720
770
770
1.35
1.38
1.25 1.31
1.26 1.38
150
550
500
500
750
800
800
200
50
150
580
530
530
200
50
680
680
680
780
830
830
630
580
580
200
50
1.19
1.26
150
830
880
880
ps
200
50
ps
ps
MOTOROLA
424
MOTOROLA
Differential Receiver
MC100LVEL16
8
1
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
NC 1
VCC
VBB
PIN DESCRIPTION
PIN
FUNCTION
D
Q
VBB
Data Inputs
Data Outputs
Ref. Voltage Output
VEE
5/96
425
REV 0
MC100LVEL16
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND)
40C
Symbol
Characteristic
Min
IEE
VBB
1.38
VEE
3.0
IIH
IIL
0C
Typ
Max
17
23
3.3
Min
1.26
1.38
3.8
3.0
25C
Typ
Max
17
23
3.3
1.26
1.38
3.8
3.0
150
CLK
CLK
0.5
600
Min
Typ
Max
17
23
3.3
150
0.5
600
85C
Min
1.26
1.38
3.8
3.0
Typ
Max
Unit
18
24
mA
1.26
3.8
150
3.3
150
0.5
600
0.5
600
0C
25C
85C
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
tPLH
tPHL
Propagation Delay
to Output
(Diff)
(SE)
150
100
275
275
400
450
215
165
290
290
365
415
225
175
300
300
375
425
240
190
315
315
390
440
tSKEW
30
20
20
20
VPP
150
VCMR
2.0
1.8
Unit
ps
150
150
150
ps
mV
V
0.4
0.4
2.1
1.9
0.4
0.4
2.1
1.9
0.4
0.4
2.1
1.9
0.4
0.4
tr
Output Rise/Fall Times Q
120
220
320
120
220
320
120
220
320
120
220
320
ps
tf
(20% 80%)
1. Duty cycle skew is the difference between a TPLH and TPHL propagation delay through a device.
2. Minimum input swing for which AC parameters guaranteed. The device has a DC gain of 40.
3. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between VPPmin and 1V. The lower end of the CMR range varies 1:1 with VEE. The
numbers in the spec table assume a nominal VEE = 3.3V. Note for PECL operation, the VCMR(min) will be fixed at 3.3V |VCMR(min)|.
MOTOROLA
426
MOTOROLA
LowVoltage Quad
Differential Receiver
MC100LVEL17
MC100EL17
20
1
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D-04
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
VEE
20
19
18
17
16
15
14
13
12
11
PIN NAMES
10
VCC
D0
D0
D1
D1
D2
D2
D3
D3
VBB
Pins
Function
Dn
Qn
VBB
Data Inputs
Data Outputs
Reference Voltage Output
MC100LVEL17
DC CHARACTERISTICS (VEE = 3.0V to 3.8V; VCC = GND) Note 1
40C
Symbol
Characteristic
Min
IEE
VBB
IIH
IINL
0C
Typ
Max
26
31
1.38
1.26
Min
1.38
150
Dn
Dn
0.5
300
25C
Typ
Max
26
31
1.26
Min
Typ
Max
26
31
1.38
150
0.5
300
0.5
300
4/95
427
1.26
Min
1.38
150
85C
REV 2
0.5
300
Typ
Max
Unit
27
33
mA
1.26
150
A
A
MC100LVEL17 MC100EL17
MC100LVEL17
AC CHARACTERISTICS (VEE = 3.0V to 3.8V; VCC = GND)
40C
Symbol
Characteristic
Min
330
280
Max
Min
530
580
340
290
Typ
25C
Max
Min
540
590
350
300
Typ
85C
Max
Min
550
600
360
310
Typ
Max
Unit
560
610
ps
75
200
25
ps
tPLH
tPHL
Propagation Delay
D to Q
tSKEW
Skew OutputtoOutput1
ParttoPart (Diff)1
Duty Cycle (Diff)2
VPP
150
VCMR
2.0
1.8
0.4
0.4
2.1
1.9
0.4
0.4
2.1
1.9
0.4
0.4
2.1
1.9
0.4
0.4
tr
tf
280
550
280
550
280
550
280
550
1.
2.
3.
4.
Diff
S.E.
Typ
0C
75
200
25
75
200
25
150
75
200
25
150
150
mV
V
ps
Skews are valid across specified voltage range, parttopart skew is for a given temperature.
Duty cycle skew is the difference between a TPLH and TPHL propagation delay through a device.
Minimum input swing for which AC parameters guaranteed. The device has a DC gain of 40.
The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between VPPmin and 1V. The lower end of the CMR range varies 1:1 with VEE. The
numbers in the spec table assume a nominal VEE = 3.3V. Note for PECL operation, the VCMR(min) will be fixed at 3.3V |VCMR(min)|.
MC100EL17
DC CHARACTERISTICS (VEE = 4.2V to 5.5V; VCC = GND) Note 1
40C
Symbol
Characteristic
Min
IEE
VBB
IIH
IINL
0C
Typ
Max
26
31
1.38
1.26
Min
Typ
Max
26
31
1.38
1.26
150
Dn
Dn
0.5
300
25C
Min
Typ
Max
26
31
1.38
1.26
150
0.5
300
85C
Min
Typ
Max
Unit
27
33
mA
1.26
150
1.38
150
0.5
300
0.5
300
MC100EL17
AC CHARACTERISTICS (VEE = 4.20V to 5.5V; VCC = GND)
40C
Symbol
Characteristic
Min
330
280
Max
Min
530
580
340
290
Typ
25C
Max
Min
540
590
350
300
Typ
85C
Max
Min
550
600
360
310
Typ
Max
Unit
560
610
ps
75
200
25
ps
tPLH
tPHL
Propagation Delay
D to Q
tSKEW
Skew OutputtoOutput1
ParttoPart (Diff)1
Duty Cycle (Diff)2
VPP
150
VCMR
3.2
3.0
0.4
0.4
3.3
3.1
0.4
0.4
3.3
3.1
0.4
0.4
3.3
3.1
0.4
0.4
tr
tf
280
550
280
550
280
550
280
550
1.
2.
3.
4.
Diff
S.E.
Typ
0C
75
200
25
75
200
25
150
75
200
25
150
150
mV
V
ps
Skews are valid across specified voltage range, parttopart skew is for a given temperature.
Duty cycle skew is the difference between a TPLH and TPHL propagation delay through a device.
Minimum input swing for which AC parameters guaranteed. The device has a DC gain of 40.
The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between VPPmin and 1V. The lower end of the CMR range varies 1:1 with VEE. The
numbers in the spec table assume a nominal VEE = 4.5V. Note for PECL operation, the VCMR(min) will be fixed at 5.0V |VCMR(min)|.
MOTOROLA
428
MOTOROLA
MC100LVEL29
MC100EL29
20
1
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D04
VCC
Q0
Q0
S0
S1
VCC
Q1
Q1
VEE
20
19
18
17
16
15
14
13
12
11
S
D
CLK
CLK
CLK
L
L
H
L
H
L
L
L
H
H
L
H
X
X
X
Z
Z
X
X
X
L
H
L
H
Undef
H
L
H
L
Undef
D0
D0
D1
D1 CLK1
10
CLK1 R1
Pins
Function
D0D1
R0R1
CLK0CLK1
S0S1
Data Inputs
Reset Inputs
Clock Inputs
Set Inputs
MC100LVEL29
DC CHARACTERISTICS (VEE = 3.0V to 3.8V; VCC = GND)
40C
Symbol
Characteristic
IEE
VBB
IIH
IIL
Min
1.38
0C
Typ
Max
35
50
1.26
Min
1.38
150
Dn Inputs
Dn Inputs
0.5
300
25C
Typ
Max
35
50
1.26
Min
1.38
150
0.5
300
429
Typ
Max
35
50
1.26
Min
1.38
150
0.5
300
7/95
85C
REV 1
0.5
300
Typ
Max
Unit
35
50
mA
1.26
150
A
A
MC100LVEL29 MC100EL29
MC100LVEL29
AC CHARACTERISTICS (VEE = 3.0V to 3.8V; VCC = GND)
40C
Symbol
Characteristic
Min
Typ
0C
Max
Min
1.1
25C
Typ
Max
Typ
Max
Typ
Max
tPLH
tPHL
Propagation Delay
to Output
tS
tH
Setup Time
Hold Time
0
100
0
100
0
100
0
100
ps
tRR
Set/Reset Recovery
100
100
100
100
ps
tPW
400
400
400
400
ps
VPP
150
150
150
150
mV
VCMR1
Common VPP<500mV
Mode RangeVPP500mV
2.0
1.8
680
700
490
490
0.4
0.4
690
710
2.1
1.9
0.4
0.4
1.1
Unit
Maximum Toggle
Frequency
480
480
1.1
Min
fMAX
CLK
S, R
1.1
Min
85C
500
500
700
720
2.1
1.9
0.4
0.4
GHz
520
520
720
740
2.1
1.9
0.4
0.4
ps
tr
Output Rise/Fall Times Q
280
550
280
550
280
550
280
550
ps
tf
(20% 80%)
1. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between VPPmin and 1V. The lower end of the CMR range varies 1:1 with VEE. The
numbers in the spec table assume a nominal VEE = 3.3V. Note for PECL operation, the VCMR(min) will be fixed at 3.3V |VCMR(min)|.
MC100EL29
DC CHARACTERISTICS (VEE = 4.2V to 5.5V; VCC = GND)
40C
Symbol
Characteristic
IEE
VBB
IIH
IIL
Min
1.38
0C
Typ
Max
35
50
1.26
Min
Typ
Max
35
50
1.38
150
Dn Inputs
Dn Inputs
25C
1.26
Min
Typ
Max
35
50
1.38
1.26
150
0.5
300
0.5
300
85C
Min
Typ
Max
Unit
35
50
mA
1.26
150
1.38
150
0.5
300
0.5
300
MC100EL29
AC CHARACTERISTICS (VEE = 4.2V to 5.5V; VCC = GND)
40C
Symbol
Characteristic
Min
Typ
0C
Max
1.1
Min
Typ
25C
Max
Typ
Max
Typ
Max
tPLH
tPHL
Propagation Delay
to Output
tS
tH
Setup Time
Hold Time
0
100
0
100
0
100
0
100
ps
tRR
Set/Reset Recovery
100
100
100
100
ps
tPW
400
400
400
400
ps
VPP
150
150
150
150
mV
VCMR1
Common VPP<500mV
Mode RangeVPP500mV
3.2
3.0
680
700
0.4
0.4
490
490
690
710
3.3
3.1
0.4
0.4
500
500
3.3
3.1
1.1
Unit
Maximum Toggle
Frequency
480
480
1.1
Min
fMAX
CLK
S, R
1.1
Min
85C
700
720
0.4
0.4
520
520
3.3
3.1
GHz
720
740
0.4
0.4
ps
tr
Output Rise/Fall Times Q
280
550
280
550
280
550
280
550
ps
tf
(20% 80%)
1. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between VPPmin and 1V. The lower end of the CMR range varies 1:1 with VEE. The
numbers in the spec table assume a nominal VEE = 4.5V. Note for PECL operation, the VCMR(min) will be fixed at 5.0V |VCMR(min)|.
MOTOROLA
430
MOTOROLA
Triple D Flip-Flop
With Set and Reset
MC100LVEL30
MC100EL30
20
1
Q0
Q0
VCC
Q1
Q1
VCC
Q2
Q2
VEE
20
19
18
17
16
15
14
13
12
11
TRUTH TABLE
R
CLK
L
L
H
L
H
L
L
L
H
H
L
H
X
X
X
Z
Z
X
X
X
L
H
L
H
Undef
H
L
H
L
Undef
S012
D0
CLK0
R0
D1
CLK1
R1
D2
10
CLK2 R2
Pins
Function
D0D2
R0R2
CLK0CLK2
S012
Data Inputs
Reset Inputs
Clock Inputs
Common Set Input
5/96
431
REV 2
MC100LVEL30 MC100EL30
MC100LVEL30
DC CHARACTERISTICS (VEE = 3.0V to 3.8V; VCC = GND)
40C
Symbol
Characteristic
Min
IEE
IIH
0C
Typ
Max
55
62
Min
25C
Typ
Max
55
62
150
Min
85C
Typ
Max
55
62
150
Min
Typ
Max
Unit
55
64
mA
150
Max
Unit
150
MC100LVEL30
AC CHARACTERISTICS (VEE = 3.0V to 3.8V; VCC = GND)
40C
Symbol
Characteristic
Min
Typ
0C
Max
1.0
Min
Typ
25C
Max
Typ
Max
Typ
Maximum Toggle
Frequency
tPLH
tPHL
Propagation Delay
to Output
tS
tH
Setup Time
Hold Time
150
200
0
100
150
200
0
100
150
200
0
100
150
200
0
100
ps
tRR
Set/Reset Recovery
400
200
400
200
400
200
400
200
ps
tPW
400
650
tr
tf
460
470
690
710
1.2
Min
fMAX
CLK
S, R
1.2
Min
85C
470
480
700
720
1.2
480
490
710
730
GHz
500
515
730
755
ps
ps
400
650
280
550
400
650
280
550
400
650
280
550
280
550
ps
Typ
Max
Unit
55
64
mA
150
Max
Unit
MC100EL30
DC CHARACTERISTICS (VEE = 4.2V to 5.5V; VCC = GND)
40C
Symbol
Characteristic
Min
IEE
IIH
0C
Typ
Max
55
62
Min
25C
Typ
Max
55
62
150
Min
85C
Typ
Max
55
62
150
Min
150
MC100EL30
AC CHARACTERISTICS (VEE = 4.2V to 5.5V; VCC = GND)
40C
Symbol
Characteristic
Min
Typ
0C
Max
Typ
Max
Typ
Max
Typ
tPLH
tPHL
Propagation Delay
to Output
tS
tH
Setup Time
Hold Time
150
200
0
100
150
200
0
100
150
200
0
100
150
200
0
100
ps
tRR
Set/Reset Recovery
400
200
400
200
400
200
400
200
ps
tPW
400
650
tr
tf
460
470
690
710
1.2
Min
Maximum Toggle
Frequency
CLK
S, R
1.2
Min
85C
fMAX
MOTOROLA
1.0
Min
25C
470
480
700
720
1.2
480
490
710
730
GHz
500
515
730
755
ps
ps
280
400
650
550
400
650
280
550
432
280
400
650
550
280
550
ps
MOTOROLA
Product Preview
2
MC100LVEL32
Divider
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
Reset
CLK
VCC
PIN DESCRIPTION
CLK
VBB
VEE
PIN
FUNCTION
CLK
Reset
VBB
Q
Clock Inputs
Asynch Reset
Ref Voltage Output
Data Ouputs
This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice.
5/96
433
REV 0
MC100LVEL32
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND)
40C
Symbol
Characteristic
Min
Typ
IEE
25
VEE
3.0
VBB
IIH
1.38
0C
Max
Min
Typ
25C
Max
Min
25
3.0
1.26
3.3
1.38
150
Typ
85C
Max
Min
25
3.8
3.0
1.26
1.38
3.3
Typ
3.8
3.0
3.3
1.26 1.38
150
Max
25
150
Unit
mA
3.8
1.26
150
Max
Unit
Characteristic
fMAX
Maximum Toggle
Frequency
tPLH
tPHL
Propagation Delay
CLK to Q
Reset to Q
VPP
Min
150
Typ
0C
Max
Min
Typ
25C
Max
Min
Typ
85C
Max
Min
Typ
3.0
3.0
3.0
3.0
GHz
500
540
500
540
510
540
540
550
ps
150
tr
Output Rise/Fall Times Q
225
tf
(20% 80%)
1. Minimum input swing for which AC parameters are guaranteed.
150
225
150
225
mV
225
ps
CLK
RESET
MOTOROLA
434
MOTOROLA
2, 4/6
MC100LVEL38
MC100EL38
20
1
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D-04
PIN DESCRIPTION
PIN
FUNCTION
CLK
EN
MR
VBB
Q0, Q1
Q2, Q3
DIVSEL
Phase_Out
FUNCTION TABLE
CLK
EN
MR
Z
ZZ
X
L
H
X
L
L
H
FUNCTION
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
VEE
20
19
18
17
16
15
14
13
12
11
Z = Low-to-High Transition
ZZ = High-to-Low Transition
EN DIV_SEL CLK
10
CLK
VBB
MR
VCC
Phase_Out
VCC
Phase_Out
DIVSEL
0
1
10/94
435
Divide
Hold Q03
Reset Q03
REV 1
Q2, Q3 OUTPUTS
Divide by 4
Divide by 6
MC100LVEL38 MC100EL38
LOGIC DIAGRAM
Q0
CLK
CLK
Q0
Q1
Q1
EN
Q2
R
4/6
R
MR
Q2
Q3
Q3
DIVSEL
Phase
Out
R Logic
PHASE_OUT
PHASE_OUT
CLK
Q (2)
Q (4)
Q (6)
Phase_Out (4)
Phase_Out (6)
MOTOROLA
436
MC100LVEL38 MC100EL38
MC100LVEL38
DC CHARACTERISTICS (VEE = 3.8V to 3.0; VCC = GND)
40C
Symbol
Characteristic
IEE
VBB
IIH
Min
0C
Typ
Max
50
60
1.38
1.26
Min
25C
Typ
Max
50
60
1.38
1.26
150
Min
85C
Typ
Max
50
60
1.38
1.26
150
Min
Typ
Max
Unit
54
65
mA
1.38
150
1.26
150
Max
Unit
MC100LVEL38
AC CHARACTERISTICS (VEE = 3.8V to 3.0; VCC = GND)
40C
Symbol
Characteristic
Min
fMAX
1000
tPLH
tPHL
Propagation Delay
CLK Q (Diff)
to Output
CLK Q (S.E.)
CLK Phase_Out (Diff)
CLK Phase_Out (S.E.)
MR Q
760
710
800
750
510
tSKEW
Within-Device Skew1
Typ
0C
Max
Min
Typ
25C
Max
1000
960
1010
1000
1050
810
Min
Typ
85C
Max
1000
780
730
820
770
530
980
1030
1020
1070
830
Min
Typ
1000
800
750
840
790
540
1000
1050
1040
1090
840
MHz
850
800
890
840
570
1050
1100
1090
1140
870
ps
ps
Q0 Q3
All
50
75
50
75
50
75
50
75
Part-to-Part
Q0 Q3 (Diff)
All
200
240
200
240
200
240
200
240
tS
Setup Time
EN CLK
DIVSEL CLK
150
150
150
150
ps
tH
Hold Time
CLK EN
CLK Div_Sel
150
200
150
200
150
200
150
200
ps
VPP2
CLK
250
VCMR3
tRR
tPW
CLK
MR
800
700
tr, tf
280
CLK
0.55
250
See3
0.55
100
250
See3
800
700
550
0.55
100
280
250
See3
800
700
550
0.55
100
280
mV
See3
100
ps
800
700
550
280
ps
550
ps
437
MOTOROLA
MC100LVEL38 MC100EL38
MC100EL38
DC CHARACTERISTICS (VEE = 4.2V to 5.46; VCC = GND)
40C
Symbol
Characteristic
IEE
VBB
IIH
Min
0C
Typ
Max
50
60
1.38
1.26
Min
25C
Typ
Max
50
60
1.38
1.26
150
Min
85C
Typ
Max
50
60
1.38
1.26
150
Min
Typ
Max
Unit
54
65
mA
1.38
150
1.26
150
Max
Unit
MC100EL38
AC CHARACTERISTICS (VEE = 4.2V to 5.46; VCC = GND)
40C
Symbol
Characteristic
Min
fMAX
1000
tPLH
tPHL
Propagation Delay
CLK Q (Diff)
to Output
CLK Q (S.E.)
CLK Phase_Out (Diff)
CLK Phase_Out (S.E.)
MR Q
760
710
800
750
510
tSKEW
Within-Device Skew1
Typ
0C
Max
Min
Typ
25C
Max
1000
960
1010
1000
1050
810
Min
Typ
85C
Max
1000
780
730
820
770
530
980
1030
1020
1070
830
Min
Typ
1000
800
750
840
790
540
1000
1050
1040
1090
840
MHz
850
800
890
840
570
1050
1100
1090
1140
870
ps
ps
Q0 Q3
All
50
75
50
75
50
75
50
75
Part-to-Part
Q0 Q3 (Diff)
All
200
240
200
240
200
240
200
240
tS
Setup Time
EN CLK
DIVSEL CLK
150
150
150
150
ps
tH
Hold Time
CLK EN
CLK Div_Sel
150
200
150
200
150
200
150
200
ps
VPP2
CLK
250
VCMR3
tRR
tPW
CLK
MR
800
700
tr, tf
280
CLK
0.55
250
See3
0.55
100
250
See3
800
700
550
0.55
100
280
250
See3
800
700
550
0.55
100
280
mV
See3
100
ps
800
700
550
280
ps
550
ps
MOTOROLA
438
MOTOROLA
2/4, 4/6
Clock
MC100LVEL39
Generation Chip
MC100EL39
20
1
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D-04
PIN DESCRIPTION
PIN
FUNCTION
CLK
EN
MR
VBB
Q0, Q1
Q2, Q3
DIVSEL
FUNCTION TABLE
CLK
EN
MR
Z
ZZ
X
L
H
X
L
L
H
FUNCTION
Synchronous Enable/Disable
Master Reset for Synchronization
75k Internal Input Pulldown Resistors
>2000V ESD Protection
Z = Low-to-High Transition
ZZ = High-to-Low Transition
DIVSELa
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
VEE
20
19
18
17
16
15
14
13
12
11
0
1
DIVSELb
0
1
1
VCC
EN DIVSELb CLK
CLK
VBB
MR
VCC
10
NC DIVSELa
3/96
439
Divide
Hold Q03
Reset Q03
REV 2
Q0, Q1 OUTPUTS
Divide by 2
Divide by 4
Q2, Q3 OUTPUTS
Divide by 4
Divide by 6
MC100LVEL39 MC100EL39
LOGIC DIAGRAM
DIVSELa
Q0
CLK
2/4
CLK
Q0
Q1
Q1
Q2
EN
4/6
Q2
Q3
MR
Q3
DIVSELb
CLK
Q (2)
Q (4)
Q (6)
MC100LVEL39
DC CHARACTERISTICS (VEE = 3.8V to 3.0; VCC = GND)
40C
Symbol
Characteristic
IEE
VBB
IIH
Min
0C
Typ
Max
50
59
1.38
1.26
Min
25C
Typ
Max
50
59
1.38
1.26
150
Min
85C
Typ
Max
50
59
1.38
1.26
150
Min
Typ
Max
Unit
54
61
mA
1.38
150
1.26
150
Max
Unit
MC100LVEL39
AC CHARACTERISTICS (VEE = 3.8V to 3.0; VCC = GND)
40C
Symbol
Characteristic
fMAX
tPLH
tPHL
Propagation Delay
to Output
tSKEW
Within-Device Skew1
Min
Typ
0C
Max
1000
CLK Q (Diff)
CLK Q (S.E.)
MR Q
760
710
600
Min
Typ
25C
Max
1000
960
1010
900
780
730
600
Min
Typ
85C
Max
1000
980
1030
900
800
750
610
Min
Typ
1000
1000
1050
910
850
800
630
MHz
1050
1100
930
ps
ps
Q0 Q3
50
50
50
50
Part-to-Part
Q0 Q3 (Diff)
200
200
200
200
tS
Setup Time
EN CLK
DIVSEL CLK
250
400
250
400
250
400
250
400
ps
tH
Hold Time
CLK EN
CLK Div_Sel
100
150
100
150
100
150
100
150
ps
MOTOROLA
440
MC100LVEL39 MC100EL39
MC100LVEL39 (continued)
AC CHARACTERISTICS (VEE = 3.8V to 3.0; VCC = GND)
40C
Symbol
Characteristic
Min
VPP
CLK
250
VCMR
2.0
1.8
Typ
0C
Max
Min
Typ
25C
Max
250
Min
Typ
85C
Max
250
Min
Typ
Max
250
Unit
mV
V
tRR
tPW
CLK
MR
500
700
tr, tf
280
0.4
0.4
2.1
1.9
0.4
0.4
100
0.4
0.4
100
500
700
550
2.1
1.9
550
0.4
0.4
100
500
700
280
2.1
1.9
100
500
700
280
550
ps
ps
280
550
ps
MC100EL39
DC CHARACTERISTICS (VEE = 4.2V to 5.46; VCC = GND)
40C
Symbol
Characteristic
IEE
VBB
IIH
Min
Typ
0C
Max
50
1.38
Min
59
Typ
50
1.26
1.38
25C
Max
59
1.26
150
Min
Typ
50
1.38
85C
Max
59
1.26
150
Min
Typ
54
1.38
150
Max
Unit
61
mA
1.26
150
Max
Unit
MC100EL39
AC CHARACTERISTICS (VEE = 4.2V to 5.46; VCC = GND)
40C
Symbol
Characteristic
fMAX
tPLH
tPHL
Propagation Delay
to Output
tSKEW
Within-Device Skew1
Min
Typ
0C
Max
1000
CLK Q (Diff)
CLK Q (S.E.)
MR Q
760
710
600
Min
Typ
25C
Max
1000
960
1010
900
780
730
600
Min
Typ
85C
Max
1000
980
1030
900
800
750
610
Min
Typ
1000
1000
1050
910
850
800
630
MHz
1050
1100
930
ps
ps
Q0 Q3
50
50
50
50
Part-to-Part
Q0 Q3 (Diff)
200
200
200
200
tS
Setup Time
EN CLK
DIVSEL CLK
250
400
250
400
250
400
250
400
ps
tH
Hold Time
CLK EN
CLK Div_Sel
100
150
100
150
100
150
100
150
ps
VPP
CLK
250
250
250
250
mV
VCMR
3.2
3.0
tRR
tPW
CLK
MR
500
700
tr, tf
280
V
0.4
0.4
3.3
3.1
100
0.4
0.4
100
500
700
550
3.3
3.1
280
0.4
0.4
100
500
700
550
3.3
3.1
280
0.4
0.4
100
500
700
550
280
ps
ps
550
ps
441
MOTOROLA
MOTOROLA
Product Preview
MC100LVEL51
8
1
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
R 1
VCC
TRUTH TABLE
R
D
Flip-Flop
CLK
CLK
CLK
VEE
This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice.
5/96
442
REV 0
MC100LVEL51
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND)
40C
Symbol
Characteristic
Min
IEE
VEE
IIH
Typ
0C
Max
Min
24
3.0
3.3
Typ
25C
Max
Min
24
3.8
3.0
3.3
150
Typ
85C
Max
Min
24
3.8
3.0
3.3
150
Typ
Max
24
3.8
3.0
3.3
150
Unit
mA
3.8
150
Max
Unit
Characteristic
fMAX
Maximum Toggle
Frequency
tPLH
tPHL
Propagation Delay
to Output
tS
Min
Typ
0C
Max
Min
Typ
25C
Max
Min
Typ
85C
Max
Min
Typ
2.8
2.8
2.8
2.8
465
455
465
455
475
465
530
510
Setup Time
ps
tH
Hold Time
100
100
100
100
ps
tRR
Reset Recovery
200
200
200
200
ps
tPW
400
400
400
400
ps
VPP
150
150
150
150
mV
VCMR
ps
CLK
R
tr
Output Rise/Fall Times Q
225
tf
(20% 80%)
1. Minimum input swing for which AC parameters are guaranteed.
GHz
V
225
443
225
225
ps
MOTOROLA
MOTOROLA
Dual Differential
2:1 Multiplexer
MC100LVEL56
MC100EL56
20
1
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D04
SEL
Data
H
L
a
b
VCC
Q0
Q0
SEL0
COM_SEL
20
19
18
17
16
SEL1 VCC
15
D0a
D0a
VBB0
D0b
D0b
D1a
Q1
Q1
VEE
14
13
12
11
D1a VBB1
10
D1b
D1b
PIN NAMES
Pins
Function
D0aD1a
D0bD1b
SEL0SEL1
COM_SEL
Q0Q1
Q0Q1
Input Data a
Input Data b
Individual Select Input
Common Select Input
True Outputs
Inverted Outputs
4/95
444
REV 1
MC100LVEL56 MC100EL56
MC100LVEL56
DC CHARACTERISTICS (VEE = 3.0V to 3.8V; VCC = GND)
40C
Symbol
Characteristic
Min
IEE
VBB
IIH
IINL
0C
Typ
Max
20
24
1.26
Min
Typ
Max
20
24
1.38
1.26
150
Dn
Dn
0.5
600
25C
Min
Typ
Max
20
24
1.38
1.26
150
0.5
600
85C
Min
Typ
Max
Unit
20
24
mA
1.26
150
1.38
150
0.5
600
0.5
600
50
50
MC100LVEL56
AC CHARACTERISTICS (VEE = 3.0V to 3.8V; VCC = GND)
40C
Symbol
Characteristic
D (Diff)
D (SE)
SEL
COMSEL
Min
Typ
340
290
430
430
0C
Max
Min
540
590
730
730
350
300
440
440
Typ
25C
Max
Min
550
600
740
740
360
310
440
440
Typ
85C
Max
Min
560
610
740
740
380
330
450
450
tPLH
tPHL
Propagation
Delay
to Output
tSKEW
WithinDevice Skew1
tSKEW
VPP(AC)
150
1000
150
1000
150
1000
VCMR
2.0
1.8
0.4
0.4
2.1
1.9
0.4
0.4
2.1
1.9
0.4
0.4
40
80
40
100
80
40
100
80
Typ
40
Max
Unit
580
630
750
750
ps
80
ps
100
ps
150
1000
mV
2.1
1.9
0.4
0.4
100
tr
Output Rise/Fall Times Q
200
540
200
540
200
540
200
540
ps
tf
(20% 80%)
1. Within-device skew is defined as identical transitions on similar paths through a device.
2. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point
of the outputs.
3. Minimum input swing for which AC parameters are guaranteed.
4. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between VPPmin and 1V. The lower end of the CMR range varies 1:1 with VEE. The
numbers in the spec table assume a nominal VEE = 3.3V. Note for PECL operation, the VCMR(min) will be fixed at 3.3V |VCMR(min)|.
445
MOTOROLA
MC100LVEL56 MC100EL56
MC100EL56
DC CHARACTERISTICS (VEE = 4.2V to 5.5V; VCC = GND)
40C
Symbol
Characteristic
Min
IEE
VBB
IIH
IINL
0C
Typ
Max
20
24
1.26
Min
Typ
Max
20
24
1.38
1.26
150
Dn
Dn
0.5
600
25C
Min
Typ
Max
20
24
1.38
1.26
150
0.5
600
85C
Min
Typ
Max
Unit
20
24
mA
1.26
150
1.38
150
0.5
600
0.5
600
50
50
MC100EL56
AC CHARACTERISTICS (VEE = 4.2V to 5.5V; VCC = GND)
40C
Symbol
Characteristic
D (Diff)
D (SE)
SEL
COMSEL
Min
Typ
340
290
430
430
0C
Max
Min
540
590
730
730
350
300
440
440
Typ
25C
Max
Min
550
600
740
740
360
310
440
440
Typ
85C
Max
Min
560
610
740
740
380
330
450
450
tPLH
tPHL
Propagation
Delay
to Output
tSKEW
WithinDevice Skew1
tSKEW
VPP(AC)
150
1000
150
1000
150
1000
VCMR
3.2
3.0
0.4
0.4
3.3
3.1
0.4
0.4
3.3
3.1
0.4
0.4
40
80
40
100
80
40
100
80
Typ
40
Max
Unit
580
630
750
750
ps
80
ps
100
ps
150
1000
mV
3.3
3.1
0.4
0.4
100
tr
Output Rise/Fall Times Q
200
540
200
540
200
540
200
540
ps
tf
(20% 80%)
1. Within-device skew is defined as identical transitions on similar paths through a device.
2. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point
of the outputs.
3. Minimum input swing for which AC parameters are guaranteed.
4. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between VPPmin and 1V. The lower end of the CMR range varies 1:1 with VEE. The
numbers in the spec table assume a nominal VEE = 4.5V. Note for PECL operation, the VCMR(min) will be fixed at 5.0V |VCMR(min)|.
MOTOROLA
446
MOTOROLA
MC100LVEL59
MC100EL59
20
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D04
Q0
Q0
VCC
Q1
Q1
VCC
Q2
Q2
VEE
20
19
18
17
16
15
14
13
12
11
TRUTH TABLE
SEL
Data
H
L
a
b
PIN NAMES
1
COM_SEL D0a
3
D0b
SEL0 D1a
10
D2b SEL2
Pins
Function
D0aD1a
D0bD1b
SEL0SEL1
COM_SEL
Q0Q2
Q0Q2
Input Data a
Input Data b
Individual Select Input
Common Select Input
True Outputs
Inverted Outputs
4/95
447
REV 1
MC100LVEL59 MC100EL59
MC100LVEL59
DC CHARACTERISTICS (VEE = 3.0V to 3.8V; VCC = GND)
40C
Symbol
Characteristic
IEE
IIH
Min
0C
Typ
Max
27
32
Min
25C
Typ
Max
27
32
150
Min
85C
Typ
Max
27
32
150
Min
Typ
Max
Unit
27
32
mA
150
Max
Unit
690
690
690
ps
150
MC100LVEL59
AC CHARACTERISTICS (VEE = 3.0V to 3.8V; VCC = GND)
40C
Symbol
Characteristic
Min
tPLH
tPHL
Propagation DATAQ/Q
Delay
SELQ/Q
COM_SELQ/Q
340
340
340
tsk(O)
OutputOutput Skew
Any Dn, Dm to Q
tr
tf
Typ
0C
Max
Min
690
690
690
340
340
340
25C
Typ
Max
Min
690
690
690
340
340
340
Typ
85C
Max
Min
690
690
690
340
340
340
Typ
ps
100
200
100
540
200
540
100
200
540
100
200
540
ps
Typ
Max
Unit
27
32
mA
150
Max
Unit
690
690
690
ps
MC100EL59
DC CHARACTERISTICS (VEE = 4.2V to 5.5V; VCC = GND)
40C
Symbol
Characteristic
IEE
IIH
Min
0C
Typ
Max
27
32
Min
25C
Typ
Max
27
32
150
Min
85C
Typ
Max
27
32
150
Min
150
MC100EL59
AC CHARACTERISTICS (VEE = 4.2V to 5.5V; VCC = GND)
40C
Symbol
Characteristic
Min
tPLH
tPHL
Propagation DATAQ/Q
Delay
SELQ/Q
COM_SELQ/Q
340
340
340
tsk(O)
OutputOutput Skew
Any Dn, Dm to Q
tr
tf
MOTOROLA
Typ
0C
Max
Min
690
690
690
340
340
340
Typ
25C
Max
Min
690
690
690
340
340
340
Typ
85C
Max
Min
690
690
690
340
340
340
Typ
ps
100
200
540
100
200
540
448
100
200
540
100
200
540
ps
MOTOROLA
MC100LVEL90
MC100EL90
20
1
A VBB output is provided for interfacing with single ended ECL signals
at the input. If a single ended input is to be used the VBB output should be
connected to the D input. The active signal would then drive the D input.
When used the VBB output should be bypassed to ground via a 0.01F
capacitor. The VBB output is designed to act as the switching reference
for the EL90 under single ended input switching conditions, as a result
this pin can only source/sink up to 0.5mA of current.
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D-04
PIN NAMES
Pins
Function
Dn
Qn
VBB
ECL Inputs
PECL Outputs
ECL Reference Voltage Output
Q0
Q0
GND
Q1
Q1
GND
Q2
Q2
VCC
20
19
18
17
16
15
14
13
12
11
PECL
PECL
PECL
ECL
ECL
ECL
10
VCC
D0
D0
VBB
D1
D1
VBB
D2
D2
VEE
7/95
449
REV 1
MC100LVEL90 MC100EL90
ECL INPUT DC CHARACTERISTICS
40C
Symbol
Characteristic
EL90
LVEL90
0C
25C
Min
Max
Min
Max
Min
4.2
3.0
5.5
3.8
4.2
3.0
5.5
3.8
4.2
3.0
Typ
85C
Max
Min
Max
Unit
5.5
3.8
4.2
3.0
5.5
3.8
150
VEE
Power Supply
Voltage
IIH
IIL
0.5
0.5
0.5
0.5
VPP
Minimum Peak-to-Peak
Input1
150
150
150
150
mV
VIH
1165
880
1165
880
1165
880
1165
880
VIL
1810
1475
1810
1475
1810
1475
1810
1475
VBB
Reference Output
1.38
1.26
1.38
1.26
1.38
1.26
1.38
1.26
IEE
8.0
mA
150
150
8.0
150
8.0
6.0
8.0
Condition
0C
25C
85C
Characteristic
Min
Max
Min
Max
Min
Typ
Max
Min
Max
Unit
VCC
3.0
3.8
3.0
3.8
3.0
3.3
3.8
3.0
3.8
VOH
2.215
2.42
2.275
2.42
2.275
2.35
2.42
2.275
2.42
VCC = 3.3V
VOL
1.47
1.745
1.49
1.68
1.49
1.60
1.68
1.49
1.68
VCC = 3.3V
20
24
26
mA
IGND
Power Supply Current
1. Levels will vary 1:1 with VCC.
24
24
Condition
0C
25C
Characteristic
Min
Max
Min
Max
Min
VCC
4.75
5.25
4.75
5.25
4.75
VOH
3.915
4.12
3.975
4.12
3.975
VOL
3.17
3.445
3.19
3.38
3.19
IGND
Power Supply Current
1. Levels will vary 1:1 with VCC.
MOTOROLA
24
24
450
Typ
85C
Max
Min
Max
Unit
5.25
4.75
5.25
Condition
4.05
4.12
3.975
4.12
VCC = 5.0V
3.30
3.38
3.19
3.38
VCC = 5.0V
20
24
26
mA
MC100LVEL90 MC100EL90
MC100LVEL90
AC CHARACTERISTICS (VEE = 3.0V to 3.8V; VCC = 3.0V to 3.8V)
40C
Symbol
Characteristic
Min
390
340
Max
Min
590
640
410
360
Typ
25C
Max
Min
610
660
420
370
Typ
85C
Max
Min
620
670
460
410
Typ
Max
Unit
660
710
ps
100
200
ps
tPLH
tPHL
Propagation Delay
D to Q
tSKEW
Skew OutputtoOutput1
ParttoPart (Diff)1
Duty Cycle (Diff)2
VPP
150
150
150
150
VCMR
See4
0.4
See4
0.4
See4
0.4
See4
0.4
tr
tf
230
500
230
500
230
500
230
500
1.
2.
3.
4.
Diff
S.E.
Typ
0C
20
100
200
20
25
100
200
20
25
100
200
20
25
25
mV
V
ps
Skews are valid across specified voltage range, parttopart skew is for a given temperature.
Duty cycle skew is the difference between a TPLH and TPHL propagation delay through a device.
Minimum input swing for which AC parameters guaranteed. The device has a DC gain of 40.
The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between VPPmin and 1V. VCMRmin depends on VEE, VPP and temperature. At
VPP < 500mV and 40C, VCMR is VEE +1.3V; and for 085C, VCMR is VEE +1.2V. At VPP 500mV and 40C, VCMR is VEE +1.5V; and for
085C, VCMR is VEE +1.4V.
MC100EL90
AC CHARACTERISTICS (VEE = 4.20V to 5.5V; VCC = 4.5V to 5.5V)
40C
Symbol
Characteristic
Min
tPLH
tPHL
Propagation Delay
D to Q
Diff
S.E.
tSKEW
Skew OutputtoOutput1
ParttoPart (Diff)1
Duty Cycle (Diff)2
Typ
390
340
20
0C
Max
Min
590
640
410
360
100
200
Typ
20
25
25C
Max
Min
610
660
420
370
100
200
Typ
20
25
85C
Max
Min
620
670
460
410
100
200
Typ
20
25
Max
Unit
660
710
ps
100
200
ps
25
VPP
150
VCMR
See4
0.4
See4
0.4
See4
0.4
See4
0.4
tr
tf
230
500
230
500
230
500
230
500
1.
2.
3.
4.
150
150
150
mV
V
ps
Skews are valid across specified voltage range, parttopart skew is for a given temperature.
Duty cycle skew is the difference between a TPLH and TPHL propagation delay through a device.
Minimum input swing for which AC parameters guaranteed. The device has a DC gain of 40.
The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between VPPmin and 1V. VCMRmin depends on VEE, VPP and temperature. At
VPP < 500mV and 40C, VCMR is VEE +1.3V; and for 085C, VCMR is VEE +1.2V. At VPP 500mV and 40C, VCMR is VEE +1.5V; and for
085C, VCMR is VEE +1.4V.
451
MOTOROLA
MOTOROLA
Product Preview
Triple PECL to ECL Translator
The MC100LVEL/EL91 is a triple PECL to ECL translator. The device
receives either standard or low voltage differential PECL signals and
translates them to either standard or low voltage differential ECL output
signals. The LVEL device can handle the low voltage signals while the EL
device is designed for the standard signals. It is possible to have low
voltage signals on one side and standard signals on the other if the
LVEL91 is used.
MC100LVEL91
MC100EL91
20
1
A VBB output is provided for interfacing with single ended PECL signals
at the input. If a single ended input is to be used the VBB output should be
connected to the D input. The active signal would then drive the D input.
When used the VBB output should be bypassed to ground via a 0.01F
capacitor. The VBB output is designed to act as the switching reference
for the EL91 under single ended input switching conditions, as aresult this
pin can only source/sink up to 0.5mA of current.
To accomplish the level translation the EL/LVEL91 requires three
power rails. The VCC supply should be connected to the positive supply,
and the VEE pin should be connected to the negative power supply. The
GND pins as expected are connected to the system ground plain. Both
VEE and VCC should be bypassed to ground via 0.01F capacitors.
Under open input conditions, the D input will be biased at VCC/2 and
the D input will be pulled to GND. This condition will force the Q output to
a low, ensuring stability.
Q0
Q0
GND
Q1
Q1
GND
Q2
Q2
VCC
20
19
18
17
16
15
14
13
12
11
ECL
PECL
PECL
PECL
10
VCC
D0
D0
D1
D1
PECL_VBB
ECL
PECL_VBB
ECL
D2
D2
VEE
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D-04
PIN NAMES
Pins
Function
Dn
Qn
PECL_VBB
PECL Inputs
ECL Outputs
PECL Reference Voltage Output
This document contains information on a product under development. Motorola reserves the right to
change or discontinue this product without notice.
7/96
452
REV 0.2
MC100LVEL91 MC100EL91
LVPECL INPUT DC CHARACTERISTICS
40C
Symbol
0C
25C
85C
Characteristic
Min
Max
Min
Max
Min
Typ
Max
Min
Max
Unit
VCC
3.0
5.25
3.0
5.25
3.0
3.3
5.25
3.0
5.25
IIH
150
IIL
VIH
2.135
2.420
2.135
2.420
2.135
2.420
2.135
2.420
VCC = 3.3V
VIL
1.49
1.825
1.49
1.825
1.49
1.825
1.49
1.825
VCC = 3.3V
VBB
Reference Output1
1.92
2.04
1.92
2.04
1.92
2.04
1.92
2.04
VCC = 3.3V
150
0.5
150
0.5
150
0.5
IGND
Power Supply Curremt
1. DC levels vary 1:1 with VCC.
Condition
0.5
6.0
mA
0C
25C
85C
Characteristic
Min
Max
Min
Max
Min
Typ
Max
Min
Max
Unit
VCC
4.75
5.25
4.75
5.25
4.75
5.0
5.25
4.75
5.25
IIH
150
IIL
VIH
3.835
4.120
3.835
4.12
3.835
4.12
3.835
4.120
VCC = 5.0V
VIL
3.19
3.525
3.19
3.525
3.19
3.525
3.19
3.525
VCC = 5.0V
VBB
Reference Output1
3.62
3.74
3.62
3.74
3.62
3.74
3.62
3.75
VCC = 5.0V
150
0.5
150
0.5
150
0.5
IGND
Power Supply Curremt
1. DC levels vary 1:1 with VCC.
Condition
0.5
6.0
mA
0C
25C
Characteristic
Min
Max
Min
Max
Min
VEE
Power Supply
EL91
Voltage
LVEL91
4.2
3.0
5.5
5.5
4.2
3.0
5.5
5.5
4.2
3.0
VOH
1085
880
1025
880
1025
VOL
1830
1555
1810
1620
1810
IEE
Typ
Max
Min
Max
Unit
5.5
5.5
4.2
3.0
5.5
5.5
955
880
1025
880
mV
1705
1620
1810
1620
mV
22
453
85C
Condition
mA
MOTOROLA
MC100LVEL91 MC100EL91
MC100LVEL91
AC CHARACTERISTICS (VEE = 3.0V to 3.8V; VCC = 3.0V to 3.8V)
40C
Symbol
Characteristic
Min
Typ
0C
Max
Min
Typ
25C
Max
Min
Typ
85C
Max
Min
Typ
Max
Unit
tPLH
tPHL
Propagation Delay
D to Q
Diff
S.E.
550
550
550
550
550
550
550
550
ps
tSKEW
Skew OutputtoOutput1
ParttoPart (Diff)1
Duty Cycle (Diff)2
75
200
25
75
200
25
75
200
25
75
200
25
ps
VPP
150
VCMR
2.0
1.8
tr
tf
1.
2.
3.
4.
150
150
150
mV
V
0.4
0.4
2.1
1.9
400
0.4
0.4
2.1
1.9
400
0.4
0.4
2.1
1.9
400
0.4
0.4
400
ps
Skews are valid across specified voltage range, parttopart skew is for a given temperature.
Duty cycle skew is the difference between a TPLH and TPHL propagation delay through a device.
Minimum input swing for which AC parameters guaranteed. The device has a DC gain of 40.
The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between VPPmin and 1V.
MC100EL91
AC CHARACTERISTICS (VEE = 4.20V to 5.5V; VCC = 4.75V to 5.25V)
40C
Symbol
Characteristic
Min
Typ
0C
Max
Min
Typ
25C
Max
Min
Typ
85C
Max
Min
Typ
Max
Unit
tPLH
tPHL
Propagation Delay
D to Q
Diff
S.E.
550
550
550
550
550
550
550
550
ps
tSKEW
Skew OutputtoOutput1
ParttoPart (Diff)1
Duty Cycle (Diff)2
75
200
25
75
200
25
75
200
25
75
200
25
ps
VPP
150
VCMR
3.2
3.0
tr
tf
1.
2.
3.
4.
150
150
150
mV
V
0.4
0.4
400
3.3
3.1
0.4
0.4
400
3.3
3.1
0.4
0.4
400
3.3
3.1
0.4
0.4
400
ps
Skews are valid across specified voltage range, parttopart skew is for a given temperature.
Duty cycle skew is the difference between a TPLH and TPHL propagation delay through a device.
Minimum input swing for which AC parameters guaranteed. The device has a DC gain of 40.
The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between VPPmin and 1V.
MOTOROLA
454
MOTOROLA
MC100LVEL92
>1500V ESD
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D-04
Q0
Q0
LVCC
Q1
Q1
LVCC
Q2
Q2
VCC
20
19
18
17
16
15
14
13
12
11
LVPECL
LVPECL
LVPECL
PECL
PECL
PECL
10
VCC
D0
D0
PECL
VBB
D1
D1
PECL
VBB
D2
D2
GND
PIN NAMES
Pins
Function
Dn
Qn
VBB
LVCC
VCC
GND
PECL Inputs
LVPECL Outputs
PECL Reference Voltage Output
VCC for LVPECL Output
VCC for PECL Inputs
Common Ground Rail
1/96
455
REV 1
MC100LVEL92
PECL INPUT DC CHARACTERISTICS
40C
Symbol
Characteristic
Min
VCC
4.5
IIH
IIL
VPP
0C
Max
Min
5.5
4.5
150
25C
Max
Min
5.5
4.5
85C
Typ
Max
Min
5.5
4.5
150
Max
150
Unit
5.5
150
Condition
0.5
600
0.5
600
0.5
600
0.5
600
Minimum Peak-to-Peak
Input1
200
200
200
200
mV
VIH
3385
4120
3385
4120
3385
4120
3385
4120
mV
VCC = 5.0V
VIL
3190
3515
3190
3525
3190
3525
3190
3525
mV
VCC = 5.0V
VBB
Reference Output2
3620
3740
3620
3740
3620
3740
3620
3740
mV
VCC = 5.0V
IVCC
12
mA
Dn
Dn
12
12
8.0
12
0C
25C
85C
Characteristic
Min
Max
Min
Max
Min
Typ
Max
Min
Max
Unit
VCC
3.0
3.8
3.0
3.8
3.0
3.3
3.8
3.0
3.8
VOH
2.215
2.42
2.275
2.42
2.275
2.35
2.42
2.275
2.42
VCC = 3.3V
VOL
1.47
1.745
1.49
1.68
1.49
1.60
1.68
1.49
1.68
VCC = 3.3V
15
20
21
mA
IGND
Power Supply Current
1. DC levels will vary 1:1 with VCC.
20
20
Condition
MC100LVEL92
AC CHARACTERISTICS (LVCC = 3.0V to 3.8V; VCC = 4.5V to 5.5V)
40C
Symbol
Characteristic
Diff
S.E.
0C
25C
85C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
490
440
590
590
690
740
510
460
610
610
710
760
510
460
610
610
710
760
530
480
630
630
730
780
ps
20
20
25
100
200
20
20
25
100
200
20
20
25
100
200
20
20
25
100
200
ps
tPLH
tPHL
Propagation Delay
D to Q
tSKEW
Skew OutputtoOutput1
ParttoPart (Diff)1
Duty Cycle (Diff)2
VPP
150
VCMR
1.3
VCC
0.2
1.2
VCC
0.2
1.2
VCC
0.2
1.2
VCC
0.2
VPP 500mV
1.5
VCC
0.2
1.4
VCC
0.2
1.4
VCC
0.2
1.4
VCC
0.2
150
150
150
mV
V
tr
Output Rise/Fall Times Q
320
580
320
580
320
580
320
580
ps
tf
(20% 80%)
1. Skews are valid across specified voltage range, parttopart skew is for a given temperature.
2. Duty cycle skew is the difference between a TPLH and TPHL propagation delay through a device.Common Mode Range4
3. Minimum input swing for which AC parameters guaranteed. The device has a DC gain of 40.
4. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between VPPmin and 1V.
MOTOROLA
456
CONTENTS
Design Guide:
System Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Transmission Line Theory . . . . . . . . . . . . . . . . . . 58
System Interconnect . . . . . . . . . . . . . . . . . . . . . . 518
Interfacing With ECLinPS . . . . . . . . . . . . . . . . . . 529
Packaging and Thermal Information . . . . . . . . . 532
Case Outlines . . . . . . . . . . . . . . . . . . . . . . . . . 537
Quality and Reliability . . . . . . . . . . . . . . . . . . . . . 543
Application Notes:
ECLinPS Circuit Performance at Standard
VIH Levels (AN1404) . . . . . . . . . . . . . . . . . . . 545
51
MOTOROLA
MOTOROLA
System Basics
SEMICONDUCTOR DESIGN GUIDE
SECTION 1
System Basics
taken so that the IR drops of the VEE bus do not create a VEE
voltage outside of the specification range. To provide the
switching currents resulting from stray capacitances and
asymmetric loading, the VEE power supply in an ECL system
needs to be bypassed. It is recommended that the VEE
supply be bypassed at each device with an RF quality 0.01F
capacitor to ground. In addition, the supply should also be
bypassed to ground with a 1.0F 10F capacitor at the
power inputs to a board. If a separate output termination
plane is used the VEE supply will be of a static nature as the
output switching current will return to ground via the VTT
supply, thus, the bypassing of every device may be on the
conservative side. If the design is going to include a liberal
use of serial or Thevenin equivalent termination schemes, a
properly bypassed VEE plane is essential.
VTT Supply
The output edge rates of the ECLinPS family necessitate
an almost exclusive use of controlled impedance
transmission lines for system interconnect (the details of this
claim will be discussed in a latter section). Thus, unless
Thevenin equivalent termination schemes are going to be
used, a VTT supply is a must in ECLinPS designs. The choice
of using only Thevenin equivalent termination schemes to
save a power supply should not be made lightly as the
Thevenin scheme consumes up to ten times more power
than the equivalent parallel termination to a 2.0V VTT
supply.
As was the case for the VEE supply, a dedicated power
plane, liberally bypassed as described above, should be
used for the VTT supply. In designs which rely heavily on
parallel termination schemes the V TT supply will be
responsible for returning the switching current of the outputs
to ground, therefore, a low AC impedance is a must. For
bypassing, many SIP resistor packs have bypass capacitors
integrated in their design to supply the necessary bypassing
of the supply. The use of SIP resistors will be discussed more
thoroughly in a later chapter.
VEE Supply
To take advantage of increased logic density and
temperature compensated outputs, many designers are
building array options with both, temperature compensated
output levels and a 5.2V VEE supply. To alleviate any
problems with interfacing these arrays to ECLinPS 100E
devices, Motorola has specified the operation of 100E
devices to include the standard 10H VEE voltage range.
Moreover, because of the superior voltage compensation of
the bias network, this guarantee comes without any changes
in the DC or AC specification limits. With the availability of
both 10H and 100K compatible devices in the ECLinPS
family, there is generally no need to run 10E devices at 100K
voltage levels. If, however, this is desired, the 10E devices
will function at 100E VEE levels with, at worst, a small
degradation in AC performance for a few devices due to soft
saturation of the current source device.
Although both the 10E and 100E devices can tolerate
variations in the VEE supply without any detrimental effects, it
is recommended that the VEE supply also have a dedicated
powerplane. If this is not a feasible constraint, care should be
Unused Inputs
All ECLinPS devices have internal 50k 75k pulldown
resistors connected to VEE. As a result, an input which is left
open will be pulled to VEE and, thus, set at a logic LOW.
These internal pulldowns provide more than enough noise
margin to keep the input from turning on if noise is coupled to
the input, therefore, there is no need to tie the inputs to VEE
external to the package. In addition, by shorting the inputs to
VEE external to the package, one removes the current limiting
effect of the pulldown resistor and, under extreme VEE
* Any reference to ECLinPS in this section include the ECLinPS Lite and Low Voltage ECLinPS families.
MOTOROLA
52
System Basics
a high state the other switches from a high to a low state
simultaneously, thus, the resultant current change through
the VCCO connection is zero. The current simply switches
between the two outputs. However, for the single-ended
output, the current change flows through the V CCO
connection of the output device. This current change through
the VCCO pin of the package causes a voltage spike due to
the inductance of the pin.
VCC
OUTPUT
CURRENT
FLOW
OUT
IN
VBB
SINGLE-ENDED OUTPUT
Unused Outputs
The handling of unused outputs is guided by two criteria:
power dissipation and noise generation. For single ended
output devices it is highly recommended to leave unused
outputs unterminated as there are no benefits in the
alternative scheme. This not only saves the power
associated with the output, but also reduces the noise on the
VCC line by reducing the current being switched through the
inductance of the VCC pins. For the counters and shift
registers of the family, the count and shift frequencies will be
maximized if the parallel outputs are left unterminated. Of
course, for applications where these parallel outputs are
needed this is not a viable alternative.
VEE
VCC
VCCO
OUTPUT
CURRENT
FLOW
OUT
IN
VBB
OUT
DIFFERENTIAL OUTPUTS
VEE
VCCO
53
MOTOROLA
System Basics
ECL outputs has always been a combination of increased
delay per OR-tie and the negative going disturbance seen at
the output when one output switches from a high to a low
while the rest of the outputs remain high. For high speed
devices the latter problem is the primary limitation due to the
increased sensitivity to this phenomena with decreasing
output transition times. The following paragraph will attempt
to describe the wire-OR glitch phenomena from a physical
perspective.
Figure 1.2 illustrates a typical wire-OR situation. For
simplicity, the discussion will deal with only two outputs;
however, the argument could easily be expanded to include
any number of outputs. If both the A and the B outputs start in
the high state they will both supply equal amounts of current
to the load. If the B output then transitions from a high to a low
the line at the emitter of B will see a sudden decrease in the
line voltage. This negative going transition on the line will
continue downward at the natural fall time of the output until
the A output responds to the voltage change and supplies the
needed current to the load. This lag in the time it takes for A to
correct the load current and return the line to a quiescent high
level is comprised of three elements: the natural response
time of the A output, the delay associated with the trace
length between the two outputs and the time it takes for a
signal to propagate through the package. The trace delay
can be effectively forced to zero by OR-tying adjacent pins.
The resulting situation can then be considered best case. In
this best case situation, if the delay through the package is
not a significant portion of the transition time of the output, the
resulting negative going glitch will be relatively small
(100mV). A disturbance of this size will not propagate
through a system. As the trace length between OR-tied
outputs increases, the magnitude of the negative going
disturbance will increase. Older ECL families specified the
maximum delay allowed between OR-tied outputs to prevent
the creation of a glitch which would propagate through a
system.
As this glitch phenomena is a physical limitation, due to
decreased edge rates, ECLinPS devices are susceptible to
the problem to an even greater degree than previous slower
ECL families. The package delay of even the 28-lead PLCC
A
PACKAGE
B
VTT
Wired-OR Connections
The use of wired-OR connections in ECL designs is a
popular way to reduce total part count and optimize the
speed performance of a system. The limitation of OR-tying
MOTOROLA
54
System Basics
With this in mind, the following recommendations are
offered for OR-tying in ECLinPS designs. First, OR-tying of
clock lines should be avoided as even in the best case
situation the disturbance on the line is significant and could
cause false clocking in some situations. In addition, wire
ORed outputs should be from the same package and
preferably should be adjacent pins. Non-adjacent outputs
should be within 1/2 of each other with the load resistor
connection situated near the midpoint of the trace (Figure
1.2). By following these guidelines, the practice of
wire-ORing ECL outputs can be expanded to the ECLinPS
family without encountering problems in the system.
50%
DATA
VBBmax
VBBnom
VBBmin
TPDnom
TPDmax
TPDnom
TPDmin
TPDnom
50%
OUTPUT
Clock Distribution
Clock skew is a major contributor to the upper limit of
operation of a high speed system; therefore, any reduction in
this parameter will enhance the overall performance of a
system. Through the ECLinPS family and new offerings in the
10H family, Motorola is providing devices uniquely designed
to meet the demands of low skew clock distribution.
By far the largest contributor to system skew is the
variation between different process lots of a given device.
This variation is what defines the total delay window specified
in the data sheets. This window can be minimized if the
devices are fully differential due to the output level defined
thresholds which ensure a centered input swing. The
propagation delay windows of single-ended ECL and other
logic technologies, are intimately tied to variations in the input
thresholds. As illustrated in Figure 1.3 although the delays,
when measured from the threshold of the input to the 50%
point of the output, are equal; when measured from the
specified 50% point of the input to the 50% point of the
output, the delays will vary with any shift in the switching
reference. Obviously, the magnitude of the delay difference is
also proportional to the edge rate of the input. In addition to
increasing the size of the delay windows, this reference shift
will cause the duty cycle of the output of a device to be
different than that of the input. Unfortunately, these
thresholds are perhaps the most difficult aspects of a logic
device to control. As a result, for the ultimate in low skew
performance differential ECL devices are a must. A quick
perusal of the ECLinPS databook will reveal a relatively large
number of totally differential devices which will lend
themselves nicely to very low skew applications such as
clock distribution.
55
MOTOROLA
System Basics
Generally, this task is accomplished with the use of a single
or series of D flip-flops as pictured in Figure 1.4. Because the
data signal and the clock signal are asynchronous, the
system designer cannot guarantee that the setup and hold
specifications for the device will be met. This in and of itself
would not cause a problem if it was not for the metastable
behavior of a D flip-flop. The metastable behavior of a flip-flop
is described by the outputs of a device attaining a nondefined
logic level or, perhaps, going into an oscillatory state when
the data and the clock inputs to the flip-flop switch
simultaneously. It has been shown that this metastable
behavior occurs across technology boundaries as well as
across performance levels within a technology.
Metastability Behavior
The metastability behavior and measurement of a flip-flop
is a complicated subject and necessitates much more time
than is available in this forum for a thorough explanation. As a
result, the following description is of an overview nature.
Anyone interested in a more thorough narration on the
subject is encouraged to read Application Note AN1504 on
page 579, which contains a more detailed discussion on the
subject.
In many designs, occasions arise where an asynchronous
signal needs to be synchronized to the system clock.
SYSTEM 1
SYSTEM 1
OUTPUT
SYSTEM 1
CLOCK
DATA
SYSTEM 2 INPUT
D-FLIP-FLOP
SYSTEM 2
SYSTEM 2
CLOCK
CLOCK
SYSTEM 1
SYSTEM 1
CLOCK
SYSTEM 2
CLOCK
SYSTEM 1
OUTPUT
DATA
D-FLIP-FLOP
DATA
SYSTEM 2 INPUT
D-FLIP-FLOP
SYSTEM 2
CLOCK
CLOCK
TD DELAY
MOTOROLA
56
System Basics
The challenge then becomes, how to characterize
metastability behavior given the above circumstances. The
standard method in the industry is to use Stolls1 equation,
combined with the standard MTBF equation, to develop the
following relationship:
MTBF = 1 / (2*fC*fD*TP*10 (t/))
where:
fC:
Clock Frequency
fD:
Data Frequency
Tp:
FF Propagation Delay
t:
Time Delay Between FF
Clocks
:
FF Resolution Time
Constant
Note that the clock frequency, data frequency and time
delay between flip-flops are user-defined parameters, thus it
is up to Motorola to provide only the propagation delays and
the resolution time constants for the ECLinPS flip-flops.
The propagation delays are, obviously, already defined
leaving only the resolution time constant yet to be
determined. An evaluation fixture was fabricated and several
ECLinPS flip-flops were evaluated for resolution time
constants.The results of the evaluation showed that the time
constant was somewhat dependent on the part type as all the
flip-flops in the ECLinPS family do not use the same general
design. The time constants range from 125225 ps
depending on the part type.
As an example, for a system with a 100MHz clock and
75MHz data rate, the required delay between clock edges of
a cascaded flip-flop chain for the E151 register, assuming a
of 200ps, would be:
MTBF = 1 / (2*100MHz*75MHz*800ps*10 t/200ps)
TD = t + TP = 3.9ns
So, for an MTBF of 10 years for the above situation the
second flip-flop should be clocked 3.9ns after the first. Similar
results can be found by applying the equation to different
data and clock rates as well as different acceptable MTBF
rates.
1 Stoll, P. How to Avoid Synchronization Problems,
VLSI Design, November/December 1982. pp. 5659.
57
MOTOROLA
MOTOROLA
SECTION 2
Transmission Line Theory
ZO=V/I=(LO/CO)
Introduction
The ECLinPS family has pushed the world of ECL into the
realm of picoseconds. When output transitions move into this
picosecond region it becomes necessary to analyze system
interconnects to determine if transmission line phenomena
will occur. A handy rule of thumb to determine if an
interconnect trace should be considered a transmission line
is if the interconnect delay is greater than 1/8th of the signal
transition time, it should be considered a transmission line
and afforded all of the attention required by a transmission
line. If this rule is applied to the ECLinPS product line a
typical PCB trace will attain transmission line behaviors for
any length >1/4. Thus, a brief overview of transmission line
theory is presented, including a discussion of distributed and
lumped capacitance effects on transmission lines. For a
more thorough discussion of transmission lines the reader is
referred to Motorolas MECL Systems Design Handbook.
where:
LO = Inductance per unit length (H)
CO = Capacitance per unit length (F)
Propagation Delay
Propagation delay (TPD) is also expressed as a function of
both the inductance and capacitance per unit length of a
transmission line. The propagation delay of the line is defined
by the following equation:
TPD=(LO*CO)
=1/TPD=1/(LO*CO)
LO and CO can be determined using the easily measured
parameters of line delay (TD), line length (L), and the line
characteristic impedance (ZO) in conjunction with Equations
1 and 2. The propagation delay is defined as the ratio of line
delay to line length:
TPD=TD/L
Combining equations 1 and 2 yields:
CO=TPD/ZO
LO=TPD*ZO
(Equation 3)
(Equation 4)
Characteristic Impedance
An interconnect which consists of two conductors and a
dielectric, characterized by distributed series resistances and
inductances along with distributed parallel capacitances
between them, is defined as a transmission line. These
transmission lines exhibit a characteristic impedance over
any length for which the distributed parameters are constant.
Since the contribution of the distributed series resistance to
the overall impedance is minimal, this term can be neglected
when expressing the characteristic impedance of a line. The
characteristic impedance is a dynamic quantity defined as
the ratio of the transient voltage to the transient current
passing through a point on the line. Thus, ZO can be
expressed in terms of the distributed inductance and
capacitance of the line as shown by Equation 1.
MOTOROLA
(Equation 2)
Background
(Equation 1)
ZO
NODE a
RO = 6
RE
58
IR = VR/ZO
Using substitution:
VT/RT = VS/ZO VR/ZO
IR
ZO
VIN
RT
VR = L*VS
IT
2. RS ZO; RT = ZO
3. RS = ZO; RT ZO
V(x,t)
where:
RS
= Source Resistance
RT
= Termination Resistance
(Equation 8)
1. RS < ZO; RT ZO
VA(t)*[U(tTPD*x) + L*U(tTPD(2Lx) +
L*S*U(tTPD(2L+x)) +
(L**2)*(S*U(tTPD(4Lx)) +
(L**2)*S**2)*U(tTPD(4L+x)) + ] +
VDC
(Equation 9)
where:
VA
TPD
L
x
VDC
IT = IS + IR where:
IT = VT/RT
(Equation 7)
Therefore:
NODE a
VR
(Equation 6)
VS, IS
RS
(Equation 5)
59
MOTOROLA
Likewise, after a time equal to three times the line delay, the
output voltage VT is
Hence:
VS/ZO)>(VS/RT)
IS + IR
IR
VS
OUTPUT VOLTAGE-V T
LINE VOLTAGE
VR
VT
IS
TL < t < 2TL
L
DISTANCE
TIME
ZO = 50
VT
VIN
H=1000ps/div
V=200mV/div
Configuration 2: RT < ZO
For the case in which RT<ZO, L is negative, and the initial
current at node a is less than the final quiescent current.
IINITIAL < IFINAL
RT = 65
Hence:
(VS/ZO) < (VS/RT)
MOTOROLA
510
VS
IR
IS
IS + IR
VT
OUTPUT VOLTAGE-V T
LINE VOLTAGE
VR
DISTANCE
TIME
RS = RO = 6
ZO = 50
VT
VIN
H=1000ps/div
V=200mV/div
RT = 35
Figure 2.9 shows the line response for the same circuit as
above, but for the case in which the input pulse width is less
than the line delay. As in the previous example, the initial
steady state voltage across the transmission line is 1.49
volts, and the reflection coefficients are 0.18 and 0.79 for
the load and source respectively. However, the intermediate
voltage across the transmission line is a series of
positive-going pulses of decreasing amplitude for each round
OUTPUT VOLTAGE-V T
S = (6 50)/(6+50) = 0.79
H=1000ps/div
V=200mV/div
From Equation 9, the output voltage VT after one line delay is:
VT(L,TPD) = VA(t)*[1 + L] + VDC = 0.87V
Likewise, after a time equal to three times the line delay, the
output voltage VT is:
VT(L,3TPD)=VA(t)*[L*L+L**2*S]+VT(L,TPD)=
0.78V
Additional iterations of Equation 9 can be performed to show
that the output response asymptotically approaches 0.77
trip of the reflected voltage, until the final steady state voltage
of 1.49 volts is reached.
Shorted Line
The shorted line is a special case of configuration 2 in
which the load reflection coefficient is 1.0, and the
reflections tend toward the steady state condition of zero line
voltage and a current defined by the source voltage and the
source resistance.
511
MOTOROLA
ZO = 50
VT
VIN
TIME
S = (16.750)/(16.7+50) = 0.5
Upon reaching the shorted end of the line, the initial voltage
waveform is inverted and reflected toward the source. At the
source end, the voltage is partially reflected back toward the
shorted end in accordance with the source reflection
coefficient. Thus, the voltage at the shorted end of the
transmission line is always zero while at the source end, the
voltage is reduced for each round trip of the reflected voltage.
The voltage at the source end tends toward the final steady
state condition of zero volts across the transmission line. The
values of the source and line characteristic impedances in
this example are such that the amplitude decreases by 50%
with each successive round trip across the transmission line.
RT = 50
VIN
TIME
H=1000ps/div
V=200mV/div
MOTOROLA
ZO = 50
VT
H=1000ps/div
V=200mV/div
512
L = (5050)/(65+50) = 0
S = (650)/(6+50) = 0.79
From Equation 9, the output voltage VT after one line delay is:
Thus, the output response attains its final steady state value
(Figure 2.14) after only one line delay when the termination
S = (5050)/(50+50) = 0
From Equation 9, the output voltage VT after one line delay is:
OUTPUT VOLTAGE-V T
TIME
H=400ps/div
V=200mV/div
Thus, the output response attains its final steady state value
after one line delay when the source resistance matches the
line characteristic impedance. Again, ringing or a stair-step
output does not occur since the load reflection coefficient is
zero (Figure 2.16).
OUTPUT VOLTAGE-V T
RS = 50
5
TIME
ZO = 50
H=400ps/div
V=100mV/div
VIN
RT = 65
Series Termination
Series termination represents a special subcategory of
Case 3 in which the load reflection coefficient is +1 and the
source resistance is made equal to the line characteristic
impedance by inserting a resistor, RST, between and in series
with, the transmission line and the source resistance RO. The
513
MOTOROLA
(Equation 10)
ZO = 50
RST = 44
VT
VIN
OUTPUT VOLTAGES
VT
VS
TIME
H=400ps/div
V=200mV/div
RS = Z0
ZO = 50
NODE a
S = (50 50)/(50+50) = 0
CL
VIN
MOTOROLA
placed at the end of the line increases the rise time of the
output signal, thereby increasing TD by an amount TD
(Figure 2.19b). Figure 2.20 shows the increase in delay for
load capacitances of 0, 1, 5, 10 and 20 picoFarads.
514
ZO
VIN
VIN
CL
50%
LINE
INPUT
Z = ZO
CL
ZC = ZO CL
TD
TD
ZO
LOADED
RESPONSE
50%
VIN/2
VIN
CL
CL
RT
ZC = (ZO/2)CL
UNLOADED
RESPONSE
LINE
OUTPUT
Z = ZO/2
VLOW
CL = 20pF
CL = 10pF
CL = 5pF
CL = 1pF
TIME
H=1000ps/div
V=200mV/div
t=0
VHIGH
tR = 0.6a
a = 1.67tR
t=a
OUTPUT VOLTAGES
CL = 0pF
80%
50%
20%
2.0
1.5
1.0
0.5
0.0
0.0
0.5
1.0
1.5
2.0
2.5
515
MOTOROLA
VOLTAGE-VS
tR = 750ps
tR = 950ps
TD/tR = 0.9
Therefore:
TIME
TD = 0.9*400ps = 360ps
VIN
VOLTAGE-VS
ZO = 50
CL
H=1000ps/div
V=100mV/div
RT = ZO
RS = RT = 93
RS = 93, RT = 76
RS = RT = 76
MOTOROLA
TIME
H=2000ps/div
V=100mV/div
516
(Equation 11)
TPD = (LO*(CO+CD))
TPD = TPD *(1 + CD/CO)
(Equation 12)
For the circuit used to obtain the traces in Figure 2.25, the
distributed load capacitance is 4pF. From Equation 3, CO is
calculated as
CO = 750ps/93 = 8pF
Hence:
ZO 93/(1 + 4pF/8pF) = 76
Thus, the effective line impedance is 17 lower than the
actual impedance while reflections are occurring on the line.
(Equation 1 3)
517
MOTOROLA
MOTOROLA
System Interconnect
SEMICONDUCTOR DESIGN GUIDE
SECTION 3
System Interconnect
Introduction
As mentioned earlier, edge rates of the ECLinPS family
are such that most interconnects must be treated as
transmission lines. Thus, a controlled impedance
environment is necessary to produce predictable
interconnect delays as well as limiting the reflection
phenomena of undershoot and overshoot. The three most
common techniques for circuit and/or system interconnect at
high data rates are microstrip, stripline and coaxial cable;
both microstrip and stripline are printed circuit board
methods, whereas coaxial cable is most often used for
interconnecting different parts of a system which are
separated by relatively large distances. For slower speed
applications (<300MHz), a twisted pair scheme also works
well. The scope of this writing will not include the twisted pair
technique; however, a detailed discussion of this topic can be
found in the MECL System Design Handbook. Finally,
wirewrap boards are not recommended for the ECLinPS
family because the fast edge speeds exceed the capabilities
of normal wirewrapped connections. Mismatches at the
connections cause reflections which distort the fast signal,
significantly reducing the noise immunity of the system and
perhaps causing erroneous operation.
Glass-Epoxy
Possesses good moisture absorption, chemical and heat
resistance properties as well as mechanical strength over
standard humidity and temperature ranges. The most widely
used versions are G10 and FR4, the fire resistant version of
G10.
Glass-Polyimide
Good for elevated temperature operation because of its
tight tolerance of the coefficient of thermal expansion. Very
hard material, so it may damage drilling equipment when
being drilled.
1. Single-sided boards
Glass-Teflon
2. Double-sided boards
3. Multilayer boards
Material
Dielectric
Constant
Dissipation
Factor
Thermal Coefficient
of Expansion
Tensile
Modulus
Glass-Epoxy
4.8 (1.0MHz)
0.022 (1.0MHz)
13 16 (106C)
2.5
0.0004 (10GHz)
224 (106C)
0.05
0.10 (1.0MHz)
12 14 (106C)
2.8
PTFE
2.1 (10GHz)
Glass-Polyimide
4.5 (1.0MHz)
MOTOROLA
518
System Interconnect
Microstrip
5
LINE CAPACITANCE CO(pF/Inch)
t
DIELECTRIC
h = mils
= 4.8
t = 1.4 mils
h = 30
h = 15
h = 60
h = 100
1
10
30
GROUND PLANE
87
(r + 1.41)
(5.98 * h)
(0.8w + t)
In
(Equation 1)
90
110
= 4.8
t = 1.4 mils
5
4
3
2
1
25
where:
r
w
t
h
70
ZO =
50
45
65
85
105
125
CHARACTERISTIC IMPEDANCE-ZO()
LINE IMPEDANCE-ZO ( )
150
h = mils
= 4.8
t = 1.4 mils
130
110
90
(eqt 2)
h = 100
70
h = 60
50
where:
r
h = 30
h = 15
30
10
30
50
70
90
110
519
MOTOROLA
System Interconnect
90
LINE IMPEDANCE-ZO ( )
200
180
160
140
120
80
70
60
50
40
100
2
b = mils
= 4.8
t = 1.4 mils
10
b = 20
b = 30
11
14
b = 60
17
20
Stripline
Stripline is a printed circuit board interconnect in which a
signal conductor is placed in a dielectric medium which is
sandwiched between two conducting layers (Figure 3.5).
4.0
w
GROUND PLANE
b
b = 50
DIELECTRIC
b = 40
b = 20
b = 30
b = 40
b = 50
b = 60
3.5
3.0
2.5
2.0
b = mils
= 4.8
t = 1.4 mils
5
GROUND PLANE
11
14
17
20
= 4.8
t = 1.4 mils
ZO =
60
r
In
4b
0.67(0.8w + t)
CAPACITANCE-CO (pF/inch)
(Equation 3)
where:
r
w
t
b
MOTOROLA
5
4
3
2
40
60
80
100
120
CHARACTERISTIC IMPEDANCE-ZO ()
1
20
520
(Equation 4)
System Interconnect
where:
r
270
230
150
110
10
1.6w 2.0w
Coaxial Cable
Coaxial cable is a two conductor transmission line
consisting of a concentric inner conductor surrounded by a
dielectric which in turn is surrounded by a tubular outer
conductor (Figure 3.10). It is ideal for transmitting high
frequency signals over long distances because of its well
defined and uniform characteristic impedance. Moreover,
crosstalk is minimized by the ground shield provided by the
outer conductor.
The propagation delay is derived in the same way as a
stripline interconnect and, thus, is described by Equation 4.
Therefore, as with stripline structures, the delay is a function
DIELECTRIC
OUTPUT
CONDUCTOR
INNER
CONDUCTOR
521
MOTOROLA
System Interconnect
Coaxial Cable Lengths
The ECLinPS family operates with rise times as fast as
several hundred picoseconds; thus, coaxial cable must be
able to transmit these pulses without introducing a significant
distortion. Viewing the ECLinPS output as a single time
constant driver circuit terminated with a 50 load, the
required line bandwidth(fc) can be calculated as follows.
fC = 0.35/tR
Summary of Values
Table 3.2 is a compilation of propagation delays at nominal
dielectric values for the three types of interconnects
discussed.
(Equation 5)
where:
tR
Interconnect
TPD
Microstrip
Stripline
Coaxial Cable
145ps/in
185ps/in
123ps/in
4.8
4.8
2.1
Termination Techniques
From transmission line theory, a signal propagating down
the line is partially reflected back to the source if the line is not
terminated in its characteristic impedance. The magnitude of
the reflected voltage signal is governed by the load reflection
coefficient, L.
L = (RT ZO) / (RT + Z0)
(Equation 6)
where:
1.48
ZO
1.10
0.90
RG58/U
0.70
RG59/U
0.50
0.30
7.6
RG188A/U
1.30
RT
7.8
8.0
8.2
8.4
8.6
(Equation 7)
where:
8.8
9.0
RS
= Source Impedance
ZO
Loss(dB)
= 20 * log (VIN/VO)
= 20 * log (0.85/0.6) = 3.0dB.
MOTOROLA
3. Series Termination
522
System Interconnect
Unterminated Lines
Figure 3.12 illustrates an unterminated transmission line.
This configuration is also referred to as a stub or an open line.
A
B
TD
RE
ZO
VEE
(Equation 8)
(Equation 11)
(Equation 12)
where:
L
= Line Length
tR
TPD
= Rise time
= Propagation Delay per unit Length
(Equation 9)
Solving Equation 13 for the maximum line length produces:
(Equation 10)
523
MOTOROLA
System Interconnect
Microstrip
ZO()
50
68
75
82
90
100
Stripline
Fanout = 1
Fanout = 2
Fanout = 1
Fanout = 2
Lmax (in)
Lmax (in)
L(max) (in)
L(max) (in)
0.3
0.3
0.3
0.3
100
0.25
0.2
0.15
0.15
0.1
0.1
0.1
0.3
0.25
0.25
0.25
0.25
0.25
0.15
0.1
0.1
0.1
0.1
0.1
Table 3.3. SPICE Derived Maximum Open Line Lengths for ECLinPS Designs
Parallel Termination
When the fastest circuit performance or the ability to drive
distributed loads is desired, parallel termination is the method
of choice. An important feature of the parallel termination
scheme is the undistorted waveform along the full length of
the line. A parallel terminated line is one in which the
receiving end is terminated to a voltage (VTT) through a
resistor (RT) with a value equal to the line characteristic
impedance (Figure 3.13a). An advantage of this technique is
that power consumption can be decreased by a judicious
choice of VTT. For 50 systems, the typical value of VTT is
negative two volts.
(Equation 15)
(Equation 16)
ZO
RT
R2 = 2.6 * ZO
(Equation 17)
R1 = R2 / 1.6
(Equation 18)
VTT
R2 = 2.25 * ZO
(Equation 19)
R1 = R2 / 1.25
(Equation 20)
50
70
75
80
90
100
120
150
ZO
R2
VEE
FIGURE 3.13B THEVENIN EQUIVALENT PARALLEL TERMINATION
MOTOROLA
100E
ZO ()
R1
R1 ()
R2 ()
R1 ()
R2 ()
81
113
121
130
146
162
194
243
130
182
195
208
234
260
312
390
90
126
135
144
161
180
216
270
113
158
169
180
202
225
270
338
524
System Interconnect
For both configurations, when the equivalent termination
resistance matches the line impedance no reflection occurs
because all the energy in the signal is absorbed by the
termination. Hence, the primary tradeoff between the two
types of termination schemes are power versus power supply
requirements. As mentioned earlier, the VTT scenario
r e q u i r e s a n e x t r a p o w e r s u p p l y ; h o w e v e r, t h e
Theveninization technique will consume 10 fold more DC
power. Fortunately, this extra power consumption will not be
seen on the die, therefore, both techniques will result in the
same die junction temperatures.
RH
VOH
770mV
VOL
RL
150 to 2.0V
100 to 2.0V
RH
25 to 2.0V
VOL
50 to 2.0V
VOH
30
40
2.0
(Equation 23)
where:
IHOUT = ( 830mV VTT) / (6 + RT)
15
35
(Equation 22)
where:
ILOUT = (1710mV VTT) / (8 + RT)
10
25
VTT
1710mV
100E Devices
The equivalent output circuit is shown in Figure 3.16. The
output levels are estimated from Figure 3.16 as follows:
SLOPE = 6 8
20
RT
830mV
Ta = 25C
VOH
VOL
RL
1.75 1.5
1.25
RT
VTT
1660mV
10E Devices
The equivalent output circuit is shown in Figure 3.15. The
output levels are estimated from Figure 3.15 as follows:
VOH = 770mV 6*IHOUT
(Equation 21)
525
MOTOROLA
System Interconnect
and
V0L = 1660mV 8 * ILOUT
(Equation 24)
where:
ILOUT = (1660mV VTT)/(8 + RT)
SIP Resistors
The choice of resistor type for use as the termination
resistor has several alternatives. Although the use of a
discrete, preferably chip resistor, offers the best isolation and
lowest parasitic additions, there are SIP resistor packs which
will work fine for ECLinPS designs. SIP resistors offer a level
of density which is impossible to obtain using their discrete
counterparts. However, there are some guidelines which the
user should follow when using SIP resistor packs. Always
terminate complimentary outputs in the same pack to
minimize inductance effects on the SIP power pin. Noise
generated on this pin will couple directly into all of the
resistors in the pack. In addition, the SIP package should
incorporate bypass capacitors in the design (Figure 3.17).
These capacitors are necessary to help maintain a solid VTT
level within the package, again mitigating any potential
crosstalk or feed through effects. A 10 pin SIP like the DALE
CSRC-10B21-500J/103M, is suitable for providing 50
terminations while maintaining a relatively noise free
environment to non-switching inputs.
(Equation 25)
(Equation 26)
RST + RO = ZO
RE
ZO
RST
RE
VEE
MOTOROLA
VEE
ZO
Calculation of RE
RE functions to establish VOH and VOL levels and to
provide the negative going drive into RST and ZO when the
driver output switches to the low state. The value of RE must
526
System Interconnect
VOH = 0.9V, VSWING = 0.85V, VEE = 5.2
RST
(Equation 29)
RE
VEE
1 / RE
ZO
VOH
(Equation 31)
RST
RE
(Equation 30)
1 / (7.10*ZO1 RST1) +
1 / (7.10*ZO2 RST2) +
1 / (7.10*Z03 RSTn)
VEE
(Equation 32)
1 / (6.56*ZO1 RST1) +
1 / (6.56*ZO2 RST2) +
1 / (6.56*Z03 RSTn)
(Equation 33)
(Equation 28)
527
(Equation 34)
MOTOROLA
System Interconnect
is 150A. Thus, for the circuit shown in Figure 3.22, in which
three gate loads are present in a 50 environment, the loss
in high state noise margin is calculated as:
RO
RST
RE
ZO
VEE
MOTOROLA
528
MOTOROLA
SECTION 4
Intefacing with ECLinPS
Interfacing to Existing ECL Families
There currently exists two basic standards for high
performance ECL logic devices: 10H and 100K. To maximize
system flexibility each member of the ECLinPS family is
available in both of the existing ECL standards: 10E series
devices are compatible with the MECL 10H family; 100E
series devices are compatible with ECL 100K.
10H
10H
100H
100H
>
>
>
>
10H
100H
100H
10H
150mV
145mV
130mV
35mV
150mV
125mV
135mV
130mV
1.4
1.6
1.8
15
30
45
60
75
90
1.0
NM Low
TEMPERATURE (C)
NM High
NM high
1.2
1.0
NM high
1.2
1.4
1.6
1.8
15
30
45
60
75
90
TEMPERATURE (C)
529
MOTOROLA
IN
OUT
E116
OUT
AC Coupling
In some cases, it may be necessary to interface an
ECLinPS design with a signal which lacks any DC offset.The
differential devices in the ECLinPS family are ideally suited
for this application. As pictured in Figure 4.3, the signal can
be AC coupled and biased around the VBB switching
reference of the device. Note that this scheme only works for
a data stream with no DC bias, for data streams such as RZ
or unencoded NRZ DC, restoration must be performed prior
to AC coupling it to an ECLinPS device.
1.0K
IN
0.001F
50
OUT
E116
E416
OUT
400
50
50
0.01F
0.01F
VBB
50
VTT
50
VBB
VTT
MOTOROLA
530
VCC
2.5K
OUT
IN
0.001F
50
E116
E416
OUT
Note that the circuit pictured in Figure 4.4 will result in the
Q outputs going high when the inputs are left open. If the
opposite is desired, the resistor to VCC can be tied to the
inverting input and VBB to the non-inverting input.
0.01F
50
50
VBB
E116
VTT
VBB
VBB
50
SINGLE GATE VBB GENERATOR
VTT
E116
VBB
VBB
E116
VBB
50
531
MOTOROLA
MOTOROLA
SECTION 5
Package and Thermal Information
Package Choice
General Information
REEL SIZE: 13 (330mm)
TAPE WIDTH: 24mm
UNITS/REEL: 500
Mechanical Polarization
PIN 1
VIEW FROM
TAPE SIDE
MOTOROLA
Thermal Management
As in any system, proper thermal management is
essential to establish the appropriate trade-off between
performance, density, reliability and cost. In particular, the
designer should be aware of the reliability implication of
continuously operating semiconductor devices at high
junction temperatures.
The increasing popularity of surface mount devices (SMD)
is putting a greater emphasis on the need for better thermal
management of a system. This is due to the fact that SMD
packages generally require less board space than their
through hole counterparts so that designs incorporating SMD
technologies have a higher thermal density. To optimize the
thermal management of a system it is imperative that the
user understand all of the variables which contribute to the
junction temperature of the device.
532
T = 6.376 10 9 e
11554.267
273.15 + TJ
Where:
TJ = TA + PDJA
Time (Hrs.)
Time (yrs.)
80
90
100
110
120
130
140
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
117.8
47.9
20.4
9.1
4.2
2.0
1.0
where:
TJ
TA
PD
JA
= Junction Temperature
= Ambient Temperature
= Power Dissipation
= Avg Pkg Thermal Resistance (Junction Ambient)
533
MOTOROLA
Differential Output
Single-ended Output
(50%) Duty Cycle)
Single-ended Output
(Worst Case)
10E
100E
10E
100E
10E
100E
50 to 2.0V
68 to 2.0V
100 to 2.0V
14.3
10.5
7.1
15.0
11.1
7.5
14.3
10.5
7.1
15.0
11.1
7.5
19.8
14.6
9.9
20.0
14.7
10.0
510 to 5.2V
330 to 5.2V
180 to 5.2V
9.7
15.0
27.5
9.8
15.1
27.8
9.7
15.0
27.5
9.8
15.1
27.8
11.8
18.3
33.5
11.7
18.0
33.1
510 to 4.5V
330 to 4.5V
180 to 4.5V
7.8
12.3
22.6
7.8
12.3
22.6
9.3
14.4
26.4
JA ( C/W)
80
70
(JA) (C/W)
60
0
125
250
500
1000
63.5
52
48
43.5
38
50
40
30
20
0
125
250
375
500
625
750
875
1000
Figure 5.4. Thermal Resistance vs Air Flow for the 28-lead PLCC
MOTOROLA
534
Heatsinks
typical
worst case
Junction Temperature =
2
(0.08)
0.76
A
(0.030)
0.51
(0.020)
0.76
(0.030)
A
Unit: mm (inch)
Min. Value
0.51
(0.020)
Dimension A
Inches
mm
PLCC-20
0.430
10.9
PLCC-28
0.530
13.5
PLCC-44
0.630
16
535
MOTOROLA
Package Dimensions
Figure 5.5 on the previous page provides recommended
printed circuit board solder pad dimensions for several PLCC
packages. With this information and the 28-lead PLCC
dimensions provided in Figure 5.6, the system designer
should have all of the information necessary to successfully
mount 28-lead PLCC packages on a surface mount PCB.
MOTOROLA
536
Case Outlines
Case Outlines
8Pin Package
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 75105
ISSUE P
A
M
1
4
0.25 (0.010)
4X
X 45 _
B
M
NOTES:
1. DIMENSIONS A AND B ARE DATUMS AND T IS A
DATUM SURFACE.
2. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
3. DIMENSIONS ARE IN MILLIMETER.
4. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
6. DIMENSION D DOES NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE D DIMENSION AT MAXIMUM MATERIAL
CONDITION.
M_
G
DIM
A
B
C
D
F
G
J
K
M
P
R
T
K
SEATING
PLANE
8X
D
0.25 (0.010)
T B
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.18
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
16Pin Packages
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B05
ISSUE J
A
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
B
1
8 PL
0.25 (0.010)
X 45 _
C
T
SEATING
PLANE
M
D
16 PL
0.25 (0.010)
T B
537
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
MOTOROLA
Case Outlines
L SUFFIX
CERAMIC DIP PACKAGE
CASE 62010
ISSUE V
A
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
B
C
T
K
SEATING
PLANE
E
F
G
D
16 PL
0.25 (0.010)
16 PL
0.25 (0.010)
T A
T B
DIM
A
B
C
D
E
F
G
H
K
L
M
N
INCHES
MIN
MAX
0.750
0.785
0.240
0.295
0.200
0.015
0.020
0.050 BSC
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
19.05
19.93
6.10
7.49
5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0_
15 _
0.51
1.01
20Pin Packages
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D04
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
A
20
11
10X
P
0.010 (0.25)
10
20X
0.010 (0.25)
T A
J
S
F
R X 45 _
C
T
18X
MOTOROLA
SEATING
PLANE
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
12.65
12.95
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0_
7_
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.499
0.510
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0_
7_
0.395
0.415
0.010
0.029
538
Case Outlines
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 77502
ISSUE C
0.007 (0.180) M T LM
B
Y BRK
0.007 (0.180) M T LM
D
L
Z
W
20
0.010 (0.250)
G1
T LM
VIEW DD
0.007 (0.180) M T LM
0.007 (0.180) M T LM
SEATING
PLANE
VIEW S
G1
0.010 (0.250) S T LM
0.007 (0.180)
T LM
VIEW S
S
NOTES:
1. DATUMS L, M, AND N DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS PLASTIC
BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM T, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS,
GATE BURRS AND INTERLEAD FLASH, BUT
INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE
THE H DIMENSION TO BE SMALLER THAN 0.025
(0.635).
0.004 (0.100)
J
K1
E
G
0.007 (0.180) M T LM
539
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.385
0.395
0.385
0.395
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
0.025
0.350
0.356
0.350
0.356
0.042
0.048
0.042
0.048
0.042
0.056
0.020
2_
10 _
0.310
0.330
0.040
MILLIMETERS
MIN
MAX
9.78
10.03
9.78
10.03
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
0.64
8.89
9.04
8.89
9.04
1.07
1.21
1.07
1.21
1.07
1.42
0.50
2_
10 _
7.88
8.38
1.02
MOTOROLA
Case Outlines
28Pin Package
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 77602
ISSUE D
0.007 (0.180)
T LM
T LM
Y BRK
0.007 (0.180)
D
Z
M
W
28
G1
0.010 (0.250)
T LM
VIEW DD
0.007 (0.180)
0.007 (0.180)
T LM
T LM
0.007 (0.180)
T LM
K1
E
0.004 (0.100)
G
SEATING
PLANE
VIEW S
G1
0.010 (0.250)
T LM
MOTOROLA
T LM
VIEW S
NOTES:
1. DATUMS L, M, AND N DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM T, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
0.007 (0.180)
540
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.485
0.495
0.485
0.495
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
0.025
0.450
0.456
0.450
0.456
0.042
0.048
0.042
0.048
0.042
0.056
0.020
2_
10_
0.410
0.430
0.040
MILLIMETERS
MIN
MAX
12.32
12.57
12.32
12.57
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
0.64
11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
0.50
2_
10_
10.42
10.92
1.02
Case Outlines
32Pin Package
T, U, Z
FA SUFFIX
PLASTIC TQFP PACKAGE
CASE 873A02
ISSUE A
4X
A1
32
0.20 (0.008) AB TU Z
25
T
B
AE
P
B1
DETAIL Y
17
V1
AE
DETAIL Y
4X
Z
9
0.20 (0.008) AC TU Z
S1
S
DETAIL AD
G
AB
0.10 (0.004) AC
AC TU Z
AC
BASE
METAL
F
8X
M_
0.20 (0.008)
SEATING
PLANE
SECTION AEAE
K
X
DETAIL AD
Q_
GAUGE PLANE
0.250 (0.010)
C E
541
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE AB IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS T, U, AND Z TO BE DETERMINED
AT DATUM PLANE AB.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE AC.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE AB.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.300
0.450
1.350
1.450
0.300
0.400
0.800 BSC
0.050
0.150
0.090
0.200
0.500
0.700
12_ REF
0.090
0.160
0.400 BSC
1_
5_
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.012
0.018
0.053
0.057
0.012
0.016
0.031 BSC
0.002
0.006
0.004
0.008
0.020
0.028
12_ REF
0.004
0.006
0.016 BSC
1_
5_
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
MOTOROLA
Case Outlines
52Pin Package
FA SUFFIX
PLASTIC TQFP PACKAGE
CASE 848D03
ISSUE C
4X
4X TIPS
0.20 (0.008) H LM N
0.20 (0.008) T LM N
52
X
X=L, M, N
CL
AB
40
AB
39
VIEW Y
3X VIEW
PLATING
J
B1
13
V1
0.13 (0.005)
27
14
26
BASE METAL
D
T LM
SECTION ABAB
A1
S1
A
S
4X
2
0.10 (0.004) T
H
T
SEATING
PLANE
4X
3
VIEW AA
0.05 (0.002)
W
1
2XR
R1
0.25 (0.010)
C2
GAGE PLANE
K
C1
E
Z
VIEW AA
MOTOROLA
542
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE H IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS L, M AND N TO BE DETERMINED
AT DATUM PLANE H.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE T.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE -H-.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46
(0.018). MINIMUM SPACE BETWEEN
PROTRUSION AND ADJACENT LEAD OR
PROTRUSION 0.07 (0.003).
DIM
A
A1
B
B1
C
C1
C2
D
E
F
G
J
K
R1
S
S1
U
V
V1
W
Z
1
2
3
MILLIMETERS
MIN
MAX
10.00 BSC
5.00 BSC
10.00 BSC
5.00 BSC
1.70
0.05
0.20
1.30
1.50
0.20
0.40
0.45
0.75
0.22
0.35
0.65 BSC
0.07
0.20
0.50 REF
0.08
0.20
12.00 BSC
6.00 BSC
0.09
0.16
12.00 BSC
6.00 BSC
0.20 REF
1.00 REF
0_
7_
0_
12 _ REF
5_
13 _
INCHES
MIN
MAX
0.394 BSC
0.197 BSC
0.394 BSC
0.197 BSC
0.067
0.002
0.008
0.051
0.059
0.008
0.016
0.018
0.030
0.009
0.014
0.026 BSC
0.003
0.008
0.020 REF
0.003
0.008
0.472 BSC
0.236 BSC
0.004
0.006
0.472 BSC
0.236 BSC
0.008 REF
0.039 REF
0_
7_
0_
12 _ REF
5_
13 _
MOTOROLA
SECTION 6
Quality & Reliability
Quality
The Motorola culture is a culture of quality. Throughout all
phases of product development, from defining and designing
to shipping the product, Motorola strives for total customer
satisfaction through Six Sigma and On Time Delivery
programs.
Defining Products
From the beginning, the goal of the ECLinPS family was to
be customer defined. Extensive work was done up front to
identify part types which were perfectly suited to the needs of
our customers. This definition phase ensured a level of
quality for the family in that the customer defines the product
rather than the supplier dictating product types.
Designing Products
Superior quality products start with the design, and the
design of a product starts with an IC process. Extensive work
was done with the MOSAIC III process to ensure a solid
platform for quality products. Process reliability studies were
performed to uncover any weaknesses in the initial process
so that enhancements could be made to strengthen it before
it was released to production. In addition, comprehensive
characterization and correlation work was completed on the
process to ensure the utmost in modeling parameter
accuracy.
The design of the products strictly adhered to the design
rules set forth by the process designers. Conservative,
manufacturable layout rules were followed to minimize the
performance variability due to a marginally manufacturable
product. In addition, the use of statistical modeling methods,
such as factorial and response surface techniques, in the
designing of the ICs leads to products with a reduced
sensitivity to variations in the manufacturing process.
Manufacturing Process
Through SPC and continual engineering work, the
manufacture of the MOSAIC III process is both monitored
and enhanced on a continuous basis. Statistical data is
gathered at both probe and final test through the device data
collection to monitor the distribution of a parameter to its
specification limits. In addition, final quality assurance gates
are set up to guarantee the quality of outgoing product.
Product Characterization
Products are both DC and AC characterized for all data
book environmental conditions prior to the release of the
product to production. The distributions of the parameters are
Reliability
To ensure the long term reliability of ECLinPS products,
extensive accelerated life testing is performed prior to
production release. This qualification work is performed by
Logic Reliability Engineering, an organization specifically
dedicated to monitoring and guaranteeing the quality and and
reliability of logic products. The accelerated life test consists
of the following:
Operating Life Test: 145C Mil. Std. 883
Temperature Cycle: 65C to 150C Mil. Std. 883
Pressure, Temperature, Humidity (Hermeticity)
A minimum of two lots, 250 die per lot taken from three
different waters in the lot constitute a qualification sample.
Various intermediate readouts are taken to monitor the
performance more closely. In addition, the devices are tested
beyond the specification limits to determine where and how
they will fail.
Another responsibility of the reliability group is that of
failure analysis. This failure analysis service is supported for
both internal purposes and for servicing the needs of our
customers. Analysis entails everything from simple package
examination to internal microprobing to SEM analysis of IC
structures. The results of the analysis are returned to the
customer and if the analysis suggests a potential problem
with the device the information is also passed to the internal
product groups.
RAP: Reliability Audit Program
The Reliability Audit Program (RAP) devised in March
1977 is the Motorola internal reliability audit which is
designed to assess outgoing product performance under
accelerated stress conditions. Logic Reliability Engineering
has overall responsibility for RAP, including updating its
requirements, interpreting its results, administration at
offshore locations and monthly reporting of results. These
reports are available at all sales offices. Also available is the
Reliability and Quality Handbook which contains data for all
Motorola semiconductors (BR518/D).
543
MOTOROLA
PTHB
48 HRS
PTH
96 HRS
ELECTRICAL
TEST
ELECTRICAL
TEST
PTH
ADD 48 HRS
PTH
ADD 48 HRS
ELECTRICAL
TEST
76 116 PCS
ELECTRICAL
TEST
INITIAL SEAL***
INITIAL SEAL***
TEMP CYCLE
100 CYCLES
THERMAL SHOCK
100 CYCLES
SEAL***
SEAL***
OP LIFE****
40 HOURS
ELECTRICAL
TEST
ELECTRICAL
TEST
ELECTRICAL
TEST
THERMAL SHOCK
ADD 900 CYCLES
THERMAL SHOCK
ADD 900 CYCLES
OP LIFE
ADD 210 HRS.
ELECTRICAL
TEST
ELECTRICAL
TEST
ELECTRICAL
TEST
TEMP CYCLE
ADD 1000 CYCLES
OP LIFE*****
ADD 750 HRS.
ELECTRICAL
TEST
ELECTRICAL
TEST
SCRAP
**
***
****
PTHB
15psig/121C/100% RH at rated VCC or VEE to be
performed on plastic encapsulated devices only.
Temp Cycle
Mil. Std. 883, Method 1010, Condition C, 65C to 150C
Op Life
Mil. Std. 883, Method 1005, Condition C (Power plus
Reverse Bias), TA = 145C.
Notes:
1. All standard 25C DC and functional parameters will be measured Go/NoGo at each readout.
2. Any indicated failure is first verified and then submitted to the Product Analysis Lab for detailed analysis.
3. Sampling to include all package types routinely.
4. Device types sampled will be by generic type within each digital IC product family (MECL, TTL, etc.) and will include all assembly locations
(Korea, Phillipines, Malaysia, etc.).
5. 16 hrs. PTHB is equivalent to 800 hrs. of 85C/85% RH THB for VCC 15V.
6. Only moisture related failures (like corrosion) are criteria for failure on PTHB test.
7. Special device specifications (48As) for digital products will reference 12MRM15301A as a source of generic data for any customer requiring
monthly audit reports.
MOTOROLA
544
AN1404
Application Note
5/92
545
REV 0
AN1404
VCB
Input
VC
VBB
MOTOROLA
546
AN1404
In Figure 7 the IINH of the input transistor has more than
doubled from the standard level. This increase in base
current leads to an increase in the VOL level as the collector
current must reduce to maintain the constant emitter current.
As the collector current reduces, the IR drop across the
collector load resistor reduces, thus raising the VOL level on
the QB output. Although the VOL level has shifted the overall
propagation delay has remained essentially unchanged.
Finally, when the input is switched all the way up to VCC the
VOL level no longer remains in spec as the input base current
has jumped to almost 1ma and there has been significant
degradation in the high-low propagation delay. It is apparent
that for this condition an E122 style buffer will not perform
adequately for most systems.
VCB
100E Structure
VCB
10E Structure
VCB
VC
Input A
VBB
VBB
VCC
VCC
VCB
VBB
VBB
VC
Input A
VC
VCB
Input
VCB
VCB
Input B
Input B
VCB
VBB
VBB
547
MOTOROLA
AN1404
Other Considerations
When driving ECLinPS devices with other than standard
input levels there is another phenomena that should be
considered; namely effects of non-centered switching
references on the AC performance of a device. For
non-standard input voltages the midpoint of the voltage swing
may not correspond to the internal VBB switching reference. If
this is the case the resulting AC variation should be included in
the evaluation of a design.
An input voltage swing not centered about the switching
reference will exhibit a delay skew between the two input edge
transitions. The size of this skew will be dependent on both the
voltage offset of the reference voltage and the midpoint of the
input swing and the slew rate of the input as it passes through
the threshold region. As an example for the case in which the
VIH = 0.5V and the VIL remains at 1.7V the midpoint of the
swing will be at 1.1V versus a 1.32V VBB reference. With a
typical slew rate of 1ps/mV for ECLinPS type edge rates the
rising input edge delay will be 220ps longer than normal and
the falling edge delay will be 220ps faster. This results in a
440ps skew between the two input transitions that would not
be seen for an ideal switching reference.
The only means of correcting this skew is to lower the VIL
level to recenter the swing or provide a different switching
reference for the device. The latter can be accomplished by
buffering the signal with a differential input device with one
input tied to an externally generated switching reference.
Raising the VIL level is not recommended due to the obvious
loss of low end noise margin accompanied by any such shift.
Conclusions
Simulations show that forward bias levels of 600mV on the
input transistor will keep the input transistor in the active
region and the performance of the device will not be
compromised. This forward bias voltage can be increased
with varying degrees of performance degradation to levels
somewhat higher than 600mV. Initial effects will be an
increase in the IINH current and a decrease in the output VOL
level on the QB output of the input gate. As the forward bias
increases further the propagation delays through the device
will be adversely affected.
The following example will outline the use of the table in the
appendix to analyze the potential performance of a design
using non-standard VIH levels. If a design called for the
10E112 and the 10E416 to be driven by a 0.2V input signal a
designer would want to know if these two devices would
perform to specifications under these conditions. From the
table the worst case collector voltage VC would be 1.05V and
0.0V respectively. Subtracting these values from 0.2V yields
forward bias voltages of 850mV and 200mV respectively.
From this information the designer would conclude that the
10E416 will function with no problems however the 10E112
could suffer performance degradation under these same
conditions.
The device information contained in the appendix of this
document will provide designers with all of the information
necessary to evaluate the input transistor forward bias
conditions for all of the ECLinPS devices for different input
voltages. With these numbers and the information provided in
this document designers will be able to make informed
decisions about their designs to meet the performance
desired at an acceptable level of risk.
MOTOROLA
548
AN1404
Appendix
Device
Input
Input Structure
VC (10E Typical)
(V)
VC (100E Typical)
(V)
E016
E101
E104/107
All
All
Dna
INT
EF
EXT
0.80
0.15
0.95
0.90
0.25
1.05
0.80
0.10
0.90
0.90
0.20
1.00
E111
E112
Dnb
All
Dn
EN/
SG
INT
EXT
INT
0.50
0.80
0.95
0.80
0.60
0.90
1.05
0.90
1.20
0.80
0.90
0.80
1.30
0.90
1.00
0.90
E116
E122
E131
All
All
D
Other
EXT
EXT
INT
SG
0.95
0.95
0.90
0.50
1.05
1.05
1.00
0.60
0.90
0.90
0.90
1.20
1.00
1.00
1.00
1.30
E141
E142
E143
E150
All
All
All
Dn
INT
INT
INT
EXT
0.80
0.80
0.80
0.95
0.90
0.90
0.90
1.05
0.80
0.80
0.80
0.90
0.90
0.90
0.90
1.00
E151
E154
E155
Other
All
All
All
INT
INT
INT
INT
0.80
0.80
0.80
0.80
0.90
0.90
0.90
0.90
0.80
0.80
0.80
0.80
0.90
0.90
0.90
0.90
All
Dn
SEL
Dn
INT
EXT
INT
EXT
0.80
0.95
0.80
0.95
0.90
1.05
0.90
1.05
0.80
0.90
0.80
0.90
0.90
1.00
0.90
1.00
E160
SEL
R, CLK
Other
INT
SG
INT
0.80
0.50
0.80
0.90
0.60
0.90
0.80
1.20
0.80
0.90
1.30
0.90
E163
E164
E166
E167
All
All
All
All
INT
INT
INT
INT
0.80
0.80
0.80
0.80
0.90
0.90
0.90
0.90
0.80
0.80
0.80
0.80
0.90
0.90
0.90
0.90
E171
E175
E195
E196
All
All
All
All
INT
INT
INT
INT
0.80
0.80
0.80
0.80
0.90
0.90
0.90
0.90
0.80
0.80
0.80
0.80
0.90
0.90
0.90
0.90
E212
E241
E256
E336
All
All
All
All
INT
INT
INT
INT
0.80
0.80
0.80
0.80
0.90
0.90
0.90
0.90
0.80
0.80
0.80
0.80
0.90
0.90
0.90
0.90
E337
E404
E416
E431
All
All
All
All
INT
EF
EF
INT
0.80
0.00
0.00
0.80
0.90
0.00
0.00
0.90
0.80
0.00
0.00
0.80
0.90
0.00
0.00
0.90
E451
E452
E457
All
All
Dn
SEL
INT
INT
EF
INT
0.80
0.80
0.00
0.80
0.90
0.90
0.00
0.90
0.80
0.80
0.00
0.80
0.90
0.90
0.00
0.90
E156
E157
E158
INT = Internal Gate; EXT = External Gate; EF = Emitter Follower Input; SG = Series Gated Input
549
MOTOROLA
AN1404
0.25
V(IN)
0.5
V(Q)
V(QB)
0.75
V(VBB)
VOLTAGE
1.0
1.25
1.5
1.75
2.0
2.25
0
2000
4000
TIME
0.0
V(IN)
0.25
V(Q)
V(QB)
0.5
V(VBB)
VOLTAGE
0.75
1.0
1.25
1.5
1.75
2.0
0
2000
4000
TIME
MOTOROLA
550
AN1404
0.0
V(IN)
0.25
V(Q)
V(QB)
0.5
V(VBB)
VOLTAGE
0.75
1.0
1.25
1.5
1.75
2.0
0
2000
4000
TIME
0.0
V(IN)
0.25
V(Q)
V(QB)
0.5
V(VBB)
VOLTAGE
0.75
1.0
1.25
1.5
1.75
2.0
0
2000
4000
TIME
551
MOTOROLA
AN1404
0.0
V(IN)
0.25
V(Q)
V(QB)
0.5
V(VBB)
VOLTAGE
0.75
1.0
1.25
1.5
1.75
2.0
0
2000
4000
TIME
MOTOROLA
552
AN1405
Application Note
7/96
553
REV 1
AN1405
SKEW DEFINITIONS
The skew introduced by logic devices can be divided into
three parts: duty cycle skew, output-to-output skew and
part-to-part skew. Depending on the specific application, each
of the three components can be of equal or overriding
importance.
OUTa
OUTb
OUTc
OUTPUT-TO-OUTPUT SKEW
OUT
TPLH
TPLH
PWhi
PWlo
fin = fout
MOTOROLA
554
AN1405
designer will need the entire commercial temperature range, a
portion of this range will need to be considered. Therefore, a
part-to-part skew specified for a single temperature is of little
use, especially if the temperature coefficient of the
propagation delay is relatively large.
For designs whose clock distribution networks lie on a
single board which utilizes power and ground planes an
assumption of non-varying power supplies would be a valid
assumption and a specification limit for a single power supply
would be valuable. If, however, various pieces of the total
distribution tree will be on different boards within a system
there is a very real possibility that each device will see different
power supply levels. In this case a specification limit for a fixed
VCC will be inadequate for the design of the system. Ideally the
data sheets for clock distribution devices should include
information which will allow designers to tailor the skew
specifications of the device to their application environment.
SYSTEM ADVANTAGES OF ECL
Skew Reductions
ECL devices provide superior performance in all three
areas of skew over their TTL or CMOS competitors. A skew
reducing mechanism common to all skew parameters is the
faster propagation delays of ECL devices. Since, to some
extent, all skew represent a percentage of the typical delays
faster delays will usually mean smaller skews. ECL devices,
especially clock distribution devices, can be operated in either
single-ended or differential modes. To minimize the skew of
these devices the differential mode of operation should be
used, however even in the single-ended mode the skew
performance will be significantly better than for CMOS or
TTL drivers.
IN
VBBlo
VBBnom
OUT
DELAYlo
DELAYnom
555
MOTOROLA
AN1405
1.20
1.05
PROPAAGATION DELAY (NORMALIZED)
1.04
CMOS/TTL
1.03
1.02
1.01
1.00
ECL
0.99
0.98
0.97
0.96
1.15
CMOS/TTL
1.10
ECL
1.05
1.00
0.95
0.94
0.98
1.02
1.06
1.10
20
40
60
80
100
TEMPERATURE (C!)
E111
Differential Interconnect
Q0
MOTOROLA
CLKa
D
Q8
CLKb
CLKa
CLKb
556
AN1405
E211
Q0
Q8
BACKPLANE
E111
Q5
Q0
Q8
15
I CC(ma)
CMOS
10
5
ECL
20
40
60
80
100
FREQUENCY (MHz)
557
MOTOROLA
AN1405
driving the clock inputs of the logic. As a result the ECL edges
need to be matched with the TTL edges as pictured in Figure 9.
H641
Q0
ECL
TTL
Q0
BACKPLANE
E111
Q8
H641
Q8
Q0
ECL
TTL
Q8
E111
Q0
DELAY
TTL
Q0
Q8
DELAY
Q8
BACKPLANE
E111
H641
Q0
ECL
TTL
Q8
MOTOROLA
558
AN1405
REFa
REFb
OUTb
OUTa
DEVICE SKEW
SYSTEM SKEW
Conclusion
The best way to maximize the performance of any
synchronous system is to spend the entire clock period
performing value added operations. Obviously any portion of
the clock period spent idle due to clock skew limits the
potential performance of the system. Using ECL technology
devices in clock distribution networks will minimize all aspects
of skew and thus maximize the performance of a system.
Unfortunately the VLSI world is not yet ECL clock based so
that the benefits of a totally ECL based distribution tree cannot
be realized for many systems. However there are methods of
incorporating ECL into the intermediate levels of the tree to
significantly reduce the overall skew. In addition the system
designers can utilize their new found knowledge to
incorporate ECL compatible clocks on those VLSI chips of
which they have control while at the same time pressuring
other VLSI vendors in doing the same so that future designs
can enjoy fully the advantages of distributing clocks with ECL.
559
MOTOROLA
AN1406
Application Note
Prepared by
Cleon Petty
Todd Pearson
ECL Applications Engineering
This application note provides detailed information on
designing with Positive Emitter Coupled Logic (PECL)
devices.
9/92
560
REV 0
AN1406
Introduction
PECL, or Positive Emitter Coupled Logic, is nothing more
than standard ECL devices run off of a positive power supply.
Because ECL, and therefore PECL, has long been the black
magic of the logic world many misconceptions and
falsehoods have arisen concerning its use. However, many
system problems which are difficult to address with TTL or
CMOS technologies are ideally suited to the strengths of ECL.
By breaking through the wall of misinformation concerning the
use of ECL, the TTL and CMOS designers can arm
themselves with a powerful weapon to attack the most difficult
of high speed problems.
It has long been accepted that ECL devices provide the
ultimate in logic speed; it is equally well known that the price
for this speed is a greater need for attention to detail in the
design and layout of the system PC boards. Because this
requirement stems only from the speed performance aspect of
ECL devices, as the speed performance of any logic
technology increases these same requirements will hold. As
can be seen in Table 1 the current state-of-the-art TTL and
CMOS logic families have attained performance levels which
require controlled impedance interconnect for even relatively
short distances between source and load. As a result system
designers who are using state-of-the-art TTL or CMOS logic
are already forced to deal with the special requirements of
high speed logic; thus it is a relatively small step to extend their
thinking from a TTL and CMOS bias to include ECL devices
where their special characteristics will simplify the design
task.
Table 1. Relative Logic Speeds
Logic
Family
Typical Output
Rise/Fall
10KH
1.0ns
ECLinPS
400ps
FAST
2.0ns
FACT
1.5ns
561
MOTOROLA
AN1406
ECL Serial Data
>200MHz
Serial/Parallel
Conversion
Low Frequency
Information Processing
Parallel/Serial
Conversion
MOTOROLA
562
AN1406
specialized functions for clock distribution are available from
Motorola (MC10/100E111, MC10/100E211, MC10/100EL11).
Care must be taken that all of the skew gained using ECL for
clock distribution is not lost in the process of translating
into CMOS/TTL levels. To alleviate this problem the
MC10/100H646 can be used to translate and fanout a
differential ECL input signal into TTL levels. In this way all of
the fanout on the backplane can be done in ECL while the
fanout on each card can be done in the CMOS/TTL levels
necessary to drive the logic.
Figure 2 illustrates the use of specialized fanout buffers to
design a CMOS/TTL clock distribution network with minimal
skew. With 50ps output-to-output skew of the MC10/100E111
and 1ns part-to-part skew available on the MC10/100H646 or
MC10/100H641, a total of 72 or 81 TTL clocks, respectively,
can be generated with a worst case skew between all outputs
of only 1.05ns. A similar distribution tree using octal CMOS or
TTL buffers would result in worst case skews of more than
6ns. This 5ns improvement in skew equates to about 50% of
the up/down time of a 50MHz clock cycle. It is not difficult to
imagine situations where an extra 50% of time to perform
necessary operations would be either beneficial or even a life
saver. For more information about using ECL for clock
distribution, refer to application note AN1405/D ECL Clock
Distribution Techniques.
PartPart
Skew = 1ns
OutputOutput
Skew = 50ps
E111
Differential ECL
Differential
ECL Input
H641
TTL
Outputs
1 of 9
H641
TTL
Outputs
9 of 9
563
MOTOROLA
AN1406
MECL to PECL DC Level Conversion
Although using ECL on positive power supplies is feasible,
as with any high speed design there are areas in which special
attention should be placed. When using ECL devices with
positive supplies the input output voltage levels need to be
translated. This translation is a relatively simple task. Since
these levels are referenced off of the most positive rail, VCC,
the following equation can be used to calculate the various
specified DC levels for a PECL device:
PECL Level = VCCNEW |Specification Level|
As an example, the VOHMAX level for a 10H device operating
with a VCC of 5.0V at 25C would be as follows:
PECL Level = 5.0V |0.81V|
PECL Level = (5.0 0.81)V = 4.19V
The same procedure can be followed to calculate all of the DC
levels, including VBB for any ECL device. Table 2 at the bottom
of the page outlines the various PECL levels for a VCC of 5.0V
for both the 10H and 100K ECL standards. As mentioned
earlier any changes in VCC will show up 1:1 on the output DC
levels. Therefore any tolerance values for VCC can be
transferred to the device I/0 levels by simply adding or
subtracting the VCC tolerance values from those values
provided in Table 2.
100E Characteristics
25C
85C
0 to 85C
Min
Max
Min
Max
Min
Max
Min
Max
Unit
VOH
1.02/3.98
0.84/4.16
0.98/4.02
0.81/4.19
0.92/4.08
0.735/4.265
1.025/3.975
0.880/4.120
VOL
1.95/3.05
1.63/3.37
1.95/3.05
1.63/3.37
1.95/3.05
1.600/3.400
1.810/3.190
1.620/3.380
VOHA
1.610/3.390
VOLA
1.035/3.965
VIH
1.17/3.83
0.84/4.16
1.13/3.87
0.81/4.19
1.07/3.93
0.735/4.265
1.165/3.835
0.880/4.120
VIL
1.95/3.05
1.48/3.52
1.95/3.05
1.48/3.52
1.95/3.05
1.450/3.550
1.810/3.190
1.475/3.525
VBB
1.38/3.62
1.27/3.73
1.35/3.65
1.25/3.75
1.31/3.69
1.190/3.810
1.380/3.620
1.260/3.740
MOTOROLA
564
AN1406
ZO
ZO
Rpd
Rt = ZO
VEE
Rt
VTT
Parallel Termination
VCC
Rs
Rpd
ZO
ZO
R1
R2
RS = ZO
VEE
VEE
Series Termination
565
MOTOROLA
AN1406
Let VCC = 4.75V and VTT = VCC 2.0V = 2.75V
Therefore:
R2 = 119 and R1 = 86 thus:
IOHmax = 23mA and IOLmin = 3.0mA
Plugging in these values for the equations at the other extreme
for VCC = 5.25V yields:
VTT = 3.05V, IOHmax = 28mA and IOLmin = 5.2mA
Although the output currents are slightly higher than nominal,
the potential for performance degradation is much less and
the results of any degradation present will be significantly less
dramatic than would be the case when the output emitter
follower is cutoff. Again in most cases the component
manufactures will provide devices with typical output levels;
typical levels significantly reduces any chance of problems.
However it is important that the system designer is aware of
where any potential problems may come from so they can be
dealt with during the initial design.
ZO
Rt
Rpd
VEE
Rt = ZO
Standard Twisted Pair Termination
VTT
Rt
Rt = ZO/2
ZO
Rt
where VOH, VOL, VEE and VTT are PECL voltage levels.
R2
Plugging in the various values for VCC will show that the VTT
tracks with VCC at a rate of approximately 0.7:1. Although this
rate is approaching ideal it would still behoove the system
designer to ensure there are no potential situations where the
output emitter follower could become cutoff. The calculations
are similar to those performed previously and will not be
repeated.
MOTOROLA
VTT
R1 + R2 = ZO/2
R3 = R1 (VTT VEE)/(VOH + VOL 2VTT)
VTT = (R3{VOH + VOL} + R1{VEE})/(R1 + 2R3)
Rt
ZO
R3
Rt = ZO/2
VEE
566
AN1406
**
**
CMOS
Sub System
TTL
Sub System
System
+5.0V
CMOS/TTL GROUND PLANE
PECL +5.0V PLANE
System
Ground
**
*
ECL
Sub System
Conclusion
The use of ECL logic has always been surrounded by
clouds of misinformation; none of those clouds have been
thicker than the one concerning PECL. By breaking through
this cloud of misinformation the traditional CMOS/TTL
designers can approach system problems armed with a
complete set of tools. For areas within their designs which
require very high speed, the driving of long, low impedance
lines or the distribution of very low skew clocks, designers can
take advantage of the built in features of ECL. By incorporating
this ECL logic using PECL methodologies this inclusion need
not require the addition of more power supplies to
unnecessarily drive up the cost of their systems. By following
the simple guidelines presented here CMOS/TTL designers
can truly optimize their designs by utilizing ECL logic in areas
in which they are ideally suited. Thus bringing to market
products which offer the ultimate in performance at the lowest
possible cost.
567
MOTOROLA
AN1406
5.0V
5.0V GND
Driver
Receiver
MOTOROLA
568
AN1503
Application Note
ECLinPS
I/O SPICE
Modeling Kit
Prepared by
Todd Pearson
ECLinPS Applications Engineering
10/91
569
REV 0
AN1503
MOTOROLA
570
IN
VBB
Rise/Fall
Diff
S.E.
1.325V
AN1503
SPICE Parameter Information
In addition to the schematics a listing of the SPICE
parameters for the transistors referenced in the schematics is
included. These parameters represent a typical device of the
given transistor size. Varying these parameters will obviously
affect the voltage levels, the propagation delays, and the
transition times of a device. For the type of modeling for which
this information is intended the actual propagation delay of a
device will not be modelled, as a result variations in this
parameter are meaningless. Furthermore the voltage levels
and transition times can be more easily varied by other means.
This will be addressed in the next section.
All of the resistors referenced in the schematics are
polysilicon resistors and thus there is no need to provide
parasitic capacitance models for these resistors in the netlist.
The only devices needed in the SPICE netlist are illustrated in
the schematics.
modeling Information
The bias driver schematics are not included as they were
deemed unnecessary for interconnect simulation, in addition
their use also results in a relatively large increase in
simulation time. Alternatively the internal reference voltages
(VBB and VCS) should be driven with ideal constant voltage
sources. The following table summarizes the voltage levels for
these internal references as well typical input voltage
parameters.
Parameter
VBB
VCS
VIH
VIL
Rise/Fall
Typical Level
Worst Case
1.325V
VEE + 1.33V
0.9V (10E); 0.95V (100E)
1.75V (10E); 1.7V (100E)
400ps (20% 80%)
Data Book
50mV
Data Book
Data Book
Data Book
571
MOTOROLA
AN1503
VCC
PKG
R1
250
R2
270
R3
270
Q4
TN6
Q5
TN6
IN
Q1
TN6
PKG
Rpd
50 k
Q2
TN6
VBB
QB
ESD
PROTECTION
CIRCUITRY
Q3
TN6
VCS
Ig = 1.5 mA
Ief = 0.75 mA
R4
325
VEE
Q6
TN6
Q7
TN6
Q8
TN6
Q9
TN6
R5
650
R6
650
VCC
PKG
R1
300
R2
300
STYLE A
TEMP COMP
NETWORK
Q4
TNECLiPS
Q5
TNECLiPS
IN
Q1
TN13p5
Q2
TN13p5
VBB
PKG
PKG
QB
VCS
Ig = 3.5 mA
R3
130
VEE
MOTOROLA
572
AN1503
VCC
PKG
R1
150
R2
150
STYLE B
TEMP COMP
NETWORK
Q6
TNECLiPS
Q4
TNECLiPS
Q7
TNECLiPS
Q5
TNECLiPS
IN
Q1a
TN13p5
Q1b
VCS
Q2a
TN13p5
Q2b
VBB
PKG
Qa
PKG
Qb
PKG
QaB
PKG
QbB
Q3a
TN13p5
Q3b
Ig = 7.0 mA
R3
65
VEE
PKG
R1
100
R2
100
STYLE C
TEMP COMP
NETWORK
R3
60
R4
60
Q5a
IN
Q1c
Q1b
Q1a
TN13p5
Q2a
TN13p5
Q2b
Q2c
Q5b
TNECLiPS
VBB
PKG
BUSB
To input gate
VCS
Q3c
Q3b
Q3a
TN13p5
RESISTOR TC = 0.405M, 2.2U
Ig = 10.5 mA
R3
43
VEE
573
MOTOROLA
AN1503
VCC
PKG
R1
150
R2
150
STYLE B
TEMP COMP
NETWORK
Q4
TNECLiPS
Q5
TNECLiPS
Q2a
TN13p5
Q1a
TN13p5
Q1b
IN
VCS
Q3b
Q2b
VBB
PKG
PKG
QB
Q3a
TN13p5
RESISTOR TC = 0.405M, 2.2U
Ig = 7.0 mA
R3
65
VEE
VCC
PKG
R1
100
R2
100
STYLE D
TEMP COMP
NETWORK
Q4
TNECLiPS
Q5
TNECLiPS
IN
Q1c
Q1a
TN13p5
Q1b
VCS
Q3c
Ig = 10.5 mA
Q2a
TN13p5
Q3b
Q2b
Q2c
VBB
PKG
PKG
QB
Q3a
TN13p5
RESISTOR TC = 0.405M, 2.2U
R3
43
VEE
MOTOROLA
574
AN1503
Style A
RTC
180
Style B
RTC
80
QT1
TN4
QT2
TN4
QT1
TN4
QT2
TN4
Style C
RTC
90
Style D
RTC
60
QT1
TN4
QT1
TN4
QT2
TN4
RPKG2
750
RPKG3
0.2
EXT
INT
LPKG1
3.5 nH
LPKG2
3.5 nH
CPKG
1.5 pF
RPKG2
750
RPKG3
0.1
EXT
INT
LPKG1
1.5 nH
LPKG2
1.5 nH
CPKG
0.8 pF
575
MOTOROLA
AN1503
VCC
INPUT
DESD1
CBVCC
RB
185
QESD
1
TN6
TO INPUT
TRANSISTOR
INPUT
QESD
2
TN6
DESD2
CBSUB
RESISTOR TC = 0.405M, 2.2U
VEE
VEE
50
6 LINE
50
3 LINE
TYPICAL INPUT
(FIG. 1)
50
10 LINE
50
TYPICAL OUTPUT
(FIG. 2)
VTT
TYPICAL INPUT
(FIG. 1)
TYPICAL INPUT
(FIG. 1)
MOTOROLA
576
AN1503
APPENDIX
Schematic/ECLinPS Device Cross Reference
Typical Input
Differential Input
ECLinPS
ECLinPS Lite
EL01, EL12, EL31, EL32 (R), EL33 (R),
EL35, EL51 (D, R)
25 Bus Outputs
2x Current Output
ECLinPS
E112, E212
E336, E337
ECLinPS Lite
EL12*
3x Current Output
E416
Standard Output
All Others
* These ECLinPS Lite devices inputs feed directly into the output buffer.
577
MOTOROLA
AN1503
SPICE Transistor Model Parameters (cont.)
**** 1.75u x 6.0u emitter
.MODEL TN6
NPN
+ ( IS= 8.56E18 BF=120 NF=1 VAF=30 IKF=10.5mA
+ ISE= 4.48E16 BR=10 NE=2 VAR=5 IKR=922uA
+ IRB= 13.2uA
RB= 291.4 RBM= 95.0 RE= 13.3 RC= 62.7
+ CJE= 29.9fF VJE= .9 MJE= .4
XTB= 0.73
+ CJC= 31.2fF VJC= .67 MJC= .32
XCJC= .3
+ CJS= 60.9fF VJS= .6 MJS= .4
FC= .9
+ TF= 8pS
TR= 1nS XTF= 10 VTF= 1.4V ITF= 27.6mA
+ ISC= 0 EG=1.11 XTI= 4.0 PTF=0 KF=0 AF=1 NR=1 NC=2)
*
**** 1.75u x 13.5u emitter
.MODEL TN13P5
NPN
+ ( IS= 2.09E17 BF=120 NF=1 VAF=30 IKF=25.7mA
+ ISE= 1.09E15 BR=10 NE=2 VAR=5 IKR=2.25mA
+ IRB= 32.2uA
RB= 122.6 RBM= 42.2 RE= 5.44 RC= 32.8
+ CJE= 67.4fF VJE= .9 MJE= .4
XTB= 0.73
+ CJC= 53.8fF VJC= .67 MJC= .32
XCJC= .3
+ CJS= 103fF VJS= .6 MJS= .4
FC= .9
+ TF= 8pS
TR= 1nS XTF= 10 VTF= 1.4V ITF= 67.5mA
+ ISC= 0 EG=1.11 XTI= 4.0 PTF=0 KF=0 AF=1 NR=1 NC=2)
*
****ECLinPS Lite ESD Diodes
.MODEL CBVCC D
+ (IS= 1.00E15 CJO= 527fF Vj= 0.545 M= 0.32 BV= 14.5 IBV= 0.1E6
+ XTI= 5 TT=1nS)
.MODEL CBSUB D
+ (IS= 1.00E15 CJO= 453fF TT= 1nS)
MOTOROLA
578
AN1504
Application Note
11/91
579
REV 0
AN1504
Metastability Theory
A bistable device such as a flip-flop has two stable output
states: the 1 or high state and the 0 or low state. When the
manufacturers specified set-up and hold times are observed
the flip-flop will achieve the proper output state (Figure 3).
However if the set-up and hold times are violated the device
may enter a metastable state, thereby increasing the
propagation delay, as indicated by the output response shown
in Figure 4.
To better understand flip-flop metastability, the operation of
a typical ECLinPS D flip-flop is reviewed. The schematic of a
D flip-flop is shown in Figure 5.
SYSTEM 1
SYSTEM 1
OUTPUT
SYSTEM 1
CLOCK
DATA
SYSTEM 2 INPUT
D-FLIP FLOP
SYSTEM 2
SYSTEM 2
CLOCK
CLOCK
SYSTEM 1
SYSTEM 1
CLOCK
SYSTEM 1
OUTPUT
DATA
D-FLIP FLOP
SYSTEM 2
CLOCK
DATA
SYSTEM 2 INPUT
D-FLIP FLOP
SYSTEM 2
CLOCK
CLOCK
TD DELAY
MOTOROLA
580
AN1504
CLOCK
VOUT CASE 1
DATA: CASE 1
VOUT CASE 2
DATA: CASE 2
VOUT CASE 3
DATA: CASE 3
TSU
TCLK
THD
Figure 2. Timing Relationships Between Data and Clock Signals for a D Flip-Flop
28.6300 NS
31.1300 NS
33.6300 NS
581
MOTOROLA
AN1504
28.6300 NS
31.1300 NS
33.6300 NS
STOP = 31.5600 NS
VCC
MASTER LATCH
DATA
REGENERATIVE
DATA
SLAVE
LATCH
REGENERATIVE
Q
Q
DATA
RESET
DATA
SET
CLOCK
CLOCK
VCS
VEE
MOTOROLA
582
AN1504
Metastable Equations
PROPAGATION DELAY
TW(TD)
TD
TP
TMAX
T0
TF
DATA
INPUT
TIME
(eqt 1)
DATA SIGNAL
DATA SIGNAL
CLOCK SIGNAL
CLOCK SIGNAL
TA
T0
TMAX
TIME
TMAX TA T0
TIME
583
MOTOROLA
AN1504
Test Circuitry For Metastable Evaluation
Plotting log MTBF versus t yields a line with slope 1/, and
log MTBF intercept of log(2*fc*fd*TP). Thus, the test circuit
must accept the clock and data input frequencies as a function
of t and yield MTBF as an output. The circuit configuration
shown in Figure 8 fulfills these criteria.
(eqt 2)
Clock Frequency
Data Frequency
MTBF = 1/(2*fC*fD*TP*10(t)/)
(eqt 4)
(eqt 3)
(VBB + 0.15 V)
DUT
10E451
HP
8082A
D1
D
Q
D1
DUT
Q
HP
8082A
CLK 1
D2
Q1
Q2
D2
Q
HP 5335A
COUNTER
10E131
10E101
10E107
CLK 2
CLK 3
COUNTER
CLK 2
TRIG
Q
HP
8082A
Q
ADJUSTABLE DELAY
(VBB 0.15 V)
COMPARATOR
COUNTER-SET
MOTOROLA
584
AN1504
Pulse generator #1 (PG 1) supplies the data signal to the
DUT. To ensure asynchronous signals between the DUT data
and clock signals, a separate pulse generator, PG2, provides
the clock signal to the DUT. Generator PG2 also provides the
clocking signal to the comparator circuitry via its inverting
output terminal. Pulse generator PG3 supplies the clock
signals to the E451 portion of the comparator section. To
increase the probability of the DUT entering the metastable
state the DUT data frequency is set at 1.33 times the DUT
clock frequency. The value of t is the delay between the
noninverting clock signals for the DUT and the E451. Finally,
the inverting terminal of PG2 supplies the clock signal for the
counter-set circuitry.
LOG MTBF
0
2
4
6
8
2e9
3e9
4e9
DELAY (SEC)
5e9
VOH
VBB
VOL
Shifted (V)
10E
100E
10E
100E
VIL
1.75
1.70
+0.25
+0.30
VIH
0.90
0.95
+1.10
+1.05
VBB
1.30
1.30
+0.70
+0.70
VCC
0.00
0.00
+2.00
+2.00
VEE
5.20
4.50
3.20
2.50
VHmeta
1.15
1.15
+0.85
+0.85
VLmeta
1.45
1.45
+0.55
+0.85
Results
An example of using a log MTBF versus t plot to determine
is shown in Figure 10.
Motorola 10E431
125 psec
Motorola 10E151
185 psec
Motorola 10E131
200 psec
Motorola 10H131
718 psec
Signetics 100131
890 psec
Signetics 100151
1172 psec
National 100131
1594 psec
Example
As an example, assume the system configuration shown in
Figure 11, in which the output from System 1 is to be
synchronized to System 2 using a 10E151 D flip-flop.
Further, the equivalent output signal for System 1 is 75 MHz
whereas the clock frequency for System 2, as well as the
synchronizing element, is 100 MHz. Under these conditions
the data and clock inputs to the D flip-flop are asynchronous
and the system designer must consider the possibility of the D
flip-flop entering the metastable state. Therefore the system
designer must determine how long the flip-flop will remain in
the metastable region in order to decide when the data at the
output of the flip-flop will attain a defined state and can be
clocked into System 2.
585
MOTOROLA
AN1504
Thus for an MTBF of 5 years the designer should delay the
clocking of the data from the output of the flip-flop into System
2 by 3.63 nsec.
Conclusion
References
t = TD TP
SYSTEM 1
75 MHz
SYSTEM 1
OUTPUT
SYSTEM 1
CLOCK
DATA
SYSTEM 2 INPUT
D-FLIP FLOP
100 MHz
SYSTEM 2
SYSTEM 2
CLOCK
CLOCK
MOTOROLA
586
AN1568
Application Note
Interfacing Between
LVDS and ECL
Prepared by
Andrea Diermeier
Motorola Logic Engineering
5/96
587
REV 0
AN1568
LVDS Levels
LVDS
100
Z = 50
ECL levels
In ECL circuits all signal levels are related to VCC supply
rail. Traditional ECL designs are supplied with negative
voltages with VCC = GND.
Today several applications use ECL devices in the PECL
mode. PECL Positive ECL is nothing more than supplying
any ECL divide with a positive power supply (+5V).
With the trend to low voltage systems a new generation of
ECL circuitry has been developed. The Low Voltage ECL
devices (LVECL) work from a 3.3V power supply either as
negative supplied or more popular from standard VCC =
+3.3V and VEE = GND as LVPECL.
100E(L) type output DC levels for the different supply
levels are shown in Table 2 on page 589.
PECL
LVPECL
LVDS
ECL
Parameter
Min
Max
Max
Unit
Condition
1374
mV
RL = 100
mV
RL = 100
mV
RL = 100
Transmitter
VOH
1474
VOL
VPP
250
400
VOS
1125
1275
925
1025
150
250
mV
Receiver
MOTOROLA
2400
+100
100
100
588
2000
mV
+100
mV
mV
AN1568
Table 2. MC100Exxx/MC100ELxx (TA = 085C)
Symbol
LVPECL1
Parameter
PECL2
ECL
Unit
VCC
+3.3
+5.0
GND
VEE
GND
GND
VOH
2.275
3.975
1.030
VOH
2.345
4.045
0.955
VOH
2.420
4.120
0.880
VOL
1.490
3.190
1.810
VOL
1.595
3.295
1.705
1.680
3.380
1.620
VOL
Maximum Output LOW Level
1. VCC assumed 3.3V. All levels vary 1:1 with VCC.
2. VCC assumed 5V. All levels vary 1:1 with VCC.
Interfacing
R1
Z = 50
LVDS
R1
10pF
ECL
100
Z = 50
10pF
R2
VEE
VCC
100k
Z = 50
Examples:
VCC = 5V, VEE = GND:
k
10pF
ECL
100
Z = 50
VBB
10pF
1k
1k
R1 = 1.2 k R2 = 3.4
R1 = 680 R2 = 1 k.
R2
589
MOTOROLA
AN1568
Interfacing LVPECL to LVDS in thevenin equation
3.3V
3.3V
3.3V
R1
270
10pF
Z = 50
3.3V
R1
270
R1
R1
Z
LVDS
ECL
100
Z = 50
ECL
Z
RT
10pF
R2
75
RT
3.3V
Vopp
R2
A
R2
75
B
Vipp
R2
VEE
B
R3
100k
Z = 50
10pF
LVDS
ECL
50
50
1k
R3
Z = 50
VOS=
1.2V
10pF
LVDS
1k
VTT
B:
Equation 3
MOTOROLA
VIL > 0 V
Calculations give nonstandard resistor values. When
choosing resistors off the shelf it should be considered to
avoid a cutoff condition also under worst case supply voltage.
Example:
For 50 controlled impedance lines R1 = 120, R2 =33
and R3=51.
For any other controlled impedance line the calculation of
the resistive divider is done according to Equation 1,
Equation 2 and Equation 3.
590
AN1568
Interfacing LVPECL to LVDS with unterminated
transmission line
Unterminated lines can be used for very short
interconnects. For details about recommended maximum
unterminated line length, see Motorolas High Performance
ECL Data Book (DL140/D), chapter 4 System
Interconnects.
3.3V
3.3V
ECL
5V
5V
R1
R1
R1
Z
A
R1
ECL
LVDS
3.3V
Vopp
Z
R2
A
B
R2
Vipp
R2
R2
LVDS
R3
Equation 5
Equation 6
ECL
Z = 50
LVEL17
1k
VIL > 0 V
Z = 50
100
Equation 4
3.3V
LVDS
R3
Examples:
Z= 50
or
Z= 50
R1 = 82
R2 = 100
R3 = 33
R1 = 82
R2 = 82
R3 = 47
591
MOTOROLA
AN1568
Interfacing from PECL to LVDS with unterminated lines
As described in LVPECL interfacing unterminated lines
can be used for very short interconnections.
E.g. the resistors can be R1 = 330, R2 = 150.
5V
3.3V
5V5%
3.3V
ECL
Z = 50
R1
LVDS
LVEL17
100
Z = 50
R1
R2
LVDS
1k
R2
3.3V
LVPECL
Interface
LVPECL to LVDS
MC100LVEL90
MC100EL90
ECL
LVDS
LVPECL
3.3V, 4.5V or
5.2V
3.3V, 4.5V or
5.2V
3.3V
3.3V
Z = 50
LVDS
LVEL91
100
LVEL91
Z = 50
3.3V,
EL91: 4.5V, 5.2V
3.3V, 4.5V or
5.2V
MOTOROLA
592
7/1/96
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Future Electronics . . . . . . . . . . . . (410)2900600
Hamilton/Hallmark . . . . . . . . . . . (410)7203400
Time Electronics . . . . . . . . . . . 1800789TIME
PENSTOCK . . . . . . . . . . . . . . . . . (410)2903746
Wyle Electronics . . . . . . . . . . . . . (410)3124844
Hanover
Hamilton/Hallmark . . . . . . . . . . . (407)6573300
PENSTOCK . . . . . . . . . . . . . . . . . (407)6721114
FAI . . . . . . . . . . . . . . . . . . . . . . . . . (404)4474767
Time Electronics . . . . . . . . . . . 1800789TIME
Wyle Electronics . . . . . . . . . . . . . (404)4419045
COLORADO
Lakewood
Denver
Arrow/Schweber Electronics . . .
FAI . . . . . . . . . . . . . . . . . . . . . . . . .
Future Electronics . . . . . . . . . . . .
Hamilton/Hallmark . . . . . . . . . . . .
Newark . . . . . . . . . . . . . . . . . . . . .
PENSTOCK . . . . . . . . . . . . . . . . .
Wyle Electronics . . . . . . . . . . . . .
Sierra Madre
Newark . . . . . . . . . . . . . . . . . . . . . (805)4491480
FAI . . . . . . . . . . . . . . . . . . . . . . . . . (602)7314661
Future Electronics . . . . . . . . . . . . (602)9687140
Hamilton/Hallmark . . . . . . . . . . . . . (602)4143000
Wyle Electronics . . . . . . . . . . . . . (602)8047000
Arrow/Schweber Electronics . . .
FAI . . . . . . . . . . . . . . . . . . . . . . . . .
Future Electronics . . . . . . . . . . . .
Wyle Laboratories Corporate . . . .
Wyle Electronics . . . . . . . . . . . . .
GEORGIA
Atlanta
593
Newark . . . . . . . . . . . . . . . . . . . . . (410)7126922
MOTOROLA
7/1/96
Bolton
Future Corporate . . . . . . . . . . . . . (508)7793000
Burlington
PENSTOCK . . . . . . . . . . . . . . . . . (617)2299100
Wyle Electronics . . . . . . . . . . . . . (617)2719953
Peabody
Time Electronics . . . . . . . . . . . 1800789TIME
Hamilton/Hallmark . . . . . . . . . . . (508)5329893
Woburn
Newark . . . . . . . . . . . . . . . . . . . . . (617)9358350
MICHIGAN
Detroit
FAI . . . . . . . . . . . . . . . . . . . . . . . . . (313)5130015
Future Electronics . . . . . . . . . . . . (616)6986800
Grand Rapids
Newark . . . . . . . . . . . . . . . . . . . . . (616)9546700
Livonia
Arrow/Schweber Electronics . . . . (810)4550850
Future Electronics . . . . . . . . . . . . (313)2615270
Hamilton/Hallmark . . . . . . . . . . . (313)4165800
Time Electronics . . . . . . . . . . . 1800789TIME
Troy
Newark . . . . . . . . . . . . . . . . . . . . . (810)5832899
MINNESOTA
Bloomington
Wyle Electronics . . . . . . . . . . . . . . . (612)8532280
Burnsville
PENSTOCK . . . . . . . . . . . . . . . . . . (612)8827630
Eden Prairie
Arrow/Schweber Electronics . . . . (612)9415280
FAI . . . . . . . . . . . . . . . . . . . . . . . . . (612)9470909
Future Electronics . . . . . . . . . . . . (612)9442200
Hamilton/Hallmark . . . . . . . . . . . (612)8812600
Time Electronics . . . . . . . . . . . 1800789TIME
Minneapolis
Newark . . . . . . . . . . . . . . . . . . . . . (612)3316350
Earth City
Hamilton/Hallmark . . . . . . . . . . . (314)2915350
MISSOURI
St. Louis
Arrow/Schweber Electronics . . . . (314)5676888
Future Electronics . . . . . . . . . . . . (314)4696805
FAI . . . . . . . . . . . . . . . . . . . . . . . . . (314)5429922
Newark . . . . . . . . . . . . . . . . . . . . . (314)4539400
Time Electronics . . . . . . . . . . . 1800789TIME
NEW JERSEY
Bridgewater
PENSTOCK . . . . . . . . . . . . . . . . . (908)5759490
Cherry Hill
Hamilton/Hallmark . . . . . . . . . . . . (609)4240110
East Brunswick
Newark . . . . . . . . . . . . . . . . . . . . . (908)9376600
Fairfield
FAI . . . . . . . . . . . . . . . . . . . . . . . . . (201)3311133
Long Island
FAI . . . . . . . . . . . . . . . . . . . . . . . . . (516)3483700
Marlton
Arrow/Schweber Electronics . . . . (609)5968000
FAI . . . . . . . . . . . . . . . . . . . . . . . . . (609)9881500
Future Electronics . . . . . . . . . . . . (609)5964080
Pinebrook
Arrow/Schweber Electronics . . . . (201)2277880
Wyle Electronics . . . . . . . . . . . . . . (201)8828358
Parsippany
Future Electronics . . . . . . . . . . . . (201)2990400
Hamilton/Hallmark . . . . . . . . . . . (201)5151641
Wayne
Time Electronics . . . . . . . . . . . 1800789TIME
MOTOROLA
Hamilton/Hallmark . . . . . . . . . . . (503)5266200
Wyle Electronics . . . . . . . . . . . . . (503)6437900
NEW MEXICO
Albuquerque
Alliance Electronics . . . . . . . . . . (505)2923360
Hamilton/Hallmark . . . . . . . . . . . . (505)8281058
Newark . . . . . . . . . . . . . . . . . . . . . (505)8281878
NEW YORK
Bohemia
Newark . . . . . . . . . . . . . . . . . . . . . (516)5674200
Hauppauge
Arrow/Schweber Electronics . . . .
Future Electronics . . . . . . . . . . . .
Hamilton/Hallmark . . . . . . . . . . .
PENSTOCK . . . . . . . . . . . . . . . . .
(516)2311000
(516)2344000
(516)4347400
(516)7249580
Portland
FAI . . . . . . . . . . . . . . . . . . . . . . . . . (503)2975020
Newark . . . . . . . . . . . . . . . . . . . . . (503)2971984
PENSTOCK . . . . . . . . . . . . . . . . . (503)6461670
Time Electronics . . . . . . . . . . . 1800789TIME
PENNSYLVANIA
Coatesville
PENSTOCK . . . . . . . . . . . . . . . . . (610)3839536
Ft. Washington
Newark . . . . . . . . . . . . . . . . . . . . . (215)6541434
Mt. Laurel
Wyle Electronics . . . . . . . . . . . . . (609)4399110
Konkoma
Hamilton/Hallmark . . . . . . . . . . . (516)7370600
Melville
Wyle Laboratories . . . . . . . . . . . . (516)2938446
Pittsford
Philadelphia
Time Electronics . . . . . . . . . . . 1800789TIME
Wyle Electronics . . . . . . . . . . . . . (609)4399110
Pittsburgh
Newark . . . . . . . . . . . . . . . . . . . . . (716)3814244
Rochester
Arrow/Schweber Electronics . . . . (716)4270300
Future Electronics . . . . . . . . . . . . (716)3879550
FAI . . . . . . . . . . . . . . . . . . . . . . . . . (716)3879600
Hamilton/Hallmark . . . . . . . . . . . . (716)2722740
Time Electronics . . . . . . . . . . . 1800789TIME
Syracuse
FAI . . . . . . . . . . . . . . . . . . . . . . . . . (315)4514405
Future Electronics . . . . . . . . . . . . (315)4512371
Newark . . . . . . . . . . . . . . . . . . . . . (315)4574873
Time Electronics . . . . . . . . . . . 1800789TIME
NORTH CAROLINA
Charlotte
FAI . . . . . . . . . . . . . . . . . . . . . . . . . (704)5489503
Future Electronics . . . . . . . . . . . . (704)5471107
Raleigh
Arrow/Schweber Electronics . . . . (919)8763132
FAI . . . . . . . . . . . . . . . . . . . . . . . . . (919)8760088
Future Electronics . . . . . . . . . . . . (919)7907111
Hamilton/Hallmark . . . . . . . . . . . (919)8720712
Newark . . . . . . . . . . . . . . . . . . . . . (919)7817677
Time Electronics . . . . . . . . . . . 1800789TIME
OHIO
Centerville
Arrow/Schweber Electronics . . . . (513)4355563
Cleveland
FAI . . . . . . . . . . . . . . . . . . . . . . . . . (216)4460061
Newark . . . . . . . . . . . . . . . . . . . . . (216)3919330
Time Electronics . . . . . . . . . . . 1800789TIME
Columbus
TENNESSEE
Knoxville
Newark . . . . . . . . . . . . . . . . . . . . . (615)5886493
TEXAS
Austin
Arrow/Schweber Electronics . . . . (512)8354180
Future Electronics . . . . . . . . . . . . (512)5020991
FAI . . . . . . . . . . . . . . . . . . . . . . . . . (512)3466426
Hamilton/Hallmark . . . . . . . . . . . (512)2193700
Newark . . . . . . . . . . . . . . . . . . . . . (512)3380287
PENSTOCK . . . . . . . . . . . . . . . . . (512)3469762
Time Electronics . . . . . . . . . . . 1800789TIME
Wyle Electronics . . . . . . . . . . . . . (512)8339953
Benbrook
PENSTOCK . . . . . . . . . . . . . . . . . (817)2490442
Carollton
Arrow/Schweber Electronics . . . . (214)3806464
Dallas
FAI . . . . . . . . . . . . . . . . . . . . . . . . . (214)2317195
Future Electronics . . . . . . . . . . . . (214)4372437
Hamilton/Hallmark . . . . . . . . . . . (214)5534300
Newark . . . . . . . . . . . . . . . . . . . . . (214)4582528
Time Electronics . . . . . . . . . . . 1800789TIME
Wyle Electronics . . . . . . . . . . . . . (214)2359953
El Paso
FAI . . . . . . . . . . . . . . . . . . . . . . . . . (915)5779531
Ft. Worth
Allied Electronics . . . . . . . . . . . . . (817)3365401
Newark . . . . . . . . . . . . . . . . . . . . . (614)3260352
Time Electronics . . . . . . . . . . . 1800789TIME
Dayton
FAI . . . . . . . . . . . . . . . . . . . . . . . . . (513)4276090
Future Electronics . . . . . . . . . . . . (513)4260090
Hamilton/Hallmark . . . . . . . . . . . (513)4396735
Newark . . . . . . . . . . . . . . . . . . . . . (513)2948980
Time Electronics . . . . . . . . . . . 1800789TIME
Mayfield Heights
Future Electronics . . . . . . . . . . . . (216)4496996
Solon
Arrow/Schweber Electronics . . . . (216)2483990
Hamilton/Hallmark . . . . . . . . . . . (216)4981100
Worthington
Hamilton/Hallmark . . . . . . . . . . . (614)8883313
OKLAHOMA
Tulsa
FAI . . . . . . . . . . . . . . . . . . . . . . . . . (918)4921500
Hamilton/Hallmark . . . . . . . . . . . (918)4596000
Newark . . . . . . . . . . . . . . . . . . . . . (918)2525070
OREGON
Beaverton
Houston
Arrow/Schweber Electronics . . . . (713)6476868
FAI . . . . . . . . . . . . . . . . . . . . . . . . . (713)9527088
Future Electronics . . . . . . . . . . . . (713)7851155
Hamilton/Hallmark . . . . . . . . . . . (713)7816100
Newark . . . . . . . . . . . . . . . . . . . . . (713)8949334
Time Electronics . . . . . . . . . . . 1800789TIME
Wyle Electronics . . . . . . . . . . . . . (713)8799953
Richardson
PENSTOCK . . . . . . . . . . . . . . . . . (214)4799215
San Antonio
FAI . . . . . . . . . . . . . . . . . . . . . . . . . (210)7383330
UTAH
Salt Lake City
Arrow/Schweber Electronics . . . .
FAI . . . . . . . . . . . . . . . . . . . . . . . . .
Future Electronics . . . . . . . . . . . .
Hamilton/Hallmark . . . . . . . . . . . .
Newark . . . . . . . . . . . . . . . . . . . . .
Wyle Electronics . . . . . . . . . . . . .
(801)9736913
(801)4679696
(801)4674448
(801)2662022
(801)2615660
(801)9749953
594
7/1/96
Mississauga
ALBERTA
Calgary
Bothell
Future Electronics . . . . . . . . . . . . (206)4893400
Redmond
Hamilton/Hallmark . . . . . . . . . . . . (206)8827000
Time Electronics . . . . . . . . . . . 1800789TIME
Wyle Electronics . . . . . . . . . . . . . (206)8811150
PENSTOCK . . . . . . . . . . . . . . . . . (905)4030724
Ottawa
Arrow Electronics . . . . . . . . . . . .
Electro Sonic Inc. . . . . . . . . . . . .
FAI . . . . . . . . . . . . . . . . . . . . . . . . .
Future Electronics . . . . . . . . . . . .
Hamilton/Hallmark . . . . . . . . . . . .
BRITISH COLUMBIA
Future Electronics . . . . . . . . . . . . (403)2505550
Hamilton/Hallmark . . . . . . . . . . . . (800)6635500
Edmonton
FAI . . . . . . . . . . . . . . . . . . . . . . . . . (403)4385888
Future Electronics . . . . . . . . . . . . (403)4382858
Hamilton/Hallmark . . . . . . . . . . . (800)6635500
Toronto
Arrow Electronics . . . . . . . . . . . .
Electro Sonic Inc. . . . . . . . . . . . .
FAI . . . . . . . . . . . . . . . . . . . . . . . . .
Future Electronics . . . . . . . . . . . .
Hamilton/Hallmark . . . . . . . . . . . .
Newark . . . . . . . . . . . . . . . . . . . . .
Saskatchewan
Hamilton/Hallmark . . . . . . . . . . . (800)6635500
Seattle
FAI . . . . . . . . . . . . . . . . . . . . . . . . . (206)4856616
Wyle Electronics . . . . . . . . . . . . . . (206)8811150
WISCONSIN
Brookfield
Arrow/Schweber Electronics . . . . (414)7920150
Future Electronics . . . . . . . . . . . . (414)8790244
Wyle Electronics . . . . . . . . . . . . . (414)5219333
Milwaukee
FAI . . . . . . . . . . . . . . . . . . . . . . . . . (414)7929778
Time Electronics . . . . . . . . . . . 1800789TIME
New Berlin
Hamilton/Hallmark . . . . . . . . . . . (414)7807200
Wauwatosa
Newark . . . . . . . . . . . . . . . . . . . . . (414)4539100
CANADA
Vancouver
Arrow Electronics . . . . . . . . . . . .
Electro Sonic Inc. . . . . . . . . . . . .
FAI . . . . . . . . . . . . . . . . . . . . . . . . .
Future Electronics . . . . . . . . . . . .
Hamilton/Hallmark . . . . . . . . . . . .
(604)4212333
(604)2732911
(604)6541050
(604)2941166
(604)4204101
(905)6707769
(416)4941666
(905)6129888
(905)6129200
(905)5646060
(905)6702888
QUEBEC
Montreal
MANITOBA
Winnipeg
Electro Sonic Inc. . . . . . . . . . . .
FAI . . . . . . . . . . . . . . . . . . . . . . . . .
Future Electronics . . . . . . . . . . . .
Hamilton/Hallmark . . . . . . . . . . . .
(613)2266903
(613)7288333
(613)8208244
(613)8208313
(613)2261700
(204)7833105
(204)7863075
(204)9441446
(800)6635500
Arrow Electronics . . . . . . . . . . . .
FAI . . . . . . . . . . . . . . . . . . . . . . . . .
Future Electronics . . . . . . . . . . . .
Hamilton/Hallmark . . . . . . . . . . . .
(514)4217411
(514)6948157
(514)6947710
(514)3351000
Quebec City
Arrow Electronics . . . . . . . . . . . . (418)6874231
FAI . . . . . . . . . . . . . . . . . . . . . . . . . (418)6825775
Future Electronics . . . . . . . . . . . . (418)8776666
ONTARIO
Kanata
PENSTOCK . . . . . . . . . . . . . . . . . (613)5926088
INTERNATIONAL DISTRIBUTORS
AUSTRALIA
AVNET VSI Electronics (Australia) (61)2 8781299
Veltek Australia Pty Ltd . . . . . (61)3 95749300
AUSTRIA
EBV Austria . . . . . . . . . . . . . . . . . (43) 1 8941774
Elbatex GmbH . . . . . . . . . . . . . . . . (43) 1 866420
Spoerle Austria . . . . . . . . . . . . . (43) 1 31872700
BELGIUM
Diode Spoerle . . . . . . . . . . . . . . (32) 2 725 4660
EBV Belgium . . . . . . . . . . . . . . . (32) 2 716 0010
CHINA
Advanced Electronics Ltd. . . . (852)2 3053633
AVNET WKK Components Ltd. (852)2 3578888
China El. App. Corp. Xiamen Co
. . . . . . . . . . . . . . . . . . . . . . . . . (86)592 5132489
Nanco Electronics Supply Ltd. (852) 2 3335121
Qing Cheng Enterprises Ltd. . (852) 2 4934202
DENMARK
Arrow Exatec . . . . . . . . . . . . . . . (45) 44 927000
Avnet Nortec A/S . . . . . . . . . . . . (45) 44 880800
EBV Denmark . . . . . . . . . . . . . . . . (45) 39690511
ESTONIA
Arrow Field Eesti . . . . . . . . . . . . . . (372) 6503288
Avnet Baltronic . . . . . . . . . . . . . . . (372) 6397000
FINLAND
Arrow Field OY . . . . . . . . . . . . . (35) 807 775 71
Avnet Nortec OY . . . . . . . . . . . . . (35) 806 13181
FRANCE
Arrow Electronique . . . . . . . . (33) 1 49 78 49 78
Avnet Components . . . . . . . . (33) 1 49 65 25 00
EBV France . . . . . . . . . . . . . . (33) 1 64 68 86 00
Future Electronics . . . . . . . . . . . . (33)1 69821111
Newark . . . . . . . . . . . . . . . . . . . . (33)130954060
SEI/Scaib . . . . . . . . . . . . . . . . (33) 1 69 19 89 00
GERMANY
HOLLAND
EBV Holland . . . . . . . . . . . . . . (31) 3465 623 53
Diode Spoerle BV . . . . . . . . . . . . (31) 4054 5430
HONG KONG
AVNET WKK Components Ltd. (852)2 3578888
Nanshing Clr. & Chem. Co. Ltd (852)2 3335121
INDIA
Canyon Products Ltd . . . . . . . (91) 80 5587758
PHILIPPINES
Alexan Commercial . . . . . . . . . (63) 22419493
SINGAPORE
Future Electronics . . . . . . . . . . . . . (65) 4791300
Strong Pte. Ltd . . . . . . . . . . . . . . . (65) 2763996
Uraco Technologies Pte Ltd. . . . . (65) 5457811
SPAIN
Amitron Arrow . . . . . . . . . . . . . . (34) 1 304 30 40
EBV Spain . . . . . . . . . . . . . . . . . (34) 1 804 32 56
Selco S.A. . . . . . . . . . . . . . . . . . (34) 1 637 10 11
SWEDEN
ArrowTh:s . . . . . . . . . . . . . . . . . . (46) 8 362970
Avnet Nortec AB . . . . . . . . . . . . (46) 8 629 14 00
SWITZERLAND
INDONESIA
P.T. Ometraco . . . . . . . . . . . . . (62) 21 6196166
ITALY
Avnet Adelsy SpA . . . . . . . . . . . . . (39) 2 381901
EBV Italy . . . . . . . . . . . . . . . . . . . . (39) 2 660961
Silverstar SpA . . . . . . . . . . . . . . . (39) 2 66 12 51
JAPAN
AMSC Co., Ltd. . . . . . . . . . . . .
Fuji Electronics Co., Ltd. . . . .
Marubun Corporation . . . . . . .
Nippon Motorola Micro Elec. . .
OMRON Corporation . . . . . . .
Tokyo Electron Ltd. . . . . . . . . .
81422546800
81338141411
81336398951
81332807300
81337799053
81355617254
S. AFRICA
Advanced . . . . . . . . . . . . . . . . . . (27) 11 4442333
Reuthec Components . . . . . . . (27) 11 8233357
THAILAND
Shapiphat Ltd. . . (66)22210432 or 22215384
TAIWAN
AvnetMercuries Co., Ltd . . . (886)2 5167303
Solomon Technology Corp. . . . (886)2 7888989
Strong Electronics Co. Ltd. . . (886)2 9179917
UNITED KINGDOM
KOREA
Jung Kwang Sa . . . . . . . . . . . . . . (82)22785333
LiteOn Korea Ltd. . . . . . . . . . . . (82)28583853
Nasco Co. Ltd. . . . . . . . . . . . . . . (82)237726800
NEW ZEALAND
AVNET VSI (NZ) Ltd . . . . . . . . . (64)9 6367801
NORWAY
595
MOTOROLA
7/1/96
UNITED STATES
ALABAMA
Huntsville . . . . . . . . . . . . . . . . . . . (205)4646800
ALASKA . . . . . . . . . . . . . . . . . . . . (800)6358291
ARIZONA
Tempe . . . . . . . . . . . . . . . . . . . . . . (602)3028056
CALIFORNIA
Calabasas . . . . . . . . . . . . . . . . . . .
Irvine . . . . . . . . . . . . . . . . . . . . . . .
Los Angeles . . . . . . . . . . . . . . . . .
San Diego . . . . . . . . . . . . . . . . . . .
Sunnyvale . . . . . . . . . . . . . . . . . . .
(818)8786800
(714)7537360
(818)8786800
(619)5412163
(408)7490510
COLORADO
Denver . . . . . . . . . . . . . . . . . . . . . (303)3373434
CONNECTICUT
Wallingford . . . . . . . . . . . . . . . . . . (203)9494100
FLORIDA
Clearwater . . . . . . . . . . . . . . . . . . (813)5244177
Maitland . . . . . . . . . . . . . . . . . . . . (407)6282636
Pompano Beach/Ft. Lauderdale (954)3516040
GEORGIA
Atlanta . . . . . . . . . . . . . . . . . . . . . (770)7297100
IDAHO
Boise . . . . . . . . . . . . . . . . . . . . . . . (208)3239413
ILLINOIS
Chicago/Schaumburg . . . . . . . . . (847)4132500
INDIANA
Indianapolis . . . . . . . . . . . . . . . . . (317)5710400
Kokomo . . . . . . . . . . . . . . . . . . . . (317)4555100
Milan . . . . . . . . . . . . . . . . . . . . . . . . . . 39(2)82201
TENNESSEE
Knoxville . . . . . . . . . . . . . . . . . . . . (423)5844841
TEXAS
Austin . . . . . . . . . . . . . . . . . . . . . . (512)5022100
Houston . . . . . . . . . . . . . . . . . . . . (713)2510006
Plano . . . . . . . . . . . . . . . . . . . . . . . (214)5165100
VIRGINIA
Richmond . . . . . . . . . . . . . . . . . . . (804)2852100
UTAH
CSI Inc. . . . . . . . . . . . . . . . . . . . . . (801)5724010
WASHINGTON
Bellevue . . . . . . . . . . . . . . . . . . . . (206)4544160
Seattle Access . . . . . . . . . . . . . . (206)6229960
WISCONSIN
Field Applications Engineering Available
Through All Sales Offices
CANADA
BRITISH COLUMBIA
MARYLAND
Columbia . . . . . . . . . . . . . . . . . . . (410)3811570
MASSACHUSETTS
Marlborough . . . . . . . . . . . . . . . . . (508)3578200
Woburn . . . . . . . . . . . . . . . . . . . . . (617)9329700
MICHIGAN
Detroit . . . . . . . . . . . . . . . . . . . . . . (810)3476800
Literature . . . . . . . . . . . . . . . . . . . (800)3922016
MINNESOTA
Minnetonka . . . . . . . . . . . . . . . . . . (612)9321500
MISSOURI
St. Louis . . . . . . . . . . . . . . . . . . . . (314)2757380
NEW JERSEY
Fairfield . . . . . . . . . . . . . . . . . . . . . (201)8082400
NEW YORK
Fairport . . . . . . . . . . . . . . . . . . . . . (716)4254000
Fishkill . . . . . . . . . . . . . . . . . . . . . . (914)8960511
Hauppauge . . . . . . . . . . . . . . . . . (516)3617000
NORTH CAROLINA
Raleigh . . . . . . . . . . . . . . . . . . . . . (919)8704355
OHIO
Cleveland . . . . . . . . . . . . . . . . . . . (216)3493100
Columbus/Worthington . . . . . . . . (614)4318492
Dayton . . . . . . . . . . . . . . . . . . . . . (513)4386800
OKLAHOMA
Tulsa . . . . . . . . . . . . . . . . . . . . . . . (918)4594565
OREGON
Portland . . . . . . . . . . . . . . . . . . . . (503)6413681
PENNSYLVANIA
MOTOROLA
Kyusyu . . . . . . . . . . . . . . . . . . . 81927257583
Gotanda . . . . . . . . . . . . . . . . . . 81354878311
Nagoya . . . . . . . . . . . . . . . . . . . 81522323500
Osaka . . . . . . . . . . . . . . . . . . . . . 8163051801
Sendai . . . . . . . . . . . . . . . . . . . 81222684333
Takamatsu . . . . . . . . . . . . . . . . 81878379972
Tokyo . . . . . . . . . . . . . . . . . . . . 81334403311
KOREA
Pusan . . . . . . . . . . . . . . . . . . . . . 82(51)4635035
Seoul . . . . . . . . . . . . . . . . . . . . . . . 82(2)5545118
MALAYSIA
MEXICO
Mexico City . . . . . . . . . . . . . . . . . 52(5)2820230
Guadalajara . . . . . . . . . . . . . . . . . 52(36)218977
Marketing . . . . . . . . . . . . . . . . . . . 52(36)212023
Customer Service . . . . . . . . . . . 52(36)6699160
NETHERLANDS
Best . . . . . . . . . . . . . . . . . . . . . . . (31)4998 612 11
Vancouver . . . . . . . . . . . . . . . . . . . (604)2937650
PHILIPPINES
Manila . . . . . . . . . . . . . . . . . . . . . (63)2 8220625
ONTARIO
Ottawa . . . . . . . . . . . . . . . . . . . . . (613)2263491
Toronto . . . . . . . . . . . . . . . . . . . . . (416)4978181
QUEBEC
Montreal . . . . . . . . . . . . . . . . . . . . (514)3333300
PUERTO RICO
San Juan . . . . . . . . . . . . . . . . . . . . (809)2822300
SINGAPORE . . . . . . . . . . . . . . . . . . (65)4818188
SPAIN
Madrid . . . . . . . . . . . . . . . . . . . . . . 34(1)4578204
or . . . . . . . . . . . . . . . . . . . . . . . . . . 34(1)4578254
JAPAN
Penang . . . . . . . . . . . . . . . . . . . . . 60(4)2282514
Milwaukee/Brookfield . . . . . . . . . (414)7920122
IOWA
KANSAS
Herzlia . . . . . . . . . . . . . . . . . . . . . 9729590222
ITALY
SWEDEN
INTERNATIONAL
AUSTRALIA
Solna . . . . . . . . . . . . . . . . . . . . . . . 46(8)7348800
Melbourne . . . . . . . . . . . . . . . . . (613)98870711
Sydney . . . . . . . . . . . . . . . . . . . . (612)29661071
BRAZIL
Sao Paulo . . . . . . . . . . . . . . . . . 55(11)8154200
CHINA
Beijing . . . . . . . . . . . . . . . . . . . . .
Guangzhou . . . . . . . . . . . . . . . .
Shanghai . . . . . . . . . . . . . . . . . .
Tianjin . . . . . . . . . . . . . . . . . . . . .
86108437222
86207537888
86213747668
86225325072
DENMARK
Denmark . . . . . . . . . . . . . . . . . . . . . (45) 43488393
FINLAND
Helsinki . . . . . . . . . . . . . . . . . . . 3580351 61191
car phone . . . . . . . . . . . . . . . . . . . 358(49)211501
FRANCE
SWITZERLAND
Geneva . . . . . . . . . . . . . . . . . . . . 41(22)799 11 11
Zurich . . . . . . . . . . . . . . . . . . . . . . 41(1)7304074
TAIWAN
Taipei . . . . . . . . . . . . . . . . . . . . . 886(2)7177089
THAILAND
Bangkok . . . . . . . . . . . . . . . . . . . . 66(2)2544910
UNITED KINGDOM
Aylesbury . . . . . . . . . . . . . . . . . 44 1 (296)395252
NEVADA, Reno
Galena Tech. Group . . . . . . . . . . (702)7460642
GERMANY
Langenhagen/Hanover . . . . . . . 49(511)786880
Munich . . . . . . . . . . . . . . . . . . . . . 49 89 921030
Nuremberg . . . . . . . . . . . . . . . . . 49 911 963190
Sindelfingen . . . . . . . . . . . . . . . . . 49 7031 79 710
Wiesbaden . . . . . . . . . . . . . . . . . . 49 611 973050
HONG KONG
Kwai Fong . . . . . . . . . . . . . . . . . 85226106888
Tai Po . . . . . . . . . . . . . . . . . . . . 85226668333
INDIA
Bangalore . . . . . . . . . . . . . . . . . . 91805598615
ISRAEL
596
WASHINGTON, Spokane
Doug Kenley . . . . . . . . . . . . . . . . (509)9242322
(407)2987100
(818)7687400
(512)8342022
(310)5944631
597
MOTOROLA
MOTOROLA
598
General Information
*DL140/D*
DL140/D