CURSUL 2:

INTRODUCTION (2)

INTRODUCTION

Integrated circuits: many transistors on one chip.

Very Large Scale Integration (VLSI): bucketloads!
Complementary Metal Oxide Semiconductor

Fast, cheap, low power transistors

Today: How to build your own simple CMOS chip

CMOS transistors
Building logic gates from transistors
Transistor layout and fabrication

Rest of the course: How to build a good CMOS chip

SILICON LATTICE
Transistors are built on a silicon substrate
Silicon is a Group IV material
Forms crystal lattice with bonds to four neighbors

Si

Si

Si

Si

Si

Si

Si

Si

Si

DOPANTS
Silicon is a semiconductor
Pure silicon has no free carriers and conducts poorly
Adding dopants increases the conductivity
Group V: extra electron (n-type) Arsenic
Group III: missing electron, called hole (p-type) Boron

Si

Si

Si

Si

Si

Si

As

Si

Si

Si

Si

Si

Si

Si

+
-

Si
Si
Si

P-N JUNCTIONS
A junction between p-type and n-type semiconductor forms a diode.
Current flows only in one direction

p-type

n-type

anode

cathode

NMOS TRANSISTOR
Four terminals: gate, source, drain, body
Gate oxide body stack looks like a capacitor

Gate and body are conductors

SiO2 (oxide) is a very good insulator
Called metal oxide semiconductor (MOS) capacitor
Even though gate is no longer made of metal*

* Metal gates are returning today!

6

NMOS OPERATION
Body is usually tied to ground (0 V)
When the gate is at a low voltage:

Source

Gate

Drain
Polysilicon
SiO2

P-type body is at low voltage

Source-body and drain-body diodes are OFF
No current flows, transistor is OFF

n+

n+
S

bulk Si

NMOS OPERATION CONT.

When the gate is at a high voltage:

Source

Gate

Drain
Polysilicon
SiO2

Positive charge on gate of MOS capacitor

Negative charge attracted to body
Inverts a channel under gate to n-type

n+

n+
S

bulk Si

Now current can flow through n-type silicon from source through channel to drain,
transistor is ON

PMOS TRANSISTOR
Similar, but doping and voltages reversed

Body tied to high voltage (VDD)

Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior

POWER SUPPLY VOLTAGE

GND = 0 V
In 1980s, VDD = 5V
VDD has decreased in modern processes

High VDD would damage modern tiny transistors

Lower VDD saves power

VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0,

10

TRANSISTORS AS SWITCHES
We can view MOS transistors as electrically controlled switches
Voltage at gate controls path from source to drain
d
nMOS

pMOS

g=1

d
OFF

ON

OFF

ON
s

11

g=0

COMPLEMENTARY CMOS
Complementary CMOS logic gates

pMOS
pull-up
network

nMOS pull-down network

inputs

pMOS pull-up network

output

a.k.a. static CMOS

Pull-up OFF

Pull-up ON

Pull-down OFF Z (float)

Pull-down ON

X (crowbar)

12

1: Circuits & Layout

nMOS
pull-down
network

CMOS INVERTER
A

1 0

ON OFF

OFF ON

A
13

Y
0: Introduction

SERIES AND PARALLEL

a
0

g1
g2

(a)

(b)

a
g1

g2

(c)

a
g1

g2
b

(d)

1
b

OFF

OFF

OFF

ON

a
1

1
b

ON

OFF

OFF

OFF

0
b

g2

a
g1

0
b

nMOS: 1 = ON
pMOS: 0 = ON
Series: both must be ON
Parallel: either can be ON

OFF

ON

ON

ON

ON

ON

ON

OFF

14

1: Circuits & Layout

CMOS NAND GATE

15

ON
OFF

ON
OFF

Y
A
B

0
1
0
1

OFF
ON
OFF
ON

0: Introduction

CMOS NOR GATE

16

A
B
Y

3-INPUT NAND GATE

Y pulls low if ALL inputs are 1
Y pulls high if ANY input is 0

Y
A
B
C

17

COMPOUND GATES
Compound gates can do any inverting function
Ex: Y (A B) (C D) (AND-AND OR INV AOI22)
A

(a)

(b)

B C

(c)

(d)

A
B
C
D

(e)

(f)

SIGNAL STRENGTH
Strength of signal

How close it approximates ideal voltage source

VDD and GND rails are strongest 1 and 0

nMOS pass strong 0

But degraded or weak 1

pMOS pass strong 1

But degraded or weak 0

Thus nMOS are best for pull-down network

PASS TRANSISTORS

Transistors can be used as switches

TRANSMISSION GATES
Pass transistors produce degraded outputs
Transmission gates pass both 0 and 1 well
Input
g
a

b
gb

b
gb

g = 0, gb = 1
a
b

g = 1, gb = 0
0
strong 0

g = 1, gb = 0
a
b

g = 1, gb = 0
strong 1
1

g
a

g
b

gb

Output

b
gb

21

1: Circuits & Layout

TRISTATES
Tristate buffer produces Z when not enabled
EN

EN
Y

EN
Y

A
EN

NONRESTORING TRISTATE
Transmission gate acts as tristate buffer

Only two transistors

But nonrestoring

Noise on A is passed on to Y

EN
A

Y
EN

MULTIPLEXERS
2:1 multiplexer chooses between two inputs
S
S

D1

D0

D0

0
Y

D1

4:1 MULTIPLEXER
4:1 mux chooses one of 4 inputs using two selects

Two levels of 2:1 muxes

Or four tristates

S1S0 S1S0 S1S0 S1S0

D0
S0
D0

D1

S1
D1
0
Y

Y
D2

D3

1
D2

D3

D LATCH
When CLK = 1, latch is transparent

D flows through to Q like a buffer

When CLK = 0, the latch is opaque

Q holds its old value independent of D

a.k.a. transparent latch or level-sensitive latch

Latch

CLK

CLK
D

Q
Q

D LATCH DESIGN
Multiplexer chooses D or old Q
CLK
D

CLK

Q
Q

0
CLK

CLK

CLK

D LATCH OPERATION
Q
D

CLK = 1

CLK
D
Q

Q
D

CLK = 0

D FLIP-FLOP DESIGN
Built from master and slave D latches
CLK

CLK
CLK

QM

D
CLK
QM

Latch

Latch

CLK

CLK

Q
CLK

CLK

Q
CLK

CLK

D FLIP-FLOP OPERATION
D

QM

CLK = 0

CLK = 1

CLK
D
Q

QM

CMOS FABRICATION
CMOS transistors are fabricated on silicon wafer
Lithography process similar to printing press
On each step, different materials are deposited or etched
Easiest to understand by viewing both top and cross-section of wafer in a
simplified manufacturing process

31

0: Introduction

INVERTER CROSS-SECTION
Typically use p-type substrate for nMOS transistors
Requires n-well for body of pMOS transistors

32

0: Introduction

WELL AND SUBSTRATE TAPS

Substrate must be tied to GND and n-well to VDD
Metal to lightly-doped semiconductor forms poor connection called Shottky
Diode

Use heavily doped well and substrate contacts / taps

33

0: Introduction

INVERTER MASK SET

Transistors and wires are defined by masks
Cross-section taken along dashed line
A

GND

34

VDD
nMOS transistor
substrate tap

pMOS transistor
well tap

0: Introduction

DETAILED MASK VIEWS

Six masks

35

n-well
Polysilicon
n+ diffusion
p+ diffusion
Contact
Metal

0: Introduction

FABRICATION
Chips are built in huge factories called fabs
Contain clean rooms as large as football fields

Courtesy of International
Business Machines Corporation.
Unauthorized use not permitted.

INTEGRATED CIRCUITS ON WAFERS

In this picture you can see how one big

crystal is grown from the purified
silicon melt. The resulting mono crystal
is called Ingot.

The Ingot is cut into individual silicon discs called

wafers

COST OF AN IC

The total cost of a product can be separated into

two components: the recurring expenses (variable
cost) and the non-recurring expenses (fixed cost).

Fixed cost; man-power, companys R&D,

manufacturing equipment, marketing, sales, building
infrastructures,

Variable cost; directly attributes to a manufactures

product and is proportional to the product volume.

FABRICATION STEPS
Start with blank wafer
Build inverter from the bottom up
First step will be to form the n-well

Cover wafer with protective layer of SiO2 (oxide)

Remove layer where n-well should be built
Implant or diffuse n dopants into exposed wafer
Strip off SiO2

p substrate

OXIDATION
Grow SiO2 on top of Si wafer
900 1200 C with H2O or O2 in oxidation furnace

SiO2

p substrate

40

0: Introduction

PHOTORESIST
Spin on photoresist
Photoresist is a light-sensitive organic polymer
Softens where exposed to light

Photoresist
SiO2

p substrate

41

0: Introduction

LITHOGRAPHY
Expose photoresist through n-well mask
Strip off exposed photoresist

Photoresist
SiO2

p substrate

42

0: Introduction

ETCH
Etch oxide with Acid fluorhidric
Seeps through skin and eats bone; nasty stuff!!!

Only attacks oxide where resist has been exposed

Photoresist
SiO2

p substrate

43

0: Introduction

STRIP PHOTORESIST
Strip off remaining photoresist
Use mixture of acids called piranah etch

Necessary so resist doesnt melt in next step

SiO2

p substrate

44

0: Introduction

N-WELL
n-well is formed with diffusion or ion implantation
Diffusion
Place wafer in furnace with arsenic gas
Heat until As atoms diffuse into exposed Si

Ion Implanatation
Blast wafer with beam of As ions
Ions blocked by SiO2, only enter exposed Si
SiO2
n well

STRIP OXIDE
Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of steps

n well
p substrate

POLYSILICON
Deposit very thin layer of gate oxide
< 20 (6-7 atomic layers)

Chemical Vapor Deposition (CVD) of silicon layer

Place wafer in furnace with Silane gas (SiH4)
Forms many small crystals called polysilicon
Heavily doped to be good conductor

POLYSILICON PATTERNING
Use same lithography process to pattern polysilicon

Polysilicon

SELF-ALIGNED PROCESS
Use oxide and masking to expose where n+ dopants should be diffused or
implanted

N-diffusion forms nMOS source, drain, and n-well contact

N-DIFFUSION
Pattern oxide and form n+ regions
Self-aligned process where gate blocks diffusion
Polysilicon is better than metal for self-aligned gates because it doesnt melt
during later processing

n well
p substrate

N-DIFFUSION CONT.
Historically dopants were diffused
Usually ion implantation today
But regions are still called diffusion

N-DIFFUSION CONT.
Strip off oxide to complete patterning step

P-DIFFUSION
Similar set of steps form p+ diffusion regions for pMOS source and drain and
substrate contact

CONTACTS
Now we need to wire together the devices
Cover chip with thick field oxide
Etch oxide where contact cuts are needed
Contact

METALIZATION
Sputter on aluminum over whole wafer
Pattern to remove excess metal, leaving wires

M etal

LAYOUT
Chips are specified with set of masks
Minimum dimensions of masks determine transistor size (and hence speed, cost, and power)
Feature size f = distance between source and drain

Set by minimum width of polysilicon

Feature size improves 30% every 3 years or so

Normalize for feature size when describing design rules
Express rules in terms of = f/2

E.g. = 0.3 m in 0.6 m process

SIMPLIFIED DESIGN RULES

Conservative rules to get you started

INVERTER LAYOUT
Transistor dimensions specified as Width / Length
Minimum size is 4 / 2sometimes called 1 unit
In f = 0.6 m process, this is 1.2 m wide, 0.6 m long

58

0: Introduction

SUMMARY

MOS transistors are stacks of gate, oxide, silicon

Act as electrically controlled switches
Build logic gates out of switches
Draw masks to specify layout of transistors

Now you know everything necessary to start designing schematics and layout for a
simple chip!

ABOUT THESE NOTES

CMOS VLSI Design: A circuit and system perspective, Weste&Harris.
http://cmosvlsi.com/

Lecture notes 2011 David Money Harris

These notes may be used and modified for educational and/or noncommercial purposes so long as the source is attributed.