Page 1

MALINENI LAKSHMAIAH WOMEN`S

ENGINEERING COLLEGE
(Approved by AICTE & Affiliated to JNTU, KAKINADA)
PULLADIGUNTA, Guntur- 522 013

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LIST OF EXPERIMENTS
1. Realization of Logic gates.
2. Parity Encoder.
3. Random Counter
4. Synchronous RAM.
5. ALU. 6. UART Model.
7. Fire Detection and Control System using Combinational Logic
circuits.
8. Traffic Light Controller using Sequential Logic circuits
9. Pattern Detection using Moore Machine.
10. Finite State Machine (FSM) based logic circuit.

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1. REALIZATION OF LOGIC GATES

AIM: To Design the following Logic Gates and verify the functionality using software
and hardware.
1.AND Gate
2.OR Gate
3.NOT Gate
4.NAND Gate
5.NOR Gate
6.Ex-OR Gate
7.Ex-NOR Gate
APPARATUS:
1. Xilinx ise 9.2i
2. Digital IC-7408,7432,7404,7400,7402,7486,74135
3. Power cards, interfacing cards

AND GATE
I.DESIGN PROCEDURE:
1 .Def:-A circuit whose output is 1 if both of its inputs are 1 and output is 0 if any of
its input is 0.
2 Determine the required number of input and output from specification
Number of inputs:2
Number of outputs:1
3. Assign a symbol to each input/output
Inputs:x,y
Outputs:z
3. Derive the truth table from the required relationship
Inputs
y

Outp
ut
z

4. Obtain the simplified Boolean functions

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5. Draw the logic diagram and verify design correctness

II PIN DIAGRAM OF IC7408:

The above logic diagram can be represented using commercially available IC
74x08 as shown:

III VERIFICATION USING SOFTWARE:

VHDL CODE:
Library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is
port(
x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC
);
end AND2;
--Dataflow model
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architecture behav1 of AND2 is

begin
Z<= x and y;

--Signal Assignment Statement

end behav1;
-- Behavioral model
architecture behav2 of AND2 is
begin
process (x, y)
begin
if (x='1' and y='1') then
Z <= '1';
else
Z <= '0';
end if;
end process;
end behav2;

-- Compare with truth table

PROCEDURE TO WORK WITH XILINX TOOL:

After installing Xilinx software go to start menu, Programs Xilinx Project navigator
1. Select file New project
2. A window will be appearing. Write the project name then click next.
3. The window will be displayed. In the project device options select the options then click
on Next.
4. Click on new source.
5. Select VHDL Module and write the file name as same as project name. And click Next
button.
6. Provide inputs and outputs. And click next
7. Click finish button.
8. Click Next two times and Finish once for upcoming windows. A dummy program will be
created
9. Make the changes in the program according to your requirements and save the program.
10.Perform check syntax if the check syntax is completed successfully. Synthesize the
program. You will get the synthesis report, schematic and Technology Schematic.
Dept. of Electronics and Communication Engineering

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CREATING TEST BENCH FOR THE VHDL MODEL

1. Create a test bench by Right clicking on the project name and Select new source.
2. Select VHDL Test bench and give the file name as tb_Program name and click
next. A dummy test bench will be created. Provide the test bench and save the test
bench.
3. Perform Check syntax and simulate test bench. SIMULATION RESULTS will be
displayed
OUT PUT WAVE FORM:

OR gate
I.DESIGN PROCEDURE:

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1 .Def:-A circuit whose output is 0 when all the inputs are 0 otherwise the output will
be 1.
2 Determine the required number of input and output from specification
Number of inputs:2
Number of outputs:1
3. Assign a symbol to each input/output
Inputs:x,y
Outputs:z
3. Derive the truth table from the required relationship
Inputs
y

Outp
ut
z

4. Obtain the simplified Boolean functions

5. Draw the logic diagram and verify design correctness

II PIN DIAGRAM OF IC7432:

The above logic diagram can be represented using commercially available
IC 74x32 as shown:

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III VERIFICATION USING SOFTWARE:

VHDL CODE:
Library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is
port(
x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC
);
end OR2;
--Dataflow model
architecture behav1 of OR2 is
begin
Z <= x or y;

--Signal Assignment Statement

end behav1;

-- Behavioral model
architecture behav2 of OR2 is
begin
process (x, y)
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begin
if (x='0' and y='0') then -- Compare with truth table
Z <= '0';
else
Z<= '1';
end if;
end process;
end behav2;

PROCEDURE TO WORK WITH XILINX TOOL:

After installing Xilinx software go to start menu, Programs Xilinx Project navigator
1.Select file New project
2.A window will be appearing. Write the project name then click next.
3. The window will be displayed. In the project device options select the options then click
on Next.
4. Click on new source.
5. Select VHDL Module and write the file name as same as project name. And click Next
button.
6. Provide inputs and outputs. And click next
7. Click finish button.
8. Click Next two times and Finish once for upcoming windows. A dummy program will be
created
9. Make the changes in the program according to your requirements and save the program.
10.Perform check syntax if the check syntax is completed successfully. Synthesize the
program. You will get the synthesis report, schematic and Technology Schematic.

CREATING TEST BENCH FOR THE VHDL MODEL

1.Create a test bench by Right clicking on the project name and Select new source.
2. Select VHDL Test bench and give the file name as tb_Program name and click
next. A dummy test bench will be created. Provide the test bench and save the test
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bench.
3. Perform Check syntax and simulate test bench. SIMULATION RESULTS will be
displayed

OUTPUT WAVEFORM:

NOT gate
I.DESIGN PROCEDURE:
1 .Def:-A circuit whose output is compliment of the input.
2 Determine the required number of input and output from specification
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Number of inputs:1
Number of outputs:1
3. Assign a symbol to each input/output
Inputs:x
Outputs:y
3. Derive the truth table from the required relationship
Inpu
t
x

Outpu
t
y

4. Obtain the simplified Boolean functions

5. Draw the logic diagram and verify design correctness

II PIN DIAGRAM OF IC7404:

The above logic diagram can be represented using commercially available IC74x04
as
Shown:

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III VERIFICATION USING SOFTWARE:

VHDL CODE:
Library IEEE;
use IEEE.std_logic_1164.all;
entity not1 is
port(
X: in STD_LOGIC;
Z: out STD_LOGIC
);
end not1;
--Dataflow model
architecture behav1 of not1 is
begin
Z<= not X;

--Signal Assignment Statement

end behav1;

-- Behavioral model
architecture behav2 of not1 is
begin
process (X)
begin
if (x='0') then -- Compare with truth table
Z <= '1';
else
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Z<= '0';
end if;
end process;
end behav2;

PROCEDURE TO WORK WITH XILINX TOOL:

After installing Xilinx software go to start menu, Programs Xilinx Project navigator
1.Select file New project
2.A window will be appearing. Write the project name then click next.
3. The window will be displayed. In the project device options select the options then click
on Next.
4. Click on new source.
5. Select VHDL Module and write the file name as same as project name. And click Next
button.
6. Provide inputs and outputs. And click next
7. Click finish button.
8. Click Next two times and Finish once for upcoming windows. A dummy program will be
created
9. Make the changes in the program according to your requirements and save the program.
10.Perform check syntax if the check syntax is completed successfully. Synthesize the
program. You will get the synthesis report, schematic and Technology Schematic.
CREATING TEST BENCH FOR THE VHDL MODEL
1.Create a test bench by Right clicking on the project name and Select new source.
2. Select VHDL Test bench and give the file name as tb_Program name and click
next. A dummy test bench will be created. Provide the test bench and save the test
bench.
3. Perform Check syntax and simulate test bench. SIMULATION RESULTS will be
displayed
OUTPUT WAVEFORM:

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NAND gate
I.DESIGN PROCEDURE:
1 .Def:-A circuit whose output is 0 when all the inputs are 1 otherwise the output will
be 1.
2 Determine the required number of input and output from specification
Number of inputs:2
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Number of outputs:1
3. Assign a symbol to each input/output
Inputs:x,y
Outputs:z
3. Derive the truth table from the required relationship
Inputs
y

Outp
ut
z

4. Obtain the simplified Boolean functions

5. Draw the logic diagram and verify design correctness

II PIN DIAGRAM OF IC7400:

The above logic diagram can be represented using commercially available
IC 74x00 as shown:

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III VERIFICATION USING SOFTWARE:

VHDL CODE:
Library IEEE;
use IEEE.std_logic_1164.all;
entity nand2 is
port(
x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC
);
end nand2;
--Dataflow model
architecture behav1 of nand2 is
begin
z<= x nand y;

--Signal Assignment Statement

end behav1;

-- Behavioral model
architecture behav2 of nand2 is
begin
Process (x, y)
Begin
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If (x='1' and y='1') then -- Compare with truth table

Z <= '0';
else
Z <= '1';
end if;
end process;
end behav2

PROCEDURE TO WORK WITH XILINX TOOL:

After installing Xilinx software go to start menu, Programs Xilinx Project navigator
1.Select file New project
2.A window will be appearing. Write the project name then click next.
3. The window will be displayed. In the project device options select the options then click
on Next.
4. Click on new source.
5. Select VHDL Module and write the file name as same as project name. And click Next
button.
6. Provide inputs and outputs. And click next
7. Click finish button.
8. Click Next two times and Finish once for upcoming windows. A dummy program will be
created
9. Make the changes in the program according to your requirements and save the program.
10.Perform check syntax if the check syntax is completed successfully. Synthesize the
program. You will get the synthesis report, schematic and Technology Schematic.

CREATING TEST BENCH FOR THE VHDL MODEL

1.Create a test bench by Right clicking on the project name and Select new source.
2. Select VHDL Test bench and give the file name as tb_Program name and click
next. A dummy test bench will be created. Provide the test bench and save the test
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bench.
3. Perform Check syntax and simulate test bench. SIMULATION RESULTS will be
displayed
OUTPUT WAVEFORM:

NOR gate
I.DESIGN PROCEDURE:
1 .Def:-A circuit whose output is 1 when all the inputs are 0 otherwise the output will
be 0.
2 Determine the required number of input and output from specification
Number of inputs:2
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Number of outputs:1
3. Assign a symbol to each input/output
Inputs:x,y
Outputs:z
3. Derive the truth table from the required relationship
Inputs
y

Outp
ut
z

4. Obtain the simplified Boolean functions

5. Draw the logic diagram and verify design correctness

II PIN DIAGRAM OF IC7402:

The above logic diagram can be represented using commercially available
IC 74x02 as shown:

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III VERIFICATION USING SOFTWARE:

VHDL CODE:
Library IEEE;
use IEEE.std_logic_1164.all;
entity nor2 is
Port (
X: in STD_LOGIC;
Y: in STD_LOGIC;
Z: out STD_LOGIC
);
end nor2;
--Dataflow model
architecture behav1 of nor2 is
begin
Z<= x nor y;--Signal Assignment Statement
end behav1;

-- Behavioral model
architecture behav2 of nor2 is
begin
process (x, y)
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begin
If (x='0' and y='0') then -- Compare with truth table
Z <= '1';
else
Z <= '0';
end if;
end process;
end behav2;

PROCEDURE TO WORK WITH XILINX TOOL:

After installing Xilinx software go to start menu, Programs Xilinx Project navigator
1.Select file New project
2.A window will be appearing. Write the project name then click next.
3. The window will be displayed. In the project device options select the options then click
on Next.
4. Click on new source.
5. Select VHDL Module and write the file name as same as project name. And click Next
button.
6. Provide inputs and outputs. And click next
7. Click finish button.
8. Click Next two times and Finish once for upcoming windows. A dummy program will be
created
9. Make the changes in the program according to your requirements and save the program.
10.Perform check syntax if the check syntax is completed successfully. Synthesize the
program. You will get the synthesis report, schematic and Technology Schematic.

CREATING TEST BENCH FOR THE VHDL MODEL

1.Create a test bench by Right clicking on the project name and Select new source.
2. Select VHDL Test bench and give the file name as tb_Program name and click
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next. A dummy test bench will be created. Provide the test bench and save the test
bench.
3. Perform Check syntax and simulate test bench. SIMULATION RESULTS will be
displayed
OUTPUT WAVEFORM:

EX-OR gate
I.DESIGN PROCEDURE:
1 .Def:-A circuit whose output is 0 when all the inputs are same otherwise the
output will be 1.
2 Determine the required number of input and output from specification
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Number of inputs:2
Number of outputs:1
3. Assign a symbol to each input/output
Inputs:x,y
Outputs:z
3. Derive the truth table from the required relationship
Inputs
y

Outp
ut
z

4. Obtain the simplified Boolean functions

5. Draw the logic diagram and verify design correctness

II PIN DIAGRAM OF IC7486:

The above logic diagram can be represented using commercially available
IC 74x86 as shown:

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III VERIFICATION USING SOFTWARE:

VHDL CODE:
Library IEEE;
use IEEE.std_logic_1164.all;
entity xor2 is
Port (
X: in STD_LOGIC;
Y: in STD_LOGIC;
Z: out STD_LOGIC
);
end xor2;
--Dataflow model
architecture behav1 of xor2 is
begin
Z<= x xor y; --Signal Assignment Statement
end behav1;

-- Behavioral model
architecture behav2 of xor2 is
begin
process (x, y)
begin
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If (x/=y) then
Z <= '1';
else
Z<= '0';
end if;

-- Compare with truth table

end process;
end behav2;

PROCEDURE TO WORK WITH XILINX TOOL:

After installing Xilinx software go to start menu, Programs Xilinx Project navigator
1.Select file New project
2.A window will be appearing. Write the project name then click next.
3. The window will be displayed. In the project device options select the options then click
on Next.
4. Click on new source.
5. Select VHDL Module and write the file name as same as project name. And click Next
button.
6. Provide inputs and outputs. And click next
7. Click finish button.
8. Click Next two times and Finish once for upcoming windows. A dummy program will be
created
9. Make the changes in the program according to your requirements and save the program.
10.Perform check syntax if the check syntax is completed successfully. Synthesize the
program. You will get the synthesis report, schematic and Technology Schematic.

CREATING TEST BENCH FOR THE VHDL MODEL

1.Create a test bench by Right clicking on the project name and Select new source.
2. Select VHDL Test bench and give the file name as tb_Program name and click
next. A dummy test bench will be created. Provide the test bench and save the test
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bench.
3. Perform Check syntax and simulate test bench. SIMULATION RESULTS will be
displayed
OUTPUT WAVEFORM:

EX-NOR gate
I.DESIGN PROCEDURE:
1 .Def:-A circuit whose output is 1 when all the inputs are same otherwise the
output will be 0.
2 Determine the required number of input and output from specification
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Number of inputs:2
Number of outputs:1
3. Assign a symbol to each input/output
Inputs:x,y
Outputs:z
3. Derive the truth table from the required relationship
Inputs
y

Outp
ut
z

4. Obtain the simplified Boolean functions

5. Draw the logic diagram and verify design correctness

II PIN DIAGRAM OF IC74135:

The above logic diagram can be represented using commercially available
IC 74x135 as shown:

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III VERIFICATION USING SOFTWARE:

VHDL CODE:
Library IEEE;
use IEEE.std_logic_1164.all;
entity xnor2 is
Port (
X: in STD_LOGIC;
Y: in STD_LOGIC;
Z: out STD_LOGIC
);
end xnor2;
--Dataflow model
architecture behav1 of xnor2 is
begin
Z<= x xnor y;

--Signal Assignment Statement

end behav1;
-- Behavioral model
architecture behav2 of xnor2 is
begin
process (x, y)
begin
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If (x=y) then
Z <= '1';
else
Z<= '0';
end if;

-- Compare with truth table

end process;
end behav2;

PROCEDURE TO WORK WITH XILINX TOOL:

After installing Xilinx software go to start menu, Programs Xilinx Project navigator
1.Select file New project
2.A window will be appearing. Write the project name then click next.
3. The window will be displayed. In the project device options select the options then click
on Next.
4. Click on new source.
5. Select VHDL Module and write the file name as same as project name. And click Next
button.
6. Provide inputs and outputs. And click next
7. Click finish button.
8. Click Next two times and Finish once for upcoming windows. A dummy program will be
created
9. Make the changes in the program according to your requirements and save the program.
10.Perform check syntax if the check syntax is completed successfully. Synthesize the
program. You will get the synthesis report, schematic and Technology Schematic.

CREATING TEST BENCH FOR THE VHDL MODEL

1.Create a test bench by Right clicking on the project name and Select new source.
2. Select VHDL Test bench and give the file name as tb_Program name and click
next. A dummy test bench will be created. Provide the test bench and save the test
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bench.
3. Perform Check syntax and simulate test bench. SIMULATION RESULTS will be
displayed
OUTPUT WAVEFORM:

THEORY:
In digital electronic circuits as two logic levels Logic-I, Logic-O. These are also known as HIGH
and LOW logic levels.
There are two logic circuits.
1. Positive logic: In which 1 corresponding to HIGH, 0 corresponding to LOW.
2. Negative logic: In which 1 corresponding to LOW, 0 corresponding to HIGH.

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BASIC OPERATIONS:
AND Gate:
IC 74LS08 is quad 2-i/p AND gate. It requires 5V DC. The o/p of AND gate is HIGH
when both the inputs are HIGH otherwise HIGH.
OR Gate:
IC 74LS32 is quad 2-i/p OR gate. It requires 5V DC. The o/p of OR gate is LOW when
both the inputs are LOW otherwise IIIGH.
NOT Gate:
IC 74LS04 is hex NOT gate. The o/p of NOF gate is always complementing of i/p.
NAND Gate:
IC 74LS00 is quad 2-i/p NAND gate. It requires 5V DC. The o/p of NAND gate is LOW
when both the inputs are HIGH otherwise I 11GII.
NOR Gate:
IC 74LS02 is quad 2-i/p NOR gate. It requires 5v. The O/p of NOR gate is HIGH when
both e inputs are LOW otherwise LOW.
EX-OR Gate:
IC 74LS86 is quad 2-i/p EX-OR gate. It requires 5V DC. The o/p of EX-OR gate is HIGH when
two different inputs are applied otherwise LOW.
PROCEDURE:
1.+5V DC is applied at 1cc (pin no 14)of each IC w.r.t ground (pin no7).
2. 1/Ps are applied (at pin nos l&2) and output is taken from (pin no 3).
3. I/Ps are applied from toggle switches and o/p is observed at o/p indicators.
PRECATIONS:
1. Avoid loose connections on bread board.
2. Take care while make connections with NOT and NOR gates.
RESULT:

1. IMPLEMENTATION OF ALL INDIVIDUAL GATES WITH

UNIVERSAL GATES NAND & NOR.
AIM:
To develop the AND, OR, NOT gates using NAND and NOR gates.
APPARATUS:
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1. Bread board IC trainer

2. IC 74LS00 (NAND)
3. IC 74LS02 (NOR)
4. Patch cards.
CIRCUIT DIAGRAMS:

0
1

1
0

0
0
1
1

0
1
0
1

0
1
1
1

AND GATE:
A

0
0
1
1

0
1
0
1

0
0
0
1

0
1

1
0

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0
0
1
1

0
1
0
1

0
0
0
1

0
0
1
1

0
1
0
1

0
1
1
1

PROCEDURE:
1. +5V DC is applied at VCC (pin no 14) of each IC w.r.t ground (pin no7).
2. Connect the circuit as shown in circuit diagram
3. Inputs are applied to toggle switches and outputs are connected to output LEDs.
4. Verify the truth tables as shown in the truth tables.
PRECATIONS:
1. Avoid loose connections on bread board.
2. Take care while make connections with VCC and GND.
3. Dont switch ON the kit till all connections are made.
RESULT:

2. VERIFICATION OF DE-MORGAN LAWS

AIM:
Design a circuit for the given conical form, draw the circuit diagram and verify De-Morgan laws.

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APPARATUS:
1. Bread board IC trainer
2. IC 7404, 7408, 7432
3. Patch cards.
THEORY:

CIRCUIT DIAGRAMS:

TRUTH TABLES:
+

0
1 Engineering
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PROCEDURE:
1. +5V DC is applied at VCC (pin no 14) of each IC w.r.t ground (pin no7).
2. Connect the circuit as shown in circuit diagram
3. Inputs are applied to toggle switches and outputs are connected to output LEDs.
4. Verify the truth tables as shown in the truth tables.
PRECAUTIONS:
1. Avoid loose connections on bread board.
2. Take care while make connections with VCC and GND.
3. Dont switch ON the kit till all connections are made.
RESULT:

3. 41 MULTIPLEXER
AIM:
Design a Combinational Logic Circuit for 41 MUX and verify the truth table.
APPARATUS:
1. Bread board IC trainer
2. IC 74153
3. Patch cards.

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THEORY:
Multiplexers are very useful components in digital systems. They transfer a large number
of information units over a smaller number of channels, (usually one channel) under the control
of selection signals. Multiplexer means many to one. A multiplexer is a circuit with many inputs
but only one output. By using control signals (select lines) we can select any input to the output.
Multiplexer is also called as data selector because the output bit depends on the input data bit
that is selected. The general multiplexer circuit has 2n input signals, n control/select signals and
1 output signal.
CIRCUIT DIAGRAM:
PIN DIAGRAM:

TRUTH TABLE:

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PROCEDURE:
1. +5V DC is applied at VCC (pin no 16) w.r.t ground (pin no 8).
2. Connect the circuit as shown in circuit diagram
3. Inputs are applied to toggle switches and outputs are connected to output LEDs.
4. Verify the truth tables as shown in the truth tables.
PRECAUTIONS:
1. Avoid loose connections on bread board.
2. Take care while make connections with VCC and GND.
3. Dont switch ON the kit till all connections are made.
RESULT:

4. 14 DE-MULTIPLEXER
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AIM:
Design a combinational circuit for 14 De-MUX and verify the truth table.
APPARATUS:
1. Bread board IC trainer
2. IC 74156
3. Patch cards.
THEORY:
De-multiplexers perform the opposite function of multiplexers. They transfer a small
number of information units (usually one unit) over a larger number of channels under the
control of selection signals. The general de-multiplexer circuit has 1 input signal, n control/select
signals and 2n output signals. De-multiplexer circuit can also be realized using a decoder
circuit with enable.

PIN DIAGRAM:

TRUTH TABLE:

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PROCEDURE:
1. +5V DC is applied at VCC (pin no 16) w.r.t ground (pin no 8).
2. Connect the circuit as shown in circuit diagram
3. Inputs are applied to toggle switches and outputs are connected to output LEDs.
4. Verify the truth tables as shown in the truth tables.
PRECAUTIONS:
1. Avoid loose connections on bread board.
2. Take care while make connections with VCC and GND.
3. Dont switch ON the kit till all connections are made.
RESULT:

5. RAM-74189
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AIM:
Verify the data read and data write operations for the IC74189.
APPARATUS:
1. Bread board IC trainer
2. IC 74189
3. Patch cards.
4. Connecting Wires
THEORY:
The 74189 is a high speed 64-bit RAM organized as a 16-word by 4-bit array. Address
inputs are buffered to minimize loading and are fully decoded on- chip. The outputs are 3-state
and are in high impedance state whenever the Memory Enable (ME) input is HIGH. The outputs
are active only in the Read mode and the output data is the complement of the stored date. Here
A0-A3 are the address inputs, D1-D4 are data inputs, O1-O4 are inverted data outputs

PIN DIAGRAM:

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MEMORY ENABLE

WRITE ENABLE

OPEARION

All data outputs are high

Read mode )date outputs are
compliment of the RAM
content)
Write mode(data inputs are
writtem on the memory; data
output are compliment of the
Ram content)

PROCEDURE:
This experiment has 3-stages- clearing the memory, data entry(write operation) and
data verification (read operation).
1. The memory enable pin is used to select 1-of-n ICs i.e., like a chip select
signal.
For simplicity, the memory enable pin is permanently held low.
2. The address lines are given through an up/down counter with preset
capability.
3. The set address switch is held high to allow the user choose any location in
the RAM, using the address bots.
4. The address and data bits are used to set an address and enter the data.
5. The Read Write switch is used to write data on the RAM.

Clearing the memory:

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The 74189 is a volatile memory. This means that it will lose the data stored in it, on
loss of power. However this does not means the content of the memory becomes
0h, but not always. The RAM IC 74189 does not come with a Clear Memory signal.
The memory has to be cleared manually.
1.
2.
3.
4.

Position the Stack/Queue switch in the Queue position.

Position the Set Address switch in the 1 position.
Set the address bits to 0h (first byte in the memory)
Position the Set Address switch in the 0 position to disable random access
and enable the counter.
5. Position the Read/ Write switch in the Write position to write data on the
memory.
6. Set the data bits to 0h (clearing the content).
7. Observe that the LEDs (D3 to D0) glow. This is to indicate that the content is
0h. Refer the truth table above and observe that the data outputs of the Ram
will be compliments of the data inputs.
8. Position the Increment/ Decrement switch in the Increment position.
9. Press the Clock to increment the counter to the next address. As the Read/
Write switch is already in the Write position, and the data bits are set to the
0h, the contents in the new location is also placed with 0h.
10.Repeat step 8 until the data in all the memory locations have been cleared.

Design a Gray Code Encoder and interface it to SRAM IC74189 for Write operation display on
7-Segment.
Design a Gray code De-Coder and interface it to SRAM IC74189 for Read operation display it
on 7-Segment.

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9. HALF ADDER AND FULL ADDER USING TWO HALF

ADDERS
AIM:
To construct half-adder and full adder using two half adders and verify its truth table.
THEORY:
Half adder is a logic circuit that adds two bits. The half adder accepts two binary digits on
its inputs and produces two binary digits on its outputs, a sum bit and a carry bit.
A Boolean equations for these outputs are Sum(S)= A B
Carry(C) =AB
The sum output is A XOR B the carry output is A AND B. therefore sum is 1 when A and B are
different carry is 1 when A and B are 1s.
Full adder is a logic circuit that adds two bits. The half adder accepts two binary digits on
its inputs and produces two binary digits on its outputs, a sum bit and a carry bit.
A Boolean equations for these outputs are Sum(S)= A B C
Carry(C)=AB+BC+AC
The sum output is A XOR B the carry output is A AND B. therefore sum is 1 when A and
B are different carry is 1 when A and B are 1s.
EQUIPMENT REQUIRED:
1. IC trainer kit.
2. ICS 7486, 7408, 7432.
3. Connecting wires/ patch chords.
LOGIC CIRCUITS:
LOGIC SYMBOL:

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CIRCUIT DIAGRAM:
HALF ADDER

FULL ADDER
TRUTH TABLE:

TRUTH TABLE:
A

SUM

CARRY

A
0
0
0
0
1
1
1
1

B
0
0
1
1
0
0
1
1

C
0
1
0
1
0
1
0
1

PROCEDURE:
1. +5V DC is applied at VCC (pin no 14) of each IC w.r.t ground (pin no7).
2. Connect the circuit as shown in circuit diagram
3. Inputs are applied to toggle switches and outputs are connected to output LEDs.
4. Verify the truth tables of half adder as shown in the truth tables.
PRECATIONS:
1. Avoid loose connections on bread board.
2. Take care while make connections with VCC and GND.
Dept. of Electronics and Communication Engineering

Sum
0
1
1
0
1
0
0
1

Carry
0
0
0
1
0
1
1
1

P a g e 45

3. Dont switch ON the kit till all connections are made.

RESULT:
The construction of half adder and full adder using half adder and the verification of truth table is
done.

10. BASIC FLIP FLOPS WITH SYNCHRONOUS AND

ASYNCHRONOUS MODES.
AIM:
Verify the truth tables of the basic flip flops with synchronous and asynchronous modes.
EQUIPMENT REQUIRED:
1. IC trainer kit.
2. ICs 7400,7402
3. Connecting wires/ patch chords.
THEORY:
The Asynchronous RS Flip Flop (Latch):
Latch is a type of bi-stable circuit, similar to a flip-flop, which can reside in either of two stable states by
virtue of feedback arrangement. The main difference between latches and flip-flops is in the method used
for changing their state.

The synchronous RS flip flop:

Synchronous flip flop means that this flip flop is concerned with time. Digital circuits can have a
concept of time using a clock signal. The clock signal simply goes from low-to-high and high-tolow in a short period time.
Rs flip flop is also called synchronous flip flop. This means that this flip flop is concern with
time. Digital circuits can have a concept of time using a clock signal. The clock signal simply
goes from low to high and high to low in a short period of time.

NAND AND NOR LATCHES

R

Unpredictable
state
0
1
0
1
1
0
1
0
1
1
No change
Dept. of Electronics and Communication Engineering
0

P a g e 46

R
0
0
1
1

0S
00

0Q

11
10
1

Q
cant say

1 No change
1

0
00
01
1
1
0
1
No change
Unpredictable
state

PROCEDURE:
1. +5V DC is applied at VCC (pin no 14)of each IC w.r.t ground (pin no7).
2. Connect the circuit as shown in circuit diagram
3. Inputs are applied to toggle switches and outputs are connected to output LEDs.
4. Verify the truth tables of NAND and NOR Latches as shown in the truth tables.
PRECATIONS:
1.Avoid loose connections on bread board.
2. Take care while make connections with VCC and GND.
3. Dont switch ON the kit till all connections are made.
RESULT:

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11.

MASTER SLAVE JK FLIP-FLOP

AIM:
Implementations of master slave flip-flop with JK Flip-Flop and verify the truth table for race
around condition.
EQUIPMENT REQUIRED:
1. IC trainer kit.
2. ICs 7476
3. Connecting wires/ patch chords.
THEORY:
A master slave flip flop contains two clocked flip flops. The first is called master and the
second slave. When the clock is high the master is active. The output of the master is set or reset
according to the state of the input. As the slave is inactive during this period its output remains in
the previous state. When clock becomes low the output of the slave flips flop changes because it
become active during low clock period. The final output of master slave flip flop is the output of
the slave flip flop. So the output of master slave flip flop is available at the end of a clock pulse.

PIN DIAGRAM:

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CONNECTION DIAGRAM:

TRUTH TABLE:

PROCEDURE:
1. +5V DC is applied at VCC (pin no 5)of each IC w.r.t
ground (pin no13).
2. Connect the circuit as shown in circuit diagram
3. Inputs are applied to toggle switches and outputs are connected to output LEDs.
4. Connect the NOT gate input to the pin no.1 and output to the pin no.6.
5. Apply the clock signal to the pin no.1
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6. Verify the truth table and of the JK master slave flip-flop.

PRECATIONS:
1.Avoid loose connections on bread board.
2. Take care while make connections with VCC and GND.
3. Dont switch ON the kit till all connections are made.
RESULT:

12.

DECADE COUNTER

AIM:
Design a decade counter and verify the truth table.
EQUIPMENT REQUIRED:
1. IC trainer kit.
2. ICs 7490
3. Connecting wires/ patch chords.
THEORY:
The decade counter (mod-10 counter) is used most often. In order to count from 0 through 9, a
counter with 3 flip-flops is not sufficient. With 4 flip-flops one can count from 0 to15 (16 states).
Out of these 16 states, we should skip any 6 states. In the decade counter, when the output is
1010(for the 10th clock pulse), all the flip-flops should be reset. Thus the outputs Q3 and Q1 are
given directly to the inputs of the AND gate and the outputs Q2 and Q0 are given through
inverters. Therefore, for the 10th clock pulse, the counter output would be 1010 for a moment.
This sends the output of the AND gate to HIGH clearing all the flip-flops. Thus a decade counter
has been developed.
PIN DIAGRAM:
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TRUTH TABLE:

PROCEDURE:
1. Connect the circuit as shown in the figure.
2. The clock pulse is given to pin-14 of IC 7490.
3. The Vcc supply is given to pin-5 of IC 7490.
4. Pin-12 and pin-1 to be shorted.
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5. Pins-2, 3 are Master Reset (MR) inputs and pins-6, 7 are Master Set (MS) inputs.
6. Pins-13, 14 has no connections.
7. Pins-2, 3, 6, 7 are inputs and is always 0 so that it is connected to ground.
8. Pins-12, 9,8,11 are outputs.
9. Feed MR terminal with 1 and MS terminals with 0 then the display shows0.
10.Feed MR terminal with 0 and MS terminals with 1 then the display shows9.
11.Feed MR terminal with 0 and MS terminals with 0,now apply clock then the output varies
between the values 0 and 9.
PRECAUTIONS:
1. Avoid loose connections on the bread board.
2. No connections are to be given to pins-13, 14.
3. Vcc should not exceed +5v.
RESULT:

3. Design the mod 6 counter using D Flip-Flop

4. Construct 4- bit ring counter with T Flip-Flop and verify the truth table.
5. Design a 8-bit right shift register using D Flip-Flop and verify the truth table

Dept. of Electronics and Communication Engineering