Chapter 3

Combinational Circuits

Chapter 3

31 Yes, it matters. The least significant input (input C in our example) must be connected to S 0 , the
next input (input B) to S 1 , and so on.

Chapter 3
32 The AND implementation is shown below:

A B

AND truth table

A B

I0

I1 M
U O
I2 X
I3

S1 S0
F

The NOT implementation is shown below:

A
NOT truth table
A

S1 S0

I0

I1 M
U O
I2 X
I3

Chapter 3

33 The AND implementation is shown below:

New truth table

AND truth table

A B

S0
I0 M
O
I1 U
X

The NOT implementation is shown below:

NOT truth table

A

S0
I0 M
O
I1 U
X

Chapter 3
34 The implementation is shown below:

A B C

I0

I1

I2

I3

I4

I5

I6

I7

S2 S1 S0

M
U
X

Chapter 3

35 The implementation is shown below:

Original truth table

New truth table

A B C

A B

C
A B

C
I0

1
1

0
1

C
C

S1 S0

I1 M
U O
I2 X
I3

Chapter 3
36 The implementation is shown below:

Original truth table

New truth table

A B C

F1

A B

F1

A B
0
1

1
0

C
1

I0

I1 M
U O
I2 X
I3

1
1

S1 S0

F1

Chapter 3

37 The implementation is shown below:

Original truth table

New truth table

A B C

F1

A B

F1

A B
0
1

1
0

0
C

I0

I1 M
U O
I2 X
I3

C
1

S1 S0

F1

Chapter 3

38 We use one 74151 with four inputs: two inputs are given through the XOR gate. The inputs of this
MUX are obtained from the following truth table:

A1

LA

A3

A2

O1

For the second MUX, the output from the first MUX is given as one input. We use the reduction
technique to connect the remaining three inputs (see the truth tables below):

10

Chapter 3

Original truth table

O1

A4

A5

A6

O2

O0

A4

A5

O2

A6

A6
A6

A6

A6

A6

A6

The implementation is shown below:

Reduced truth table

A6

11

Chapter 3
A1 A0

A3 A2

0
1
1
0
1
0
0
1

S2
I0
I1
I2
I3
I4
I5
I6
I7

A5 A4

S1 S0

M O
U
X

Note that we need an inverter to generate A 6 .

A6
A6
A6
A6
A6
A6
A6
A6

S2
I0
I1
I2
I3
I4
I5
I6
I7

S1 S0

M O
U
X

12

Chapter 3

39 In ripple-carry adders, delay in the generation of result is proportional to the number of bits because
of the carry propagation. We use them in practice because they are simple to implement.

Chapter 3

13

310 Carry lookahead adders produce the result in a constant time, independent of the number of bits.
In ripple-carry adders, output delay is proportional to the number of bits due to carry propagation.
However, carry lookahead adders are complex to implement compared to ripple-carry adders.

14

Chapter 3

311 The implementation is shown below:

Halfadder
Cin
Halfadder
A

Sum

Cout

Sum

sum

Cout

Cout

15

Chapter 3
312 The implementation is shown below:

Reduced truth table

Full adder truth table

A B C in Sum C out

A B

Sum Cout

Cin

Cin

Cin

Cin

Cin

Cin

A B

Cin
Cin
Cin
Cin

S1 S0
I 0a
I 1a M
U Oa
I 2a X
I 3a
Ea

A B

0
Sum

Cin
Cin
1

S1 S0
I 0b
I 1b M
U Ob
I 2b X
I 3b
Eb

Strictly speaking, we need an inverter to complement Cin (i.e., to get Cin).

Cout

16

Chapter 3

313 The implementation is shown below:

I3 I2

0
1
1
1

S1 S0
I 0a
I 1a M
U Oa
I 2a X
I 3a
Ea

I3 I2

I1
O1

0
1
1

S1 S0
I 0b
I 1b M
U Ob
I 2b X
I 3b
Eb

Enable
input
Strictly speaking, we need an inverter to complement Cin (i.e., to get Cin).

O0

17

Chapter 3
314 The implementation of (A

Bin) is shown below:

Full subtractor truth table

Reduced truth table

A B Bin Diff Bout

A B

Diff Bout

Bin

Bin

Bin

Bin

Bin

Bin

A B

Bin
Bin
Bin
Bin

S1 S0
I 0a
I 1a M
U Oa
I 2a X
I 3a
Ea

A B

Bin
Diff

1
0
Bin

S1 S0
I 0b
I 1b M
U Ob
I 2b X
I 3b
Eb

Strictly speaking, we need an inverter to complement Bin (i.e., to get Bin).

Bout

18

Chapter 3

315 The truth table is given below. If we eliminate variable D, we need an inverter. Eliminating input
A gives the answer we are looking for. The implementation is shown below:

19

Chapter 3

Segment d truth table

Reduced truth table

Number A B C D segment d

B C D segment d

10

1/0

11

1/0

12

1/0

13

1/0

14

1/0

15

1/0
B C D

1
A
1
1
0
1
1
0

S2
I0
I1
I2
I3
I4
I5
I6
I7

S1 S0

M O
U
X

Segment d

20

Chapter 3

316 The implementation is shown below:

Original truth table

A1 A0 B1 B0

Reduced truth table

A>B

A1 A0 B1

A>B

B0

B0

0
A1 A0 B1

0
0
B0
0
1
0
1
B0

S2
I0
I1
I2
I3
I4
I5
I6
I7

S1 S0

M O
U
X

A>B

21

Chapter 3
317 The implementation is shown below:

Original truth table

A1 A0 B1 B0

Reduced truth table

A<B

A1 A0 B1

A<B

B0

B0

0
A1 A0 B1

B0
1
0
1
0
B0
0
0

S2
I0
I1
I2
I3
I4
I5
I6
I7

S1 S0

M O
U
X

A<B

22

Chapter 3

318 The implementation is shown below:

Original truth table

A1 A0 B1 B0

Reduced truth table

A>B

A1 A0 B1

A>B

B0

B0

0
A1 A0 B1

0
1
B0
1
0
0
0
B0

S2
I0
I1
I2
I3
I4
I5
I6
I7

S1 S0

M O
U
X

A>B

23

Chapter 3
319 The implementation is shown below:

Original truth table

A1 A0 B1 B0

Reduced truth table

C3 C2 C1 C0

A1 A0 B1

C2

C1

C0

0 0 0 0

0 0 0 0

0 0 0 0

B0

0 0 0 0

B0

0 0 0 0

B0 0

0 0 0 1

B0 0

0 0 1 0

B0 B0

0 0 1 1

B0 B0 B0 B0

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 0

0 0 0 0

0 0 1 1

0 1 1 0

1 0 0 1

A1 A0 B1

0
0
0
0
0
1
0
B0

C3

S2
I0
I1
I2
I3
I4
I5
I6
I7

0
0
0
0
0
0
0
B0

S2
I0
I1
I2
I3
I4
I5
I6
I7

S1 S0

M O
U
X

A1 A0 B1

S1 S0

M O
U
X

A1 A0 B1

0
0
0
1
C2
B0
B0
B0
B0

S2
I0
I1
I2
I3
I4
I5
I6
I7

A1 A0 B1

S1 S0

M O
U
X

C3

0
0
B0
C1 B0
0
0
B0
B0

S2
I0
I1
I2
I3
I4
I5
I6
I7

S1 S0

M O
U
X

C0

24

Chapter 3

320 The implementation is shown below:

Original truth table for A/B

A1 A0 B1 B0

Q1 Q0 R1 R0

A1 A0 B1

Q1

Q0

R1

R0

0 0 0 0

0 0 0 0

0 0 0 0

B0 0

0 0 0 0

0 0 0 0

B0 0

0 1 0 0

0 0 0 1

B0 B0 0

0 0 0 1

0 0 0 0

1 0 0 0

0 1 0 0

0 0 1 0

0 0 0 0

1 1 0 0

0 1 0 1

0 1 0 0

A1 A0 B1

0
0
B0
0
0
B0
B0
1

Reduced truth table

S2
I0
I1
I2
I3
I4
I5
I6
I7

0
0
0
Q0 0
0
B0
0
0

0
B0

A1 A0 B1

0
0
0
0
B0
0
B0
0

S2
I0
I1
I2
I3
I4
I5
I6
I7

S1 S0

M O
U
X

A1 A0 B1

S1 S0

M O
U
X

B0 B0 0

S2
I0
I1
I2
I3
I4
I5
I6
I7

A1 A0 B1

S1 S0

M O
U
X

Q1

0
0
0
R1 1
0
0
0
B0

S2
I0
I1
I2
I3
I4
I5
I6
I7

S1 S0

M O
U
X

R0

Chapter 3
Note that we set quotient and remainder to zero when dividing by zero.

25

26

Chapter 3

321 PALs are very similar to PLAs except that there is no programmable OR array. Instead, OR
connections are fixed. As a result of this change to the OR array, there is a loss of flexibility that
sometimes may cause problems but in practice is not such a big problem. But the advantage of
PAL devices is that we can cut down all the OR array fuses that are present in a PLA.

27

Chapter 3
322 The full adder truth table is shown below:

Full adder truth table

A B C in Sum C out
0

The full adder implementation is shown below:

A
B
Cin

P0

P1

P2

P3

P4

P5

P6

P7
Cout
Sum

The full subtractor truth table is shown below:

28

Chapter 3

Full subtractor truth table

A B Bin Diff Bout
0

The full subtractor implementation is shown below:

A
B
Bin

P0

P1

P2

P3

P4

P5

P6

P7
Bout
Diff

29

Chapter 3
323 The implementation is shown in the following figure:
Enable
I1
I2
I3

O1
O2

Note that we need just three gates from the AND array.

30
324 The XOR gates acts as a programmable inverter. It complements the B input for (A
so that we can use the full adder for the subtract operation.

Chapter 3

B ) function

Chapter 3
325 This exercise is deleted. The XOR gate is deleted from the figure.

31

32
326 See Exercise 3-12.

Chapter 3