Documente Academic
Documente Profesional
Documente Cultură
A Report on
Master of Technology in
VLSI Desing and Embedded Sytems
Submitted by
Vasudev S
1RV14LVS33
ARM7TDMI
ARR 7 Overview
The ARM7 was introduced the Thumb 16-bit instruction set providing improved code density
compared to previous designs. The most widely used ARM7 designs implement the ARMv4T
architecture, but some implement ARMv3 or ARMv5TEJ. All these designs use a Von
Neumann architecture, thus the few versions comprising a cache do not separate data and
instruction caches.
Some ARM7 cores are obsolete. One historically significant model, the ARM7DI[1] is notable
for having introduced JTAG based on-chip debugging; the preceding ARM6 cores did not
support it. The "D" represented a JTAG TAP for debugging; the "I" denoted an ICEBreaker
debug module supporting hardware breakpoints and watchpoints, and letting the system be
stalled for debugging. Subsequent cores included and enhanced this support.
It is a versatile processor designed for mobile devices and other low power electronics. This
processor architecture is capable of up to 130 MIPS on a typical 0.13 m process. The
ARM7TDMI processor core implements ARM architecture v4T. The processor supports both
32-bit and 16-bit instructions via the ARM and Thumb instruction sets.
ARM licenses the processor to various semiconductor companies, which design full chips
based on the ARM processor architecture.
ARM7TDMI Introduction
The ARM7TDMI processor is a member of the ARM family of general-purpose 32-bit
microprocessors. The ARM family offers high performance for very low-power consumption
and gate count. The ARM architecture is based on Reduced Instruction Set Computer (RISC)
principles. The RISC instruction set, and related decode mechanism are much simpler than
those of Complex Instruction Set Computer (CISC) designs. This simplicity gives:
A high instruction throughput
An excellent real-time interrupt response
A small, cost-effective, processor macrocell
Memory Access
The ARM7TDMI processor has Von Neumann architecture, with a single 32-bit data bus
carrying both instructions and data. Only load, store, and swap instructions can access data
from memory. Data can be 8-bit bytes, 16-bit halfwords, or 32-bit words. Words must be
aligned to 4-byte boundaries. Halfwords must be aligned to 2-byte boundaries.
Memory Interface
The memory interface of the ARM7TDMI processor enables performance potential to be
realized, while minimizing the use of memory. Speed-critical control signals are pipelined to
allow system control functions to be implemented in standard low-power logic. These control
signals facilitate the exploitation of the fast-burst access modes supported by many on-chip
and off-chip memory technologies.
ARM7TDMI Variants:
ARM&TDMI comes in 2 variants one is ARM7TDMI and the other is ARM7TDMI-S where
S stands for Synthesizable, non-S cores are not physical chips made by ARM. The Atmel
AT91SAM7 series is an example of a hard ARM7TDMI macrocell with customer IP added.
Whereas in S series it can be added peripheral and then go to a Fab to manufacture custom
microcontroller.
ARM7TDMI Core
The ARM7TDMI core is the industrys most widely used 32-bit embedded RISC
microprocessor. Optimized for cost and power sensitive applications, the ARM7TDMI
solution provides the low power consumption, small size and high performance needed in
portable, embedded applications. Key features are:
Hard macrocell
Portable down to 0.13m
Performance up to 120 MIPS (Dhrystone 2.1)
Thumb and ARM instruction sets
Three-stage pipeline
Unified bus architecture
Low power, fully static design
Small die size
Coprocessor interface
EmbeddedICE-RT debug logic
Embedded Trace Macrocell (ETM) interface
ARM7TDMI-S core
ARM7TDMI-S core is the synthesizable version of the ARM7TDMI core with identical
performance levels and feature set. Optimized for flexibility, the ARM7TDMI-S core cuts
time-to-market by reducing development time while allowing for increased design flexibility.