Documente Academic
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8, AUGUST 2010
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AbstractStatic characteristics of an analog-to-digital converter (ADC) can be directly determined from the histogrambased quasi-static approach by measuring the ADC output when
excited by an ideal ramp/triangular signal of sufficiently low
frequency. This approach requires only a fraction of time compared to the conventional dc voltage test, is straightforward, is
easy to implement, and, in principle, is an accepted method as
per the revised IEEE 1057. However, the only drawback is that
ramp signal sources are not ideal. Thus, the nonlinearity present
in the ramp signal gets superimposed on the measured ADC
characteristics, which renders them, as such, unusable. In recent
years, some solutions have been proposed to alleviate this problem
by devising means to eliminate the contribution of signal source
nonlinearity. Alternatively, a straightforward step would be to get
rid of the ramp signal nonlinearity before it is applied to the ADC.
Driven by this logic, this paper describes a simple method about
using a nonlinear ramp signal, but yet causing little influence on
the measured ADC static characteristics. Such a thing is possible
because even in a nonideal ramp, there exist regions or segments
that are nearly linear. Therefore, the task, essentially, is to identify
these near-linear regions in a given source and employ them
to test the ADC, with a suitable amplitude to match the ADC
full-scale voltage range. Implementation of this method reveals
that a significant reduction in the influence of source nonlinearity
can be achieved. Simulation and experimental results on 8- and
10-bit ADCs are presented to demonstrate its applicability.
Index TermsAnalog-to-digital converter (ADC) static characteristics, ADC testing, best segment identification, nonlinear ramp,
quasi-static histogram testing, ramp testing.
I. I NTRODUCTION
HE RESOLUTION and speed of analog-to-digital converters (ADC) are constantly increasing due to advances
in very large scale integration design techniques, manufacturing, and newer architectures. It is well recognized that performance of even the best available high-speed high-resolution
ADC is known to decline when acquiring fast-rising highfrequency nonrepetitive signals. Errors arising due to a lowered
ADC performance can tend to be unacceptable, particularly
when higher accuracies have to be achieved, e.g., when the
ADC is a part of a reference measuring system and/or during
calibration activities. Static and dynamic nonlinearities of the
ADC are accepted indices that assist in the evaluation of
Manuscript received May 15, 2009; revised August 8, 2009; accepted
August 12, 2009. Date of publication October 16, 2009; date of current version
July 14, 2010. The Associate Editor coordinating the review process for this
paper was Dr. Dario Petri.
The authors are with the High Voltage Laboratory, Department of Electrical Engineering, Indian Institute of Science (IISc), Bangalore 560012, India
(e-mail: santoshvora@yahoo.com; satish@hve.iisc.ernet.in).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIM.2009.2031852
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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 59, NO. 8, AUGUST 2010
III. L ITERATURE
Ever since the standards included the conventional dc-based
test, it was quite obvious that the overall time for a static test
was going to be very high for high-resolution ADCs. Search
for alleviating this problem began and led to the following
alternatives, which were, in principle, adhering to the main
philosophy of the dc test, but were innovative and reduced
total test time. Nevertheless, the reduction achieved was not
sufficient enough. In this context, particular mention must be
made about the following methods: 1) the servo-loop-based
method [8]; 2) variable step-size estimation using extrapolated
convergence factor algorithm [9]; 3) small triangular signal
method [10]; and 4) the authors method based on a staircase
signal [11]. As a matter of fact, the superiority demonstrated
by the triangular/ramp-based methods has been instrumental
in their inclusion into the standard [1], and a brief summary
emphasizing their ideas is included.
A method proposed in [7] exploits the noise property of
ADCs and employs an imperfect ramp with a resolution
of about one standard deviation of ADC equivalent noise.
In this method, every ramp application covers a few code
bins. The signal ramps up the discrete steps to cover the
full-scale (FS) range of the ADC. A histogram of the
output codes is generated, and the transfer characteristic
is extracted from the resultant response.
The quasi-static histogram-based ramp vernier test [10],
[12] is now one of the three standard methods [1]. It
employs small-amplitude triangular signals with accurate
dc biases to achieve reduction in ramp nonlinearity. This
The principle of the proposed method depends on the following two basic facts.
1) The percentage linearity of the ramp/triangle waveform
remains practically unaltered irrespective of its amplitude [4]. This implies that the ramp/triangular waveform
amplitude can be increased or decreased without significantly affecting the percentage nonlinearity of the signal.
This fact is verified (and found to be true) for a signal
source, whose result is presented later.
2) A nonlinear ramp waveform can be thought of as a
curve, which can be approximated by a number of short
segments of different lengths. It can easily be visualized
that some of these segments can be much more linear (in
a local sense), compared to the entire curve. Utilizing
this important concept, the most linear segment of the
nonlinear ramp is to be determined. Once such a segment
is identified, its amplitude is suitably altered to match
the FS voltage (FSV) range of the ADC to be tested.
Finally, the ramp signal is provided with an appropriate
dc bias/offset to ensure that only the most linear segment
of the ramp will be seen by the ADC. This is exactly
what is required to measure the static characteristics. As
the ramp amplitude is higher than the ADC FS range,
the ADC converts only the most linear part of the ramp
waveform that falls within its voltage range, while the
remaining parts (lying outside the voltage range) are
clipped and, later, discarded.
Analysis of models for source nonlinearity existing in literature
reveals that certain segments of the ramp could, in fact, be
VORA AND SATISH: ADC STATIC CHARACTERIZATION USING NONLINEAR RAMP SIGNAL
Fig. 1. Nonlinear ramp and its nonlinearity considering the FS signal compared to that due to a segment. The reduction in % NL is evident.
more linear than the entire ramp. (Note: In some models, the
opposite can also be true, i.e., some segments can possess
higher nonlinearity than the entire waveform.) Fig. 1 depicts
this basic idea. From the figure, it is evident that considering
the entire waveform yields a nonlinearity of p%, whereas an
arbitrarily chosen segment has only a small fraction of p%
nonlinearity.
The amount of overdrive to be used is an important parameter
to be selected in an FS ramp-based histogram testing. The
overdrive requirement in a ramp signal is preferred mainly to
minimize the bias error caused by input-equivalent noise. An
overdrive also helps in avoiding influence of high nonlinearity
at the discontinuity. An overdrive, in most cases, equivalent to
three standard deviation of input equivalent noise is found to
be sufficient. Further details can be found in [14]. However,
in the proposed method, only a part of the ramp (i.e., a rampsegment) is being used as the input to the ADC. Parts of the
ramp signal above and below the selected segment are automatically clipped. Hence, the need for the overdrive is eliminated,
unless the best segment is located at the extreme ends of
the ramp.
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(2)
(3)
(4)
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Fig. 2.
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 59, NO. 8, AUGUST 2010
(a) Conventional FS ramp testing. (b) Principle of the proposed method. (Note: Signal source amplitudes for FS range and proposed method are different.)
Fig. 3. Nonlinear ramp signals (exaggerated for the sake of clarity), position of maximum nonlinearity, and best segment are marked for the models described
by (a) (2), (b) (3), and (c) (4).
VORA AND SATISH: ADC STATIC CHARACTERIZATION USING NONLINEAR RAMP SIGNAL
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Fig. 6. (a) INL characteristics due to FS ideal ramp and FS nonlinear ramp
[defined by (3), with p = 0.9 and q = 1.1]. (b) INL characteristics due to FS
ideal ramp and best segment of nonlinear ramp.
due to the ideal ramp, thus proving the potential of the proposed idea.
The source model corresponding to (4) [Fig. 3(c)], as reported in [12], has an almost uniform nonlinearity in all the
segments, as depicted in Fig. 4(c). In such a case, any segment
along the ramp would produce similar results. By raising the
source voltage to six times the ADC input range, an 84% reduction in nonlinearity became achievable. This is a peculiar case,
and such a source should be avoided, unless the best segment
nonlinearity is less than 1 LSB of the ADC. However, for
real sources, in general, the source contribution to nonlinearity
can be further reduced by raising the source amplitude and/or
reducing the ADC input range setting by selecting shorter
segment lengths.
VI. E XPERIMENTAL D ETAILS
Fig. 5. (a) INL characteristics due to FS ideal ramp and FS nonlinear ramp
wave [defined by (2)]. (b) INL characteristics due to FS ideal ramp and best
segment of nonlinear ramp.
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Fig. 8. Static INL characteristics of an 8-bit ADC (DSO-1). (a) True INL
and INL due to the FS nonlinear ramp. (b) True INL and INL due to the best
segment of the nonlinear ramp.
VORA AND SATISH: ADC STATIC CHARACTERIZATION USING NONLINEAR RAMP SIGNAL
Fig. 9. Static INL characteristics of an 8-bit ADC (DSO-2). (a) True INL and
INL due to the FS nonlinear ramp. (b) True INL and INL due to best segment
of the nonlinear ramp.
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Fig. 10. Static INL characteristics of a 10-bit ADC (RTD). (a) True INL and
INL due to the FS nonlinear ramp. (b) True INL and INL due to the best
segment of the nonlinear ramp.
The simulation and experimental results prove that a lowlinearity ramp source with an appropriate dc bias can be effectively employed to estimate the static INL characteristics of an
ADC. Some of the related issues are summarized as follows.
The method proposes to use a low-frequency ramp signal.
However, the change in signal slope when using increased
values of N will not be appreciable since in all the cases, it
will be much less than the device slew rate, thus ensuring
static-ness of the test.
The method excites all the ADC code bins in a single
application when the segment length spans a voltage that
is same as the ADC input voltage range. The sample
requirement and, hence, the test time, is N times the
number of samples required by FS ramp and remains
constant, irrespective of the ADC resolution. It indicates
that the method is time efficient compared to the other
histogram-based ramp test techniques.
The choice of N is governed by the resolutions of the
source and the ADC, or in other words, digital sources
with a resolution better by at least 3 bits is preferred.
Furthermore, with a greater value of N , subject to the
source capability, the segment linearity is expected to
improve.
Once the best segment is identified, acquisition of a large
number of samples is the only component that involves
time since the proposal does not necessitate any major post
processing.
VIII. C ONCLUSION
A simple and effective method has been described by which
a nonideal low-frequency ramp generator possessing more than
the stipulated nonlinearity could still be employed to test an
ADC for estimating its static characteristics. Normally, a source
must have a nonlinearity of less than 1 LSB to qualify for use
in such tests. However, by employing the proposed method,
a significant reduction in source nonlinearity accrues, thereby
rendering it usable. The basic idea is to identify and use only
the most linear segment/region of the nonlinear ramp to test the
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