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I. INTRODUCTION
Manuscript received August 17, 2013; revised October 21, 2013; accepted
November 19, 2013. Date of publication December 18, 2013; date of current
version March 24, 2014. This paper was approved by Guest Editor Hideyuki
Kabuo. This work is supported by CDADIC and partly by SRC.
T. Oh was with the School of Electrical Engineering and Computer Science,
Oregon State University, Corvallis, OR 97331 USA, and is now with Tektronix,
Inc., Beaverton, OR 97077 USA.
H. Venkatram was with the School of Electrical Engineering and Computer
Science, Oregon State University, Corvallis, OR 97331 USA, and is now with
Intel Corporation, Hillsboro, OR 97124 USA.
U. Moon is with the School of Electrical Engineering and Computer Science,
Oregon State University, Corvallis, OR 97331 USA.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2013.2293019
0018-9200 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
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(1)
The amplified time input signal is quantized based on a time reference and the time-domain quantization error can be generated.
Similar to a conventional pipelined ADC in a voltage domain,
this amplification scheme can be applied to process a time-domain signal in a pipelined architecture as shown in Fig. 2. After
) is quantized by the subthe reset phase, the time input (
)
TDC, which generates the digital output and DAC pulse (
is generfor residue generation. As shown in Fig. 3,
from the time reference (
) during
ated according to
) is
the quantization. Then, the time-domain residue (
amplified by 4 with a different current ratio of 4:1 for charging
and discharging in this example. After the zero-crossing com) is generated
parison, the time-domain residue output (
for further quantization in the next pipeline stage. With time-domain residue amplification and its simple open loop configuration, further quantization is possible to extract higher resolution
with relatively low power consumption.
OH et al.: A TIME-BASED PIPELINED ADC USING BOTH VOLTAGE AND TIME DOMAIN INFORMATION
963
Fig. 5. Conventional
Conversion
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Fig. 6. Proposed
for zero-crossing, the time-domain output at zero-crossing is always linear regardless of the amplifier non-idealities, as long as
the current source meets linearity requirement [13]. The residue
output after the amplification phase in this case is derived in the
following equation:
(4)
As reflected in (4), the residue output in voltage domain is still
affected by the amplifier characteristics. However, the time-domain output at zero-crossing in the discharging phase is independent of the amplifier characteristics as shown in (5):
(5)
is linear regardless of the amplifier
As a result, the output
characteristics in the proposed - conversion. An intuitive
way to understand (5) is to realize that the zero-crossing detection by the comparator is always detected at the same voltage
(for the differential zero). There is no signal dependent amplifier error in the time-domain output at the zero-crossing detection. Therefore, a low gain nonlinear amplifier can be used in
the proposed - conversion. The bandwidth of the amplifier
affects the time delay during the discharging phase, which is
largely signal independent in a relatively high bandwidth amplifier. Despite being a three phase operation, the time required
for the voltage domain residue amplification can be minimized.
The amplification phase does not require a fully settled residue
output in voltage domain. Fig. 7 shows the linearity simulation
of the proposed - conversion which compares the linearity
OH et al.: A TIME-BASED PIPELINED ADC USING BOTH VOLTAGE AND TIME DOMAIN INFORMATION
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To solve the problem efficiently, a hybrid time-domain quantization stage is proposed as shown in Fig. 9. The proposed hybrid stage employs a capacitor DAC for charge subtraction instead of using a time-domain DAC pulse. The linearity of DAC
in this architecture only depends on capacitor matching, which
is not difficult to achieve. Time-domain error sources such as
jitter or delay cell mismatch now only affect the linearity of
sub-TDC and it is relaxed with the given redundancy between
stages. With a conventional error correction scheme which usually is employed to correct comparator error in a pipelined ADC,
the time reference error up to
can be corrected by
the 1 bit redundancy between the pipeline stages [17]. Fig. 10
illustrates the operation of the proposed stage. Initially, all capacitors are reset to the positive reference. In charging phase,
capacitors are charged by a fixed current (4I) based on the time
input. At the same time, sub-TDC quantizes the time input and
generates a corresponding thermometer code for the DAC operation, sequentially. In next phase, the stored charge on the capacitors (which represents the residue) is discharged by a different current ratio (I) for residue amplification. After the zerocrossing, the amplified time residue output is passed on to the
next pipelined stage.
The comparison of two different time amplification methods
is shown in Fig. 11. In case of the amplification using a dual
slope (charging and discharging), the linearity of the current
source is limited (or signal swing is reduced) and the residue
gain is not well defined due to the different type of current
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sources (PMOS and NMOS type) for the amplification. However in a single slope case (using two charging slopes) similar
to [8], the same type of current source is used for amplification.
As a result, the residue gain only depends on the matching of the
same type of current sources which is well defined with careful
layout. In this case, the linearity of the current source can be
maximized with a proper control of the output common mode.
Although twice the capacitors are required in the single slope
case, it provides many advantages in real implementation which
uses a low supply voltage. In case of the amplification using a
dual slope, it is difficult to get a required signal swing with high
linearity, which results in an increased capacitance for the same
SNR with a smaller signal swing. Therefore, the amplification
method using the single slope is employed in this work.
Because the first stage residue amplifier is the most power consuming block in conventional pipelined architecture, this simple
amplifier structure incorporating small load capacitance reduces
ADC power consumption significantly. The power consumption
of the amplifier is further reduced by turning it off asynchronously after zero-crossing.
OH et al.: A TIME-BASED PIPELINED ADC USING BOTH VOLTAGE AND TIME DOMAIN INFORMATION
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Fig. 15. Switched charge pump (drawn PMOS current sources only for simplicity).
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Fig. 17.
In the proposed ADC, the equivalent voltage-to-time conversion gain depends on the capacitance and current value with
a given voltage reference and time reference for discharging.
However these values are not well defined in real implementation. The - tracking circuit shown in Fig. 17 provides a
coarse current reference for MDAC and TSTGs. With a same
voltage and time reference, the tracking circuit tracks the correct current value for discharging for a replica capacitor used in
MDAC and TSTG1. However due to the limited matching accuracy of this replica path, the - gain is also tuned externally,
and the finite gain error after tuning is corrected by a simple
off-chip radix-based calibration in digital domain [19].
Fig. 18. Integrated noise model from the current source in MDAC.
V. CONSIDERATION OF NON-IDEALITIES
A. Integrated Noise From Current Source
In the proposed ADC, the integrated noise from the current
source in the first stage MDAC dominates the noise performance, which is directly related to the ADC resolution. Fig. 18
shows the equivalent noise model to analyze the integrated noise
from the current source of MDAC. If we assume the bandwidth
of the amplifier is much higher than the switching time for discharging (
), the voltage accumulated on feedback
capacitor
is approximated as follows:
(6)
where the power spectral density of the current source is
. Therefore, the equivalent input-referred noise is
derived in following equation by dividing the signal gain:
(7)
and
is the residue gain of the
Because the ratio between
MDAC, this equation can be re-formulated as follows:
(9)
is
, is the residue gain (
),
where
and
is the effective voltage (or overdrive voltage) of the
current source. From (9), the input referred noise from current
source is affected by the sampling capacitance, the residue gain,
and the ratio between the ADC reference range (or signal range)
and the effective voltage of the current source. For given signal
swing, this noise can be minimized by maximizing effective
voltage of the current source for a given supply voltage. Also,
this noise can be reduced by increasing the residue gain (by resolving more bits from the first stage). Even though the proposed ADC requires a slightly larger sampling capacitance than
the conventional pipelined ADC for the same SNR performance
due to this additional noise from the discharging current source,
the benefits of the proposed architecture in terms of the power
consumption and linearity in real implementation are significant, especially under the condition with low supply voltage.
OH et al.: A TIME-BASED PIPELINED ADC USING BOTH VOLTAGE AND TIME DOMAIN INFORMATION
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m CMOS process
Fig. 19. Residue plot of TSTG (a) with comparator delay and (b) with delay
correction by injecting time offset in time reference.
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TABLE I
PERFORMANCE COMPARISON.
Fig. 22. Measured output spectrum (
factor of 4).
, downsampled by a
TABLE II
PERFORMANCE SUMMARY OF THE PROTOTYPE ADC.
is 38.2 fJ/conversion-step. Table I compares the recently published state of the art Nyquist ADC with maximum SNDR
above 65 dB, sampling rate above 50 MHz, and Walden FOM
below 100 fJ/C-S [20][24]. As shown in Table I, the proposed
ADC shows a competitive FOM among the recently published
ADCs with similar specifications. The FOM of the proposed
ADC can be improved further with a more advanced CMOS
process. Fig. 25 shows the power breakdown and Table II
summarizes the measured performance of the prototype ADC,
respectively.
VII. CONCLUSION
A pipelined ADC incorporating a time-based pipeline architecture is presented in this paper. The proposed ADC uses both
OH et al.: A TIME-BASED PIPELINED ADC USING BOTH VOLTAGE AND TIME DOMAIN INFORMATION
time domain and voltage domain information in analog-to-digital conversion. By using the pipelined TDC as a backend stage
of the ADC, as well as a pipeline stage in voltage domain as
the first stage, the proposed architecture achieves power efficiency and the linearity. The proposed ADC is amenable to
process scaling and uses a scaling-friendly amplifier with minimum dc gain and maximum signal swing (in the first stage
MDAC for - conversion). The power efficiency and linearity of the ADC are further improved by the proposed hybrid
time-domain pipeline stage which uses a simple charge pump
and capacitor DAC for the time residue generation.
ACKNOWLEDGMENT
The authors would like to thank Texas Instruments for the
chip fabrication.
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Taehwan Oh (S09M14) received the B.S. and
M.S. degrees in electronic engineering from Sogang
University, Seoul, Korea, in 2000 and 2002, respectively, and the Ph.D. degree in electrical engineering
and computer science from Oregon State University,
Corvallis, OR, USA, in 2013.
He is currently an analog design engineer at
Tektronix, Inc., Beaverton, OR, USA. From 2002
to 2009, he was with Samsung Electronics, Yongin,
Korea, where he was working on analog-to-digital
converters and analog front-end for various applications. His research interests include high performance analog-to-digital
converters and analog front-end for signal interface in many applications.
Hariprasath Venkatram (S08M14) received the
B.Tech. and M.Tech. dual degrees in electrical engineering from Indian Institute of Technology, Madras,
India, in 2008, and the Ph.D. degree in electrical engineering and computer science from Oregon State
University, Corvallis, OR, USA, in 2013.
He is currently a research scientist at Intel Corporation, Hillsboro, OR, USA. He has received the
Professor Achim Bopp Award from IIT-Madras and
a finalist in the Broadcom Foundation University
Research competition. His research interests include
data converters, timing circuits, amplifiers, filters and mixed signal design. He
is a member of Solid-State Circuits and Circuits and Systems Society.
Un-Ku Moon (S92M94SM99F09) received
the B.S. degree from the University of Washington,
Seattle, WA, USA, in 1987, the M.Eng. degree from
Cornell University, Ithaca, NY, USA, in 1989, and
the Ph.D. degree from the University of Illinois,
Urbana-Champaign, IL, USA, in 1994.
He has been with the School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR, USA, since 1998. Before joining
Oregon State University, he was with Bell Laboratories from 1988 to 1989, and from 1994 to 1998. His
technical contributions have been in the area of analog and mixed-signal circuits including high linearity filters, timing recovery, PLLs, data converters, and
low-voltage circuits for CMOS.
Dr. Moon served as the Editor-in-Chief of the IEEE JOURNAL OF SOLIDSTATE CIRCUITS and the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II,
as a Distinguished Lecturer of the IEEE Solid-State Circuits Society, as an Associate Editor of the IEEE JOURNAL OF SOLID-STATE CIRCUITS and the IEEE
TRANSACTIONS ON CIRCUITS AND SYSTEMS II, and as the Deputy Editor-inChief of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II. He served on
governing boards of both the IEEE Solid-State Circuits Society (SSCS AdCom)
and the IEEE Circuits and Systems Society (CASS BoG) as the SSCS representative to CASS. He also served as a Technical Program Committee member of
the IEEE International Solid-State Circuits Conference, the IEEE VLSI Circuits
Symposium, and the IEEE Custom Integrated Circuits Conference. He currently
serves on the Executive Committee of the IEEE Symposia on VLSI Technology
and Circuits.