Title:

IMPLEMENTATION OF COMMUNICATION USING CYCLIC

REDUNDANCY CHECK

Author:

JYOTI WADHWANI, NITIN NARKHEDE

Journal:

INTERNATIONAL JOURNAL OF EMERGING TECHNOLOGY AND

ADVANCED ENGINEERING

Volume:

VOLUME 3, ISSUE 7, JULY 2013

Date:

JULY 2013

ISSN:

2250-2459

Abstract:
Cyclic redundancy checking is a method of checking for errors in data that has
been transmitted on a communications link. The Cyclic Redundancy Check (CRC) is an
efficient technique for detecting errors during digital data transmissions between a
source and a destination. It is designed to be fast and easy to implement in a hardware
by using logic XOR (exclusive OR) gates and shifters. The algorithm provides very good
protection from burst errors, which are typical for transmission lines. Thanks to easy
implementation, it is useful for error detection but cannot safely rely on data integrity
verification.
This paper describes the mathematical basis behind CRC in an intuitive fashion
and then explains Algorithm for the serial CRC generating and checking at both
transmitter and receiver side. This includes analyzing various types of error during
transmission.

Insight:
This paper focuses on the application of Cyclic Redundancy Checking (CRC)
on the checking for errors in data in a communications links. The paper thoroughly
discussed that Cyclic Redundancy Checking is fast reliable when it comes to error
detection, though it cannot be relied with the integrity of data. It was also thoroughly
discussed that Cyclic Redundancy Checking uses the implementation of logic XOR
gates and shifter.
The paper concludes that Cyclic Redundancy Checking can be used in
communication systems where large data packages are transmitted, since the process
of checking is fast. It also concludes that the Cyclic Redundancy Checking was
executed well even with the 32-bit datas.

Title:

PARALLEL COMPUTATION OF CRC USING SPECIAL

GENERATOR POLYNOMIALS

Author:

HAMED SHEIDAEIAN, BEHROUZ ZOLFAGHARI

Journal:

INTERNATIONAL JOURNAL OF COMPUTER NETWORKS &

COMMUNICATIONS

Volume:

VOLUME 4, NO. 1

Date:

JANUARY 2012

ISSN:

2410-0595

Abstract:
CRC (Cyclic Redundancy Check) is an error detection method commonly used in
data communication systems, computer networks and storage environments. In this
method, the transmitter divides the message by an agreed upon polynomial called the
generator and concatenates the calculated residue to the message. The properties of
the generator determine the range of errors which are detectable in the receiver side.
The division operation is currently performed using serial circuits called Linear
Feedback Shift Registers especially in the Ethernet network access protocol.
Developing methods for parallel computation of the residue makes CRC suitable for
higher layer protocols and software applications. This paper studies a case for parallel
CRC computation using special generators which have special multiples called OZO
(One-Zero-One) polynomials are divisible. We first provide a systematic approach to
finding such polynomials and then design and evaluate the algorithm and the hardware
required to perform the parallel division.

Insight:
This paper focuses on the application of Cyclic Redundancy Checking (CRC)
as the main method used in error detection in data communication systems, computer
networks and storage environments. It was explained that in Cyclic Redundancy
Checking, the transmitter divides the message by an agreed upon polynomial called the
generator and concentrates the calculated residue to the message.
It was concluded in the paper that LFSRs are used to implements Cyclic
Redundancy Checking computations. Linear Feedback Shift Registers are sequential

circuits in which the output of the last flip flop is fed to the input of the first flip flop
through a number of XOR gates.
Title:

DATA LINK LAYER DESIGNING ISSUES: ERROR CONTROLA

ROADMAP

Author:

MONIKA SINGH & RUHI SAXENA

Journal:

GLOBAL JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY: C

SOFTWARE & DATA ENGINEERING

Volume:

VOLUME 14 ISSUE 8

Date:

2014

ISSN:

0975-4350

Abstract:
Different networks are used to transfer data from one device to another with
acceptable accuracy. For most applications, a system must guarantee that the data
received are identical to the data transmitted. Transmission media are most error-prone
link. In a network, the capacity of nodes is different and the rate at which the sender is
sending data might not be the same rate at which the receiver accepts it. In this paper,
we discuss on designing issues of data link layer. The primary focus is on various error
detecting and controlling mechanisms.

Insight:
This paper focuses on designing issues commonly on a Data link layer, The Error
Control. In CISCO, the Data Link Layer refers to the provision of reliable transit of data
across a physical network link, where Error Control takes place. The paper introduces
four redundancy checking mechanism Vertical Redundancy Checking (VRC),
Longitudinal Redundancy Checking (LRC), Cyclical Redundancy Checking (CRC) and
Checksum.
This paper concludes that all four methods of error detection has its own
advantages and its own mechanism to detect error. However, in particular, the paper
discussed that Vertical Redundancy Checking is simple and can detect all single-bit
error. Therefore, It tells that VRC checks and can detect even a small error in a data. On
the other hand, Cyclical Redundancy Checking has a very good performance in

detecting single bit errors, double errors an odd number of errors and burst errors, while
checksum is not as efficient as the CRC.ce