Documente Academic
Documente Profesional
Documente Cultură
By D.R. Sentz
January, 2015
In 1976-77 I constructed an audio cassette interface for my
homebrew computer. I used the Bit Boffer design by Don
Lancaster, as published in the March 1976 issue of BYTE magazine,
plus the read/write time delay circuits and remote ON/OFF
control circuit described in that same issue of BYTE, in the
article The COMPLEAT Tape Cassette Interface by Jack Hemenway.
My Tx clock circuit is slightly different from the Hemenway
article, per the Bit Boffer requirement for 19200 Hz. Bit
Boffer provides the divide-down to 4800 Hz for the ACIA.
My tape recorder did not have an Aux input, so I added a
20kohm gain control to reduce the Bit Boffers output voltage to
just a few millivolts, for the dynamic microphone input.
00010
00020
00030
00040
00050
00060
00070
00080
00090
00100
00110
00120
00130
8010
00140
8011
00150 A002
00160 A002 0002
00170 A004 0002
00190
00200
00210
00220
00230
00240
00250
00260
00270
00280
00290
00300
00310
00320
00330
00340
00350
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00370
00380
00390
00400
00410
00420
00430
00440
00450
00440
A048
A048
A04A
A04D
A04F
A051
A054
A057
A059
A05B
A05D
A060
A062
A065
A067
A068
A06A
A06D
A06F
A071
A072
A075
A077
A079
A07A
A07C
A07F
A04A
FE A002
8D 2B
C6 1D
F7 8010
F6 8010
C5 08
26 F9
A6 00
B7 8011
8D 10
BC A004
27 03
08
20 F1
B7 8011
8D 03
8D 09
3F
F6 8010
C5 02
27 F9
39
C6 5F
F7 8010
39
NAM
OPT
PUNCHER2
O,S,NOG OBJECT TAPE AND SYMBOLS
*
* CASSETTE PUNCHER PROGRAM BY DONALD R. SENTZ
* 1977 ORIGINAL, UPDATED JANUARY 2015
* THIS PROGRAM IS USED TO WRITE MEMORY
* TO THE AUDIO CASSETTE UNIT WHICH
* IS INTERFACED TO THE ACIA CHIP ON THE
* MEK6800 BOARD. ENTER START ADDRESS IN
* A002-03, AND END ADDRESS IN A004-05.
* THIS PROGRAM WAS PREPARED USING THE
* RESIDENT EDITOR/ASSEMBLER MP-E.
ACIACT EQU
$8010
ACIA CONTROL REGISTER
ACIADT EQU
$8011
ACIA DATA REGISTER
ORG
$A002
BEGAD RMB
2
START ADDRESS
ENDAD RMB
2
END
ADDRESS
LOOP1
LOOP2
ENDCH
WAIT
RESET
ORG
FDB
LDX
BSR
LDA
STA
LDA
BIT
BNE
LDA
STA
BSR
CPX
BEQ
INX
BRA
STA
BSR
BSR
SWI
LDA
BIT
BEQ
RTS
LDA
STA
RTS
END
B
B
B
B
A
A
$A048
$A04A
BEGAD
RESET
#$1D
ACIACT
ACIACT
#8
LOOP1
0,X
ACIADT
WAIT
ENDAD
ENDCH
GO INITIALIZE ACIA
START MOTOR, DEFINE FORMAT
8 BITS, ODD PARITY, 1 STOP
LOOP2
ACIADT
WAIT
RESET
ARE WE DONE?
WAIT UNTIL ALL BITS ON TAPE
POINT TO NEXT MEM LOC.
AND KEEP PUTTING
THIS WRITE IS NECESSARY SO
THAT THE PRECEDING WRITE
OP. COMPLETES(JAN/2015)
B
B
ACIACT
#2
WAIT
B
B
#$5F
ACIACT
S00B000050554E4348455232AD
S11EA048A04AFEA0028D2BC61DF78010F68010C50826F9A600B780118D10BC94
S11EA063A00427030820F1B780118D038D093FF68010C50227F939C65FF78008
S105A07E103993
S9
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
8010
00015
8011
00016
E0E3
00017 A002
00018 A002 0002
00019 A004 0002
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040
00041
00042
00043
00044
00045
00046
00047
00048
00049
A014
A014
A016
A019
A048
A048
A04A
A04D
A04F
A051
A054
A057
A059
A05B
A05E
A060
A062
A064
A066
A068
A069
A06C
A06E
A071
A073
A075
A078
A079
NAM
OPT
C6 5F
RESET
F7 8010
39
A04A
FE A002
8D C5
C6 1D
F7 8010
F6 8010
C5 04
26 F9
F6 8010
C5 01
27 F9
C5 70
27 03
8D AC
3F
B6 8011
A7 00
BC A004
26 05
8D 9F
7E E0E3
08
20 E0
LOADER
O,S,NOG
LOOP1
LOOP2
CONT
CONT2
ORG
LDA
STA
RTS
ORG
FDB
LDX
BSR
LDA
STA
LDA
BIT
BNE
LDA
BIT
BEQ
BIT
BEQ
BSR
SWI
LDA
STA
CPX
BNE
BSR
JMP
INX
BRA
END
B
B
B
B
B
B
B
B
B
A
A
$A014
#$5F
ACIACT
$A048
$A04A
BEGAD
RESET
#$1D
ACIACT
ACIACT
#4
LOOP1
ACIACT
#1
LOOP2
#$70
CONT
RESET
ACIADT
0,X
ENDAD
CONT2
RESET
CNTRL
LOOP2
GO INITIALIZE ACIA
START MOTOR, DEFINE FORMAT
8 BITS, ODD PARITY, 1 STOP
DATA CARRIER DETECT?
IF NOT, KEEP CHECKING
RCV DATA REG. FULL?
IF NOT, KEEP CHECKING.
ANY ERROR FLAGS SET?
IF NOT, GO READ DATA.
STOP MOTOR
EXIT IF ANY READ ERROR
READ DATA BYTE
PUT IT TO LOC(X)
WAS IT THE LAST BYTE?
IF NOT, CONTINUE
ELSE STOP MOTOR
AND NORMAL EXIT
POINT TO NEXT LOC
AND CONTINUE READING TAPE
THE END