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1.
INTRODUCTION
(1)
IB
IX
VX
IZ
X
Z+
CCCII+
IY
VY
IZ
Z-
ACTA ELECTROTEHNICA
[14]
a. 002 or 112
VX VY 0 or VX VY V , I Z 0 ;
b.
(a)
VX
VY
VZ
c.
VX
VY
VZ
0
1
Delay
Average Power
Biasing
Peak Current
Offset Current
NMOS
PMOS
(4)
TABLE 3
Performance Details of the XOR of Fig.3(a)
3.
012
1
1
(3)
V ;
VX 0 , VY V , I Z
RX
TABLE 2
Bipolar XOR characteristic
(b)
102
V ;
VX V , VY 0 , I Z
RX
TABLE 1
Unipolar XOR Characteristic
(2)
RZ
4.
30ps
64W
= 1V
13A
50.0nA (002)
3A
(112)
0.1m/0.1m
0.3m/0.1m
50K
(optional)
(b)
(c)
Fig. 3. (a) XOR characteristic of the CCCII; (b) Bipolar
representation of the XOR truth table; (c) Simulation results.
TABLE 4 :
Functional Details of XOR Realization of Fig. 8. Here, LOGIC 1
= VDD = V; LOGIC 0 = V; I=V/RX
A
IZ
2I
2I
IA
IB
IZ
2I
2I
(a)
(a)
148W
IZ
13A
Peak
Current
Offset Current
(b)
Fig. 5. (a) XOR realization Topology for voltage inputs; (b) output
current signal for input voltage combination as per Table 3.
TABLE 5
Performance details of the proposed XOR in Fig.4(a)
Delay
Average Power
(62W per CCCII)
Biasing
60ps
124W
= 1V
Peak Current
8A
Offset Current
0.0A
N/PMOS :
0.1m/0.1m
5.
Average Power
(74W per CCCII)
Biasing
= 1V
0nA (002)
6nA (112)
N/PMOS :
0.1m/0.1m
Technology
45nm CMOS
t tDELAY
(5)
ACTA ELECTROTEHNICA
REFERENCES
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. Both
and
is
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CONCLUSION
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