Bipolar IC process

The major steps in the IC bipolar process are listed in the diagram below.
Crystal growth

Wafer slicing and polishing

Buried layer

Epitaxial growth

Isolation diffusion

Base diffusion

Emitter and collector diffusion

Open contact windows

Interconnect and metallization

Separate and mount chips

Wirebond connction to header

Seal package
Bipolar IC Fabrication Steps
The starting material is a p-type single crystal silicon wafer having 5 to 20 ohm-cm resistivity
and thickness of approximately several hundred micrometers. The diameter can be 50, 75,
100, 125, or 150 mm. The most standard size is 100 mm or about 4 inches
1. A thin layer of SiO2 is formed on all surfaces of a p-type silicon wafer by exposing it
to oxygen or water vapour in an electric furnace. The first masking step defines the
area for n+ buried layers, (also called sub-collector). The function of this layer is to
reduce the collector resistance of the transistor. The SiO 2 is removed in these areas by
chemical etching. Thermal diffusion or ion implantation forms the desired heavily
doped n-type, that is, n+ buried layer region. The resulting structure is shown in the
figure below.
2. The SiO2 masking layer is removed, exposing the entire silicon wafer surface. By
epitaxial deposition, an n-type layer is grown, over the entire surface. It is n-type
single-crystal silicon 2 to 5 micro meter thick with its resistivity in the range of 0.1 to
1 ohm-cm. During the epitaxial process, the n-type dopant previously introduced in
the buried layer areas diffuses in all directions. This is shown in the figure below.
3. The wafer with the epitaxial layer is then oxidized at an elevated temperature in an
H2O ambient. This forms a layer of SiO 2, approximately 0.5 micro meters thick over
the entire surface of silicon. A second masking step defines a border completely
enclosing n-type islands of silicon that are to be electrically isolated collectors of
transistors. P-type diffusion into the border areas is continued until the entire epitaxial
layer has been penetrated, as shown in the figure below. Thus, islands of n-type
silicon are bounded on all sides by p-type Si. Isolation is achieved by applying
voltages such that this p-n junction is always reverse- biased. The p-type diffusion
uses boron as impurity. A new layer of thermal oxide is grown over the isolation
areas.
4. The third masking step defines base regions of n-p-n transistors. Patterns of resistors
are formed simultaneously in separate isolated n-type regions. Boron is again diffused
(but this time not as deeply) or implanted to forms bases and resistors. The n-type
collector is converted to p-type when the density of p-type impurities exceeds that of
n-type impurities. The resulting structure is shown in figure below.
5. The fourth photolithographic step defines n-type transistor emitters and n-type regions
for low resistance contacts to collector regions, as in the figure below. Again
conversion of p-type base to n-type requires impurity compensation.

6. An oxide is again thermally grown over the entire wafer and via photolithography, (5 th
mask) those regions where contact is to be made to the silicon are defined. Metal (AI)
is then deposited by vacuum evaporation. The photolithographic process (6th mask) is
then used to define the appropriate metallization inter-connection pattern, and the
remaining metal is removed. The figure below shows the contact areas (defined by 5 th
mask) to collector, base, and emitter. The 6thmasking step is not shown in figure.

Bipolar IC Manufacture Steps

At this point, the ICs are in finished state. However before finished form, a protective
passivating layer using glass is deposited over the entire wafer. This is known as die
passivation or scratch protection, or glassivation. This protects the surface of the wafer from
contamination. Glassivation is done using chemical vapour deposition. This added step
paysoff in protection before and after packaging, in higher yields and in better reliability.
A final masking step removes the above insulating layer over the pads where contacts will be
made. Now the IC chip undergoes a probe test. This is necessary because there are many
faulty chips after such highly complicated fabrication steps. The probe test is automatically
carried out by contacting the pads of every chip with microelectrode probes. Registration of
each chip with respect to the probes is done automatically by final mechanical adjustment.
The chip is then tested using a set of test vectors, which consist of a sequence of input
voltages, stimuli (to chip input pads) and expected output voltage responses (from chip output
pads) that have been previously generated by the design engineer. If the chip passes all test
vectors, namely all outputs provide the correct results for all input stimuli then the probes are
automatically stepped to the next chip position and all test vectors are applied to that chip.
This process is repeated until all chips have been tested. Chips that failed to pass all test
vectors are marked with an ink dot. Due to computer controlled operation of wafer probe
equipment, upto 16000 test vectors are tested for each chip of a wafer in some minutes.

Faulty chips will be thrown away later. Now, the entire wafer is broken into individual chips.
This is discussed below.

Chip Separation
The entire wafer is divided up into individual chips by scribe-and-break operation using
any one of the following ways.

Diamond-tipped scribe

High-intensity laser beam (laser scribing), or

High-speed circular saw

Since this process is similar to glass culling it is called scribing and breaking. In the diamondtipped scribe method, the grooves are very shallow. In laser scribing method, the grooves are
somewhat deeper, and may extend more than halfway through the wafer. In the high-speed
circular saw method, the wafer will have a pattern of orthogonally oriented scribing streets
which are kept clear of oxide and metal and are aligned along certain crystallographic
directions to promote the easy and smooth cleavage of the wafer.
A popular process for chip separation is to use a wafer saw to cut entirely through the wafer.
The wafer is mounted on adhesive-coated tape prior to the sawing operation so that after
sawing the chips will remain in matrix form for convenience in further operations.
Faulty chips are identified using probe test mentioned above. Hence, only good chips are
mounted in containers. The chips are bonded to either metal headers or ceramic substrate.
The metal headers are usually gold-plated Kover. Kovar is an iron-nickel-cobalt alloy whose
thermal expansion coefficient is a close match to that of silicon. The headers axe heated to
temperatures in the range of 400 to 420C in an inert-gas atmosphere (N 2 or a mixture of
about 90% N2 and 10% H2). The chips are then bonded to the headers by means of the
formation of a gold-silicon alloy that results in a good mechanical bond and a low-resistance
electrical contact. This contact will be the substrate of the IC chip. The same process is used
for discrete components, such as transistor. In that case the contact will be the collector of the
transistor.

Lead Bonding and Encapsulation

Connecting the pads (metallised contact areas) to the terminal (that is, pins) of container with
gold (or aluminium) wires is referred to as bonding. For this purpose small-diameter (20 to 40
micro meters) gold wires are used. Aluminium wire is used especially for high-current power
devices, where large-diameter round or flat ribbon leads may be used. Take a look at the
figure below.

Lead Bonding
The IC chip is now encapsulated in a metal, ceramic or plastic package. The plastic package
is the lowest in cost, but the metal and ceramic package offer the advantage of providing a
hermetic seal and a higher operating temperature range.