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Data Sheet
FEATURES
APPLICATIONS
Agile LO frequency synthesis
Programmable clock generator
FM chirp source for radar and scanning systems
Test and measurement equipment
Acousto-optic device drivers
Polar modulator
Fast frequency hopping
REF CLK
MULTIPLIER
SERIAL OR PARALLEL
DATA PORT
12-BIT DAC
10836-001
LINEAR
SWEEP
BLOCK
Figure 1.
Rev. D
Document Feedback
AD9914
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
AC Specifications.......................................................................... 5
REVISION HISTORY
1/14Rev. C to Rev. D
Changes to Digital Timing Specifications Parameter, Table 2 ..... 5
Changes to Figure 23 .......................................................................15
Change to DAC Calibration Output Section ...............................20
Change to Address 0x02, Table 14.................................................34
Changes to Table 17 .........................................................................41
11/13Rev. B to Rev. C
Changes to Table 2 ............................................................................. 5
Change to Programming and Function Pins Section .................30
7/13Rev. A to Rev. B
Change to CMOS Logic Outputs Parameter, Table 1 ................... 4
Changes to Table 2 ............................................................................. 7
Changes to DDS Core Section .......................................................19
Rev. D | Page 2 of 48
Data Sheet
AD9914
GENERAL DESCRIPTION
AD9914 via a serial or parallel I/O port. The AD9914 also
supports a user defined linear sweep mode of operation for
generating linear swept waveforms of frequency, phase, or
amplitude. A high speed, 32-bit parallel data input port is
included, enabling high data rates for polar modulation
schemes and fast reprogramming of the phase, frequency,
and amplitude tuning words.
AD9914
OUTPUT
SHIFT
KEYING
OSK
DRCTL
DRHOLD
2
DIGITAL
RAMP
GENERATOR
DROVER
3
PS[2:0]
I/O_UPDATE
32
INTERNAL
PROGRAMMING
REGISTERS
DDS
DAC_RSET
AMPLITUDE (A)
A
Acos (t + )
PHASE ()
DATA
ROUTE
FREQUENCY ()
Asin (t + )
AND
PARTITION
CONTROL
CLOCK
DAC
12-BIT
SYSCLK
AOUT
AOUT
REF_CLK
REF_CLK
PLL
D0 TO D31
4
F0 TO F3
POWERDOWN
CONTROL
MULTICHIP
SYNCHRONIZATION
Rev. D | Page 3 of 48
10836-002
MASTER_RESET
LOOP_FILTER
SYNC_IN
SYNC_OUT
EXT_PWR_DWN
SYNC_CLK
AD9914
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
AVDD (1.8V) and DVDD (1.8V) = 1.8 V 5%, AVDD (3.3V) and DVDD_I/O (3.3V) = 3.3 V 5%, TA = 25C, RSET = 3.3 k,
IOUT = 20 mA, external reference clock frequency = 3.5 GHz with reference clock (REF CLK) multiplier bypassed, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SUPPLY VOLTAGE
DVDD_I/O
DVDD
AVDD (3.3V)
3.135
1.71
3.135
3.30
1.80
3.30
3.465
1.89
3.465
V
V
V
1.71
1.80
1.89
20
433
640
mA
mA
mA
178
mA
AVDD (1.8V)
SUPPLY CURRENT
IDVDD_I/O
IDVDD
IAVDD(3.3V)
IAVDD(1.8V)
TOTAL POWER DISSIPATION
Base DDS Power, PLL Disabled
2392
3091
mW
2237
2627
mW
28
20
138
400
2.0
60
3
2.7
mW
mW
mW
mW
DVDD_I/O
0.8
200
V
V
A
pF
DVDD_I/O
0.4
V
V
IOH = 1 mA
IOL = 1 mA
REF CLK inputs should always be ac-coupled (both
single-ended and differential)
pF
k
V
1.5
1
1.4
2
0.8
Manual or automatic
616
1
1.4
2
0.8
V p-p
pF
k
V
1.5
V p-p
Rev. D | Page 4 of 48
Data Sheet
AD9914
AC SPECIFICATIONS
AVDD (1.8V) and DVDD (1.8V) = 1.8 V 5%, AVDD3 (3.3V) and DVDD_I/O (3.3V) = 3.3 V 5%, TA = 25C, RSET = 3.3 k, IOUT =
20 mA, external reference clock frequency = 3.5 GHz with reference clock (REF CLK) multiplier bypassed, unless otherwise noted.
Table 2.
Parameter
REF CLK INPUT
REF CLK Multiplier Bypassed
Input Frequency Range
Duty Cycle
Minimum Differential Input Level
System Clock (SYSCLK) PLL Enabled
VCO Frequency Range
VCO Gain (KV)
Maximum PFD Rate
CLOCK DRIVERS
SYNC_CLK Output Driver
Frequency Range
Duty Cycle
Rise Time/Fall Time (20% to 80%)
SYNC_OUT Output Driver
Frequency Range
Duty Cycle
Rise Time (20% to 80%)
Fall Time (20% to 80%)
DAC OUTPUT CHARACTERISTICS
Output Frequency Range (1st Nyquist
Zone)
Output Resistance
Output Capacitance
Full-Scale Output Current
Gain Error
Output Offset
Voltage Compliance Range
Min
Typ
500
45
632
2400
Max
Unit
Test Conditions/Comments
Input frequency range
3500
55
MHz
%
mV p-p
2500
60
125
45
50
650
MHz
MHz/V
MHz
146
55
MHz
%
ps
9.1
66
MHz
%
ps
ps
1750
MHz
10 pF load
33
1350
1670
0
50
1
20.48
+10
0.6
AVDD +
0.50
10
AVDD
0.50
pF
mA
% FS
A
V
Wideband SFDR
101.1 MHz Output
427.5 MHz Output
696.5 MHz Output
1396.5 MHz Output
Narrow-Band SFDR
100.5 MHz Output
427.5 MHz Output
696.5 MHz Output
1396.5 MHz Output
DIGITAL TIMING SPECIFICATIONS
Time Required to Enter Power-Down
Time Required to Leave Power-Down
Minimum Master Reset time
Maximum DAC Calibration Time (tCAL)
Maximum PLL Calibration Time (tREF_CLK)
Maximum Profile Toggle Rate
66
65
57
52
dBc
dBc
dBc
dBc
95
95
95
92
dBc
dBc
dBc
dBc
45
ns
250
135
ns
SYSCLK cycles
s
16
8
2
ms
ms
SYNC_CLK period
24
Rev. D | Page 5 of 48
AD9914
Parameter
PARALLEL PORT TIMING
Write Timing
Address Setup Time to WR Active
Data Sheet
Min
Max
Typ
Unit
ns
0
3.8
ns
ns
2.1
ns
3.8
ns
10.5
ns
92
0
ns
ns
Read Timing
Address to Data Valid
Address Hold to RD Inactive
Test Conditions/Comments
ns
69
ns
50
ns
69
ns
50
ns
80
MHz
ns
ns
ns
ns
ns
1.5
5.1
4.9
0
78
4
ns
0
ns
ns
2
0
2
0
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
2
Rev. D | Page 6 of 48
Data Sheet
Parameter
DATA LATENCY (PIPELINE DELAY)
Single Tone Mode or Profile Mode
(Matched Latency Disabled)
Frequency
Phase
Amplitude
Single Tone Mode or Profile Mode
(Matched Latency Enabled)
Frequency
Phase
Amplitude
Modulation Mode with 32-Bit Parallel
Port (Matched Latency Disabled)
Frequency
Phase
Amplitude
Modulation Mode with 32-Bit Parallel
Port (Matched Latency Enabled)
Frequency
Phase
Amplitude
Sweep Mode (Match Latency Disabled)
Frequency
Phase
Amplitude
Sweep Mode (Match Latency Enabled)
Frequency
Phase
Amplitude
AD9914
Min
Typ
Max
Unit
Test Conditions/Comments
SYSCLK cycles = fS = system clock frequency
in GHz
318
342
294
318
102
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
OSK disabled
OSK enabled
OSK disabled
OSK enabled
OSK enabled
318
342
318
342
342
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
OSK disabled
OSK enabled
OSK disabled
OSK enabled
OSK enabled
318
342
294
318
102
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
OSK disabled
OSK enabled
OSK disabled
OSK enabled
OSK enabled
318
342
318
342
342
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
OSK disabled
OSK enabled
OSK disabled
OSK enabled
OSK enabled
342
366
318
342
126
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
OSK disabled
OSK enabled
OSK disabled
OSK enabled
OSK enabled
342
366
342
366
366
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
OSK disabled
OSK enabled
OSK disabled
OSK enabled
OSK enabled
Rev. D | Page 7 of 48
AD9914
Data Sheet
Table 3.
Parameter
AVDD (1.8 V), DVDD (1.8 V) Supplies
AVDD (3.3 V), DVDD_I/O (3.3 V) Supplies
Digital Input Voltage
Digital Output Current
Storage Temperature Range
Operating Temperature Range
Maximum Junction Temperature
Lead Temperature (10 sec Soldering)
Rating
2V
4V
0.7 V to +4 V
5 mA
65C to +150C
40C to +85C
150C
300C
Table 4.
Symbol
JA
JMA
JMA
JB
JB
JC
JT
Description
Junction-to-ambient thermal
resistance (still air) per JEDEC
JESD51-2
Junction-to-ambient thermal
resistance (1.0 m/sec airflow)
per JEDEC JESD51-6
Junction-to-ambient thermal
resistance (2.0 m/sec air flow)
per JEDEC JESD51-6
Junction-to-board thermal
resistance (still air) per JEDEC
JESD51-8
Junction-to-board characterization
parameter (still air) per JEDEC
JESD51-6
Junction-to-case thermal resistance
Junction-to-top-of-package
characterization parameter (still air)
per JEDEC JESD51-2
Value1
24.1
Unit
C/W
21.3
C/W
20.0
C/W
13.3
C/W
12.8
C/W
2.21
0.23
C/W
C/W
ESD CAUTION
Rev. D | Page 8 of 48
Data Sheet
AD9914
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
D18
D19
I/O_UPDATE
MASTER_RESET
DGND
DVDD_I/O (3.3V)
SYNC_CLK
D20
D21
D22
D23
D24
D25
D26
DGND
DVDD (1.8V)
D27
D28
D29
D30
D31
EXT_PWR_DWN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
AD9914
TOP VIEW
(Not to Scale)
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
OSK
DROVER
DRHOLD
DRCTL
SYNC_IN
SYNC_OUT
AVDD (3.3V)
REF
LOOP_FILTER
AVDD (1.8V)
AVDD (1.8V)
REF CLK
REF CLK
AVDD (3.3V)
AVDD (3.3V)
AGND
AVDD (3.3V)
AGND
DAC_RSET
AVDD (3.3V)
AGND
DAC_BP
NOTES
1. THE EPAD MUST BE SOLDERED TO GROUND.
10836-003
DVDD (1.8V)
DGND
PS0
PS1
PS2
F0
F1
F2
F3
AVDD (1.8V)
AGND
AVDD (3.3V)
AGND
AVDD (3.3V)
AGND
AGND
AVDD (3.3V)
AVDD (3.3V)
AOUT
AOUT
AVDD (3.3V)
AGND
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
D17
D16
D15/A7
D14/A6
D13/A5
DVDD (1.8V)
DGND
D12/A4
D11/A3
D10/A2
D9/A1
D8/A0
D7
D6
D5
DVDD_I/O (3.3V)
DGND
D4/SYNCIO
D3/SDO
D2/SDIO/WR
D1/SCLK/RD
D0/CS/PWD
Mnemonic
D5 to D7, D16 to
D31, D27 to D31
I/O 1
I/O
D15/A7
I/O
D14/A6
I/O
D13/A5
I/O
D12/A4
I/O
D11/A3
I/O
10
D10/A2
I/O
11
D9/A1
I/O
Description
Parallel Port Pins. The 32-bit parallel port offers the option for serial or parallel programming
of the internal registers. In addition, the parallel port can be configured to provide direct FSK,
PSK, or ASK (or combinations thereof ) modulation data. The 32-bit parallel port configuration
is set by the state of the four function pins (F0 to F3).
Parallel Port Pin/Address Line. The state of the F0 to F3 function pins determines if this pin
acts as a line for direct FSK, PSK, or ASK data or as an address line for programming the
internal registers.
Parallel Port Pin/Address Line. The state of the F0 to F3 function pins determines if this pin
acts as a line for direct FSK, PSK, or ASK data or as an address line for programming the
internal registers.
Parallel Port Pin/Address Line. The state of the F0 to F3 function pins determines if this pin
acts as a line for direct FSK, PSK, or ASK data or as an address line for programming the
internal registers.
Parallel Port Pin/Address Line. The state of the F0 to F3 function pins determines if this pin
acts as a line for direct FSK, PSK, or ASK data or as an address line for programming the
internal registers.
Parallel Port Pin/Address Line. The state of the F0 to F3 function pins determines if this pin
acts as a line for direct FSK, PSK, or ASK data or as an address line for programming the
internal registers.
Parallel Port Pin/Address Line. Multipurpose pin depending on the state of the function pins
(F0 to F3). The state of the F0 to F3 function pins determines if this pin acts as a line for direct
FSK, PSK, or ASK data or as an address line for programming the internal registers.
Parallel Port Pin/Address Line. Multipurpose pin depending on the state of the function pins
(F0 to F3). The state of the F0 to F3 function pins determines if this pin acts as a line for direct
FSK, PSK, or ASK data or as an address line for programming the internal registers.
Rev. D | Page 9 of 48
AD9914
Data Sheet
Pin No.
12
Mnemonic
D8/A0
I/O 1
I/O
18
D4/SYNCIO
19
D3/SDO
I/O
20
D2/SDIO/WR
I/O
21
D1/SCLK/RD
22
D0/CS/PWD
6, 23, 73
7, 17, 24, 74, 84
16, 83
32, 56, 57
33, 35, 37, 38,
44, 46, 49, 51
34, 36, 39, 40,
43, 47, 50, 52,
53, 60
25, 26, 27
DVDD (1.8V)
DGND
DVDD_I/O (3.3V)
AVDD (1.8V)
AGND
I
I
I
I
I
Description
Parallel Port Pin/Address Line. The state of the F0 to F3 function pins determines if this pin
acts as a line for direct FSK, PSK, or ASK data or as an address line for programming the
internal registers.
Parallel Port Pin/Serial Port Synchronization Pin. This pin is D4 for direct FSK, PSK, or ASK data.
If serial mode is invoked via F0 to F3, this pin is used to reset the serial port.
Parallel Port Pin/Serial Data Output. This pin is D3 for direct FSK, PSK, or ASK data. If serial
mode is invoked via F0 to F3, this pin is used for readback mode for serial operation.
Parallel Port Pin/Serial Data Input and Output/Write Input. This pin is D2 for direct FSK, PSK,
or ASK data. If serial mode is invoked via F0 to F3, this pin is used for the SDIO for serial
operation. If parallel mode is enabled, this pin is used to write to change the values of the
internal registers.
Parallel Port Pin/Serial Clock/Read Input. This pin is D1 for direct FSK, PSK, or ASK data. If
serial mode is invoked via F0 to F3, this pin is used for SCLK for serial operation. If parallel
mode is enabled, this pin is used to read back the value of the internal registers.
Parallel Port Pin/Chip Select/Parallel Width. This pin is D0 for direct FSK, PSK, or ASK data. If
serial mode is invoked via F0 to F3, this pin is used for the chip select for serial operation. If
parallel mode is enabled, this pin is used to set either 8-bit data or16-bit data.
Digital Core Supplies (1.8 V).
Digital Ground.
Digital Input/Output Supplies (3.3 V).
Analog Core Supplies (1.8 V).
Analog Ground.
AVDD (3.3V)
PS0 to PS2
F0 to F3
41
AOUT
42
AOUT
45
DAC_BP
48
DAC_RSET
54
55
58
59
61
62
63
64
65
REF_CLK
REF_CLK
LOOP_FILTER
REF
SYNC_OUT
SYNC_IN
DRCTL
DRHOLD
DROVER
I
I
O
O
O
I
I
I
O
66
OSK
Profile Select Pins. Digital inputs (active high). Use these pins to select one of eight
phase/frequency profiles for the DDS. Changing the state of one of these pins transfers the
current contents of all I/O buffers to the corresponding registers. State changes should be set
up on the SYNC_CLK pin (Pin 82).
Function Pins. Digital inputs. The state of these pins determines if a serial or parallel interface
is used. In addition, the function pins determine how the 32-bit parallel data-word is
partitioned for FSK, PSK, or ASK modulation mode.
DAC Complementary Output Source. Analog output (voltage mode). Internally connected
through a 50 resistor to AVDD (3.3V).
DAC Output Source. Analog output (voltage mode). Internally connected through a 50
resistor to AVDD (3.3V).
DAC Bypass Pin. Provides access to the common control node of the DAC current sources.
Connecting a capacitor between this pin and ground can improve noise performance at the
DAC output.
Analog Reference. This pin programs the DAC output full-scale reference current. Connect a
3.3 k resistor to AGND.
Complementary Reference Clock Input. Analog input.
Reference Clock Input. Analog input.
External PLL Loop Filter Node.
Local PLL Reference Supply. Typically at 2.05 V.
Digital Synchronization Output. Used to synchronize multiple chips.
Digital Synchronization Input. Used to synchronize multiple chips.
Ramp Control. Digital input (active high). This pin controls the sweep direction (up/down).
Ramp Hold. Digital input (active high). Pauses the sweep when active.
Ramp Over. Digital output (active high). This pin switches to Logic 1 when the digital ramp
generator reaches its programmed upper or lower limit.
Output Shift Keying. Digital input (active high). When the OSK features are placed in either
manual or automatic mode, this pin controls the OSK function. In manual mode, it toggles
the multiplier between 0 (low) and the programmed amplitude scale factor (high). In
automatic mode, a low sweeps the amplitude down to zero and a high sweeps the
amplitude up to the amplitude scale factor.
Rev. D | Page 10 of 48
Data Sheet
AD9914
Pin No.
67
Mnemonic
EXT_PWR_DWN
I/O 1
I
82
SYNC_CLK
85
MASTER_RESET
86
I/O_UPDATE
EPAD
1
Description
External Power-Down. Digital input (active high). A high level on this pin initiates the
currently programmed power-down mode.
Clock Output. Digital output. Many of the digital inputs on the chip, such as I/O_UPDATE,
PS[2:0], and the parallel data port (D0 to D31), must be set up on the rising edge of
this signal.
Master Reset. Digital input (active high). Clears all memory elements and sets registers to
default values.
Input/Output Update. Digital input (active high). A high on this pin transfers the contents of
the I/O buffers to the corresponding internal registers.
Exposed Pad. The EPAD must be soldered to ground.
I = input, O = output.
Rev. D | Page 11 of 48
AD9914
Data Sheet
10
10
20
20
30
30
40
40
SFDR (dBc)
50
60
50
60
70
70
80
80
90
175MHz/DIV
STOP 1.75GHz
10
10
20
20
30
30
40
40
SFDR (dBc)
50
60
60
70
80
80
90
90
START 0Hz
175MHz/DIV
STOP 1.75GHz
100
10
20
20
30
30
40
40
SFDR (dBc)
0
10
50
60
80
80
90
90
STOP 1.75GHz
SPAN 500kHz
60
70
175MHz/DIV
50kHz/DIV
50
70
10836-006
SFDR (dBc)
START 0Hz
CENTER 427.5MHz
100
SPAN 500kHz
50
70
100
50kHz/DIV
10836-005
SFDR (dBc)
CENTER 171.5MHz
10836-008
START 0Hz
100
10836-007
90
10836-004
100
100
CENTER 696.5MHz
50kHz/DIV
SPAN 500kHz
Rev. D | Page 12 of 48
10836-009
SFDR (dBc)
Nominal supply voltage; DAC RSET = 3.3 k, TA = 25C, unless otherwise noted.
AD9914
10
10
20
20
30
30
40
40
SFDR (dBc)
50
60
50
60
70
70
80
80
90
100
START 0Hz
175MHz/DIV
STOP 1.75GHz
10836-010
90
100
50kHz/DIV
CENTER 1396.5MHz
SPAN 500kHz
10836-013
SFDR (dBc)
Data Sheet
80
10
90
PHASE NOISE (dBc/Hz)
30
40
50
60
110
120
130
SMA AND
ADCLK925
140
150
SMA
160
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
fC/fS
10
20
30
40
50
1k
10k
100k
1M
FREQUENCY OFFSET (Hz)
10M
100M
70
SYSCLK = 2.7GHz
SYSCLK = 2.8GHz
SYSCLK = 2.9GHz
SYSCLK = 3.0GHz
SYSCLK = 3.1GHz
SYSCLK = 3.2GHz
SYSCLK = 3.3GHz
SYSCLK = 3.4GHz
SYSCLK = 3.5GHz
80
90
PHASE NOISE (dBc/Hz)
SYSCLK = 1.5GHz
SYSCLK = 1.6GHz
SYSCLK = 1.7GHz
SYSCLK = 1.8GHz
SYSCLK = 1.9GHz
SYSCLK = 2.0GHz
SYSCLK = 2.1GHz
SYSCLK = 2.2GHz
SYSCLK = 2.3GHz
SYSCLK = 2.4GHz
SYSCLK = 2.5GHz
SYSCLK = 2.6GHz
100
Figure 14. Absolute Phase Noise of REF CLK Source Driving AD9914
Rohde & Schwarz SMA100 Signal Generator at 3.5 GHz Buffered by Series
ADCLK925
170
10
10836-011
80
10836-014
70
100
110
1396MHz
120
696MHz
130
140
60
150
427MHz
70
160
80
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
fC/fS
0.40
170
10
10836-012
SFDR (dBc)
100
171MHz
100
1k
10k
100k
1M
FREQUENCY OFFSET (Hz)
10M
100M
10836-015
SFDR (dBc)
20
Figure 15. Absolute Phase Noise Curves of DDS Output at 3.5 GHz Operation
Rev. D | Page 13 of 48
Data Sheet
70
70
80
80
90
90
PHASE NOISE (dBc/Hz)
100
110
1396MHz
130
140
NORMALIZED
REF CLK SOURCE
150
1k
10k
100k
1M
FREQUENCY OFFSET (Hz)
10M
100M
305MHz
140
170
10
10836-016
100
123MHz
100
1k
10k
100k
1M
FREQUENCY OFFSET (Hz)
10M
100M
Figure 19. Absolute Phase Noise Curves of DDS Output Using Internal PLL at
2.5 GHz Operation
60
60
70
70
80
80
PHASE NOISE (dBc/Hz)
90
100
110
120
1396MHz
130
696MHz
140
150
160
100
110
1396MHz ABSOLUTE
120
130
1396MHz RESIDUAL
150
170
171MHz
100
1k
10k
100k
1M
FREQUENCY OFFSET (Hz)
10M
100M
160
10
100
1k
10k
100k
1M
FREQUENCY OFFSET (Hz)
10M
100M
10836-020
180
10
90
140
427MHz
10836-017
497MHz
130
160
Figure 16. Absolute Phase Noise Curves of Normalized REF CLK Source to
DDS Output at 1396 MHz (SYSCLK = 3.5 GHz)
0.5
60
3.3V ANALOG
70
80
PHASE NOISE (dBc/Hz)
0.4
0.3
1.8V DIGITAL
0.2
1.8V ANALOG
0.1
90
100
110
1396MHz ABSOLUTE
120
130
140
150
1396MHz RESIDUAL
160
170
3.3V DIGITAL
0
500
1000
1500
2000
2500
3000
3500
4000
180
10
10836-018
120
150
160
170
10
978MHz
110
10836-019
120
100
100
1k
10k
100k
1M
FREQUENCY OFFSET (Hz)
10M
100M
10836-021
AD9914
Figure 21. Residual Phase Noise vs. Normalized Absolute REF CLK Source
Phase Noise at 1396 MHz
Rev. D | Page 14 of 48
Data Sheet
AD9914
930
FREQUENCY (MHz)
920
910
900
890
M20.00ms
A CH2
1.64V
IT 40.0ps/pt
870
6
TIME (ms)
10836-024
CH2 1.0V
10836-022
880
930
1.0
0.9
920
0.8
FREQUENCY (MHz)
TIME (ms)
0.7
0.6
0.5
0.4
0.3
0.2
910
900
890
880
1000
1500
2000
2500
3000
3500
Figure 23. DAC Calibration Time vs. SYSCLK Rate. See the DAC Calibration
Output Section for Formula.
Rev. D | Page 15 of 48
870
6
TIME (ms)
10836-025
0
500
10836-023
0.1
AD9914
Data Sheet
EQUIVALENT CIRCUITS
AGND
IFS
CURRENT
SWITCH
ARRAY
SWITCH
CONTROL
CURRENT
SWITCH
ARRAY
IFS/2 + ICODE
DVDD (3.3V)
IFS/2 ICODE
CODE
41
INTERNAL
50
10836-044
INTERNAL
50
AOUT
AVDD (3.3V)
10836-045
AOUT 42
AVDD (3.3V)
DVDD (3.3V)
REF_CLK
10836-043
10836-048
REF_CLK
Rev. D | Page 16 of 48
Data Sheet
AD9914
THEORY OF OPERATION
DIGITAL RAMP MODULATION MODE
The modes define the data source used to supply the DDS with
its signal control parameters: frequency, phase, or amplitude.
The partitioning of the data into different combinations of
frequency, phase, and amplitude is established based on the
mode and/or specific control bits and function pins.
Although the various modes are described independently, they can
be enabled simultaneously. This provides an unprecedented level
of flexibility for generating complex modulation schemes. However,
to avoid multiple data sources from driving the same DDS signal
control parameter, the device has a built-in priority protocol.
In single tone mode, the DDS signal control parameters come
directly from the profile programming registers. In digital ramp
modulation mode, the DDS signal control parameters are delivered
by a digital ramp generator. In parallel data port modulation mode,
the DDS signal control parameters are driven directly into the
parallel port.
The various modulation modes generally operate on only one of
the DDS signal control parameters (two in the case of the polar
modulation format via the parallel data port). The unmodulated
DDS signal control parameters are stored in programming registers
and automatically routed to the DDS based on the selected mode.
A separate output shift keying (OSK) function is also available.
This function employs a separate digital linear ramp generator
that affects only the amplitude parameter of the DDS. The OSK
function has priority over the other data sources that can drive
the DDS amplitude parameter. As such, no other data source
can drive the DDS amplitude when the OSK function is enabled.
Rev. D | Page 17 of 48
AD9914
Data Sheet
MODE PRIORITY
The ability to activate each mode independently makes it
possible to have multiple data sources attempting to drive the
same DDS signal control parameter (frequency, phase, and
amplitude). To avoid contention, the AD9914 has a built-in
priority system. Table 6 summarizes the priority for each of the
DDS modes. The data source column in Table 6 lists data sources
for a particular DDS signal control parameter in descending
order of precedence. For example, if the profile mode enable bit
and the parallel data port enable bit (0x01[23:22]) are set to
Logic 1 and both are programmed to source the frequency
tuning word to DDS output, the profile modulation mode has
priority over the parallel data port modulation mode.
Data Source
Programmable
modulus
DRG
Profiles
Lowest
Priority
Parallel port
Rev. D | Page 18 of 48
Data Sheet
AD9914
POW
2 14
2
=
POW
360 14
2
FTW
f OUT = 32 f SYSCLK
2
(1)
Amplitude Scale =
(2)
To find the ASF value necessary for a particular scale factor, solve
Equation 3 for ASF and round the result (in a manner similar
to that described previously for finding an arbitrary FTW).
12
PHASE
OFFSET
CONTROL
16
MSB ALIGNED
32-BIT
ACCUMULATOR
32
FREQUENCY 32
CONTROL
32
DQ
R
DDS_CLK
(3)
FTW
f OUT = 1 32 f SYSCLK
2
ASF
20 log 12
2
12
14
17
32 17
(MSBs)
ANGLE-TOAMPLITUDE 12
12
CONVERSION
(SINE OR
COSINE)
TO DAC
ACCUMULATOR
RESET
Rev. D | Page 19 of 48
10836-026
f
FTW = round 2 32 OUT
f SYSCLK
ASF
212
AD9914
Data Sheet
469,632
fS
RECONSTRUCTION FILTER
The DAC output signal appears as a sinusoid sampled at fS. The
frequency of the sinusoid is determined by the frequency tuning
word (FTW) that appears at the input to the DDS. The DAC
MAGNITUDE
(dB)
IMAGE 0
IMAGE 1
IMAGE 2
IMAGE 3
IMAGE 4
0
20
40
PRIMARY
SIGNAL
FILTER
RESPONSE
SIN(x)/x
ENVELOPE
60
80
SPURS
100
fs/2
fs
3fs/2
2fs
BASE BAND
Rev. D | Page 20 of 48
5fs/2
10836-027
t CAL =
Data Sheet
AD9914
55 REF_CLK
PECL,
LVPECL,
OR
LVDS
DRIVER
TERMINATION
54 REF_CLK
0.1F
BALUN
(1:1)
SINGLE-ENDED SOURCE,
DIFFERENTIAL INPUT
54 REF_CLK
0.1F
58
PLL ENABLE
CFR3[18]
0.1F
55 REF_CLK
ENABLE
1, 2, 4, 8
54 REF_CLK
LOOP
FILTER
0.1F
1
0
IN
PLL
OUT
CHARGE
PUMP DIVIDE
SYSCLK
55
54
INPUT DIVIDER
2
7
RESET CFR3[22]
N
ICP CFR3[15:8]
INPUT DIVIDER RATIO
CFR3[21:20]
CFR3[5:3]
10836-028
REF_CLK
50
10836-029
SINGLE-ENDED SOURCE,
SINGLE-ENDED INPUT
DOUBLER
CLOCK EDGE
CFR3[16]
55 REF_CLK
50
LOOP_FILTER
DOUBLER ENABLE
CFR3[19]
0.1F
REF_CLK
The PLL enable bit is used to choose between the PLL path or
the direct input path. When the direct input path is selected,
the REF_CLK/REF_CLK pins must be driven by an external
signal source (single-ended or differential). Input frequencies
up to 3.5 GHz are supported.
VCO Calibration
When using the PLL to generate the system clock, VCO calibration
is required to tune the VCO appropriately and achieve good
performance. When the reference input signal is stable, the
VCO cal enable bit in the CFR1 register, 0x00[24], must be
asserted. Subsequent VCO calibrations require that the VCO
calibration bit be cleared prior to initiating another VCO
calibration. VCO calibration must occur before DAC calibration
to ensure optimal performance and functionality.
Rev. D | Page 21 of 48
AD9914
Data Sheet
CZ = 560pF (RECOMMENDED)
0.47F
REF
CP
50pF
Note that the total PLL multiplication value for the PLL is always
2N due to the fixed divide by 2 element in the feedback path.
This is shown in Figure 34. This fixed divide by 2 element forces
only even PLL multiplication.
VCO
CP
PFD
PLL OUT
REFCLK PLL
PLL IN
The primary control for the OSK block is the OSK enable bit
(0x00[8]). When the OSK function is disabled, the OSK input
controls and OSK pin are ignored.
26
OSK
27
66
OSK ENABLE
EXTERNAL
OSK ENABLE
AMPLITUDE SCALE 12
FACTOR (1 OF 8
SELECTED PROFILE
REGISTERS [27:16])
OSK
12
CONTROLLER
DDS CLOCK
Rev. D | Page 22 of 48
TO DDS
AMPLITUDE
CONTROL
PARAMETER
10836-031
RPZ (3.5k)
10836-030
LOOP_FILTER
58
59
Data Sheet
AD9914
The output of the DRG is a 32-bit unsigned data bus that can be
routed to any one of the three DDS signal control parameters, as
controlled by the two digital ramp destination bits in Control
Function Register 2 according to Table 9. The 32-bit output bus
is MSB-aligned with the 32-bit frequency parameter, the 16-bit
phase parameter, or the 12-bit amplitude parameter, as defined
by the destination bits. When the destination is phase or amplitude,
the unused LSBs are ignored.
DRG Overview
DRCTL
DRHOLD
DROVER
63
64
65
Digital Ramp
Destination Bits
(CFR2[21:20])
00
01
1x1
CLEAR DIGITAL
RAMP ACCUMULATOR
AUTOCLEAR DIGITAL
RAMP ACCUMULATOR
32
32
TO DDS
SIGNAL
CONTROL
PARAMETER
32
32
x = dont care.
32
DIGITAL RAMP RATE REGISTER
10836-032
The DRG also supports a hold feature controlled via the DRHOLD
pin. When this pin is set to Logic 1, the DRG is stalled at its last
state; otherwise, the DRG operates normally. The DDS signal
control parameters that are not the destination of the DRG are
taken from the active profile.
DDS CLOCK
The primary control for the DRG is the digital ramp enable bit
(0x01[19]). When disabled, the other DRG input controls are
ignored and the internal clocks are shut down to conserve power.
32
DECREMENT STEP SIZE
32
INCREMENT STEP SIZE
32
32
1
32
32
D
DRCTL 63
R
16
NEGATIVE SLOPE RATE
16
POSITIVE SLOPE RATE
32
32
UPPER
LIMIT
LOWER
LIMIT
TO DDS
SIGNAL
CONTROL
PARAMETER
16
LOAD
CONTROL
LOGIC
DRHOLD 64
DDS CLOCK
LIMIT CONTROL
PRESET
LOAD
ACCUMULATOR
RESET
CONTROL
LOGIC
Q
DIGITAL
RAMP
TIMER
Rev. D | Page 23 of 48
NO-DWELL
CONTROL
2
NO DWELL
. ACC
AUTOCLEAR DIGITAL RAMP
10836-033
DIGITAL
RAMP
GENERATOR
Bits Assigned to
DDS Parameter
31:0
31:18
31:20
32
DIGITAL RAMP LOWER LIMIT REGISTER
DDS Signal
Control
Parameter
Frequency
Phase
Amplitude
AD9914
Data Sheet
24 P
f SYSCLK
24 N
f SYSCLK
where P and N are the two 16-bit values stored in the 32-bit digital
ramp rate register and control the step interval. N defines the step
interval of the negative slope portion of the ramp. P defines the step
interval of the positive slope portion of the ramp.
The step size of the positive (STEPP) and negative (STEPN) slope
portions of the ramp are 32-bit values programmed into the 32-bit
rising and falling digital ramp step size registers (0x06 and 0x07).
Program each of the step sizes as an unsigned integer (the hardware
automatically interprets STEP N as a negative value). The
relationship between the 32-bit step size values and actual units
of frequency, phase, or amplitude depend on the digital ramp
destination bits. Calculate the actual frequency, phase, or amplitude
step size by substituting STEPN or STEPP for M in the following
equations as required:
M
Frequency Step = 32 f SYSCLK
2
Phase Step =
Phase Step =
45M
229
The phase and amplitude step size equations yield the average
step size. Although the step size accumulates with 32-bit precision,
the phase or amplitude destination exhibits only 16 bits or 12 bits,
respectively. Therefore, at the destination, the actual phase or
amplitude step is the accumulated 32-bit value truncated to
16 bits or 12 bits, respectively.
As described previously, the step interval is controlled by a
16-bit programmable timer. There are three events that can
cause this timer to be reloaded prior to its expiration. One event
occurs when the digital ramp enable bit transitions from cleared
to set, followed by an I/O update. A second event is a change of
state in the DRCTL pin. The third event is enabled using the load
LRR at I/O update bit (0x00[15]).
(radians)
(degrees)
With the limit control block embedded in the feedback path of the
accumulator, resetting the accumulator is equivalent to presetting
it to the lower limit value.
M
231
Note that the frequency units are the same as those used to
represent fSYSCLK (MHz, for example). The amplitude units are
the same as those used to represent IFS, the full-scale output
current of the DAC (mA, for example).
M
Amplitude Step = 32 I FS
2
Rev. D | Page 24 of 48
Data Sheet
AD9914
P DDS CLOCK CYCLES
NEGATIVE
STEP SIZE
+t
POSITIVE
STEP SIZE
UPPER LIMIT
DRG OUTPUT
LOWER LIMIT
DROVER
DRHOLD
AUTO
CLEAR
CLEAR
DRCTL
RELEASE
CLEAR DIGITAL
RAMP ACCUMULATOR
AUTOCLEAR DIGITAL
RAMP ACCUMULATOR
13
11
10
12
10836-034
I/O_UPDATE
Rev. D | Page 25 of 48
AD9914
Data Sheet
tion between the limits. Likewise, if the DRG output is in the
midst of a negative slope and the DRCTL pin transitions from
Logic 0 to Logic 1, the DRG immediately switches to the positive
slope parameters and resumes oscillation between the limits.
When both no-dwell bits are set, the DROVER signal produces
a positive pulse (two cycles of the DDS clock) each time the DRG
output reaches either of the programmed limits (assuming that
the DRG over output enable bit (0x01[13]) is set).
Event 4Because the digital ramp no-dwell high bit is set, the
moment that the DRG output reaches the upper limit, it immediately switches to the lower limit, where it remains until the
next Logic 0 to Logic 1 transition of DRCTL.
Operation with the digital ramp no-dwell low bit set (instead of
the digital ramp no-dwell high bit) is similar, except that the DRG
output ramps in the negative direction on a Logic 1 to Logic 0
transition of DRCTL and jumps to the upper limit upon
reaching the lower limit.
POSITIVE
STEP SIZE
+t
UPPER LIMIT
DRG OUTPUT
LOWER LIMIT
DROVER
10836-035
DRCTL
Data Sheet
AD9914
DROVER Pin
POWER-DOWN CONTROL
10836-036
0x0A
Digital core
DAC
Input REF CLK clock circuitry
FREQUENCY
LOWER LIMIT
Rev. D | Page 27 of 48
AD9914
Data Sheet
Mode Description
Parallel programming mode
Bits[31:24] 2
Data[15:8]
(optional)
0001
Not used
0010
FTW[31:24]
FTW[15:8]
FTW[7:0]
FTW[31:24]
FTW[23:16]
POW[15:8]
POW[7:0]
AMP[11:8]
AMP[7:0]
AMP[11:8]
AMP[7:0]
POW[15:8]
POW[7:0]
FTW[31:24]
FTW[23:16]
FTW[15:8]
AMP[15:8]
FTW[31:24]
FTW[23:16]
FTW[15:8]
POW[15:8]
FTW[31:24]
FTW[23:16]
FTW[15:8]
AMP[7:0]
FTW[31:24]
FTW[23:16]
FTW[15:8]
POW[7:0]
FTW[23:16]
FTW[15:8]
FTW[7:0]
AMP[15:8]
FTW[23:16]
FTW[15:8]
FTW[7:0]
POW[15:8]
FTW[23:16]
FTW[15:8]
FTW[7:0]
AMP[7:0]
FTW[23:16]
FTW[15:8]
FTW[7:0]
POW[7:0]
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Rev. D | Page 28 of 48
Data Sheet
FUNCTION
PINS
AD9914
F[3:0]
DECODE
DDS
DIRECT MODES
PARALLEL
PORT PINS
32
32
BITS[31:0]
32
32
ROUTING
LOGIC
DQ
CK
SYNC_CLK
FTW
FREQUENCY
POW
PHASE
AMP
AMPLITUDE
16
12
32
FUNCTION PINS AND DIRECT MODE
BITS[31:0] VS. FTW, POW, AMP
F[3:0] BITS[31:24] BITS[23:16] BITS[15:8]
0000
0001
PARALLEL
CONTROL
27
PARALLEL MODE
SERIAL MODE
BITS[15:8]
FTW[7:0]
0011
FTW[15:8]
FTW[7:0]
FTW[31:24] FTW[23:16]
0100
POW[15:8]
POW[7:0]
AMP[11:8]
AMP[7:0]
8 BITS[31:24]
8 BITS[23:16]
DIRECT MODE
0010
OSK ENABLE
PARALLEL MODE
BITS[7:0]
BIT 2
BIT 1
AMP[7:0]
BIT 0
0101
AMP[11:8]
POW[15:8]
POW[7:0]
0110
AMP[15:8]
0111
POW[15:8]
1000
AMP[7:0]
1001
POW[7:0]
1010
FTW[23:16] FTW[15:8]
FTW[7:0]
AMP[15:8]
BIT 3
1011
FTW[23:16] FTW[15:8]
FTW[7:0]
POW[15:8]
BIT 2
1100
FTW[23:16] FTW[15:8]
FTW[7:0]
AMP[7:0]
BIT 1
1101
FTW[23:16] FTW[15:8]
FTW[7:0]
POW[7:0]
BIT 0
D[15:8]
SYSTEM
CLOCK
PROGRAMMING
REGISTERS
D[7:0]
A[7:0]
WR
IO_UPDATE
RD
16 BITS/8 BITS
SERIAL MODE
SERIAL
CONTROL
5
SYNCIO
SDO
SDIO
SCLK
CS
10836-046
BIT 4
NOTES
1. AMP[11:0] CONTROLS AMPLITUDE. AMP[15:12] UNUSED.
Rev. D | Page 29 of 48
AD9914
Data Sheet
Rev. D | Page 30 of 48
Data Sheet
AD9914
SERIAL PROGRAMMING
To enable SPI operations, set Pin 28 (F0) to logic high and Pin 29
to Pin 31 (F1 to F3) to logic low. To program the AD9914 with a
parallel interface, see the Parallel Programming section.
Mnemonic
D4/SYNCIO
D3/SDO
D2/SDIO/WR
D1/SCLK/RD
D0/CS/PWD
INSTRUCTION BYTE
The instruction byte contains the following information as
shown in the instruction byte information bit map.
MSB
LSB
I7
I6
I5
I4
I3
I2
I1
I0
R/W
A5
A4
A3
A2
A1
A0
Rev. D | Page 31 of 48
AD9914
Data Sheet
Data is read from this pin for protocols that use separate lines
for transmitting and receiving data. When the AD9914 operates
in single bidirectional I/O mode, this pin does not output data
and is set to a high impedance state.
SYNCIOInput/Output Reset
Note that the SCLK stall condition between the instruction byte
cycle and data transfer cycle in Figure 42 to Figure 45 is not
required.
MSB/LSB TRANSFERS
The AD9914 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. This
functionality is controlled by Bit 0 in CFR1 (0x00). The default
format is MSB first. If LSB first is active, all data, including the
instruction byte, must follow LSB-first convention. Note that the
highest number found in the bit range column for each register is
the MSB, and the lowest number is the LSB for that register.
I/O_UPDATEInput/Output Update
The I/O update initiates the transfer of written data from the
serial or parallel I/O port buffer to active registers. I/O_UPDATE
is active on the rising edge, and its pulse width must be greater
than one SYNC_CLK period.
INSTRUCTION CYCLE
CS
SDIO
I7
I6
I5
I4
I3
I2
I1
I0
D7
D6
D5
D4
D3
D2
D1
10836-037
SCLK
D0
CS
SCLK
I6
I7
I5
I4
I3
I2
I1
I0
DON'T CARE
DO7
SDO
DO5
DO6
DO4
DO3
DO2
DO1
DO0
10836-038
SDIO
Figure 43. 3-Wire Serial Port Read Timing, Clock Stall Low
INSTRUCTION CYCLE
CS
I7
I6
I5
I4
I3
I2
I1
I0
D7
D6
D5
D4
D3
D2
D1
D0
10836-039
SDIO
DO0
10836-040
SCLK
CS
SCLK
SDIO
I7
I6
I5
I4
I3
I2
I1
I0
DO7
DO6
DO5
DO4
Figure 45. 2-Wire Serial Port Read Timing, Clock Stall High
Rev. D | Page 32 of 48
DO3
DO2
DO1
Data Sheet
AD9914
A[7:0]
D[7:0] OR
D[15:0]
A1
D1
tRDHIGH
Value
92
0
Unit
ns max
ns min
tRDLOV
tRDHOZ
tRDLOW
tRDHIGH
69
50
69
50
ns max
ns max
ns max
ns max
Test Conditions/Comments
Address to data valid time
Address hold time to RD signal
inactive
RD low to output valid
RD high to data three-state
RD signal minimum low time
RD signal minimum high time
Value
1
Unit
ns
tDSU
3.8
ns
tAHD
ns
tDHD
ns
tWRLOW
tWRHIGH
tWR
2.1
3.8
10.5
ns
ns
ns
A2
A3
D2
D3
tRDLOW
RD
tRDHOZ
10836-041
tRDLOV
tADV
tAHD
tWR
D[7:0] OR
D[15:0]
A1
A2
D1
A3
D2
WR
tASU
tWRHIGH
tDSU
tWRLOW
D3
tAHD
tDHD
Rev. D | Page 33 of 48
10836-042
A[7:0]
AD9914
Data Sheet
Bit Range
(Parallel
Address)
[7:0]
(0x00)
[15:8]
(0x01)
Bit 7
(MSB)
Digital
powerdown
Load LRR
at I/O
update
Bit 6
DAC
powerdown
Autoclear
digital
ramp
accumulator
Bit 5
REF CLK
input
powerdown
Autoclear
phase
accumulator
[23:16]
(0x02)
CFR2
Control
Function
Register 2
(0x01)
[31:24]
(0x03)
[7:0]
(0x04)
[15:8]
(0x05)
[23:16]
(0x06)
CFR3
Control
Function
Register 3
(0x02)
CFR4
Control
Function
Register 4
(0x03)
Digital Ramp
Lower Limit
Register
(0x04)
[31:24]
(0x07)
[7:0]
(0x08)
[15:8]
(0x09)
[23:16]
(0x0A)
[31:24]
(0x0B)
[7:0]
(0x0C)
[15:8]
(0x0D)
[23:16]
(0x0E)
[31:24]
(0x0F)
[7:0]
(0x10)
[15:8]
(0x11)
[23:16]
(0x12)
[31:24]
(0x13)
Bit 4
Open
Bit 3
External
power-down
control
Bit 2
Open
Bit 1
SDIO input
only
Clear digital
ramp
accumulator
Clear phase
accumulator
Open
External
OSK enable
OSK
enable
0x00
Parallel port
streaming
enable
Enable
sine
output
VCO cal
enable
0x01
Open
Open
Open
Matched
latency
enable
Profile
mode
enable
Frequency
jump
enable
Parallel
data port
enable
Manual ICP
selection
SYNC_CLK
enable
SYNC_CLK
invert
Reserved
Open
0x09
Digital ramp
enable
Digital
ramp nodwell high
Digital
ramp nodwell low
Program
modulus
enable
0x00
ICP[2:0]
0x00
Lock
detect
enable
Minimum LDW[1:0]
Input
divider
reset
Input divider[1:0]
0x00
0x00
Open
Open
Default
Value
(Hex) 1
0x08
Bit 0
(LSB)
LSB first
mode
Doubler
enable
0x1C
0x19
PLL enable
PLL input
divider
enable
Doubler
clock edge
0x00
Open
0x00
0x20
0x21
0x05
Open
Auxiliary
divider
powerdown
DAC CAL
clock
powerdown
DAC CAL
enable 2
0x00
0x00
0x00
0x00
0x00
Rev. D | Page 34 of 48
Data Sheet
Register
Name (Serial
Address)
Digital Ramp
Upper
Limit
Register
(0x05)
Rising Digital
Ramp Step
Size
Register
(0x06)
Falling Digital
Ramp Step
Size
Register
(0x07)
Digital Ramp
Rate
Register
(0x08)
Lower
Frequency
Jump
Register
(0x09)
Upper
Frequency
Jump
Register
(0x0A)
Profile 0 (P0)
Frequency
Tuning
Word 0
Register
(0x0B)
Bit Range
(Parallel
Address)
[7:0]
(0x14)
[15:8]
(0x15)
[23:16]
(0x16)
[31:24]
(0x17)
[7:0]
(0x18)
[15:8]
(0x19)
[23:16]
(0x1A)
[31:24]
(0x1B)
[7:0]
(0x1C)
[15:8]
(0x1D)
[23:16]
(0x1E)
[31:24]
(0x1F)
[7:0]
(0x20)
[15:8]
(0x21)
[23:16]
(0x22)
[31:24]
(0x23)
[7:0]
(0x24)
[15:8]
(0x25)
[23:16]
(0x26)
[31:24]
(0x27)
[7:0]
(0x28)
[15:8]
(0x29)
[23:16]
(0x2A)
[31:24]
(0x2B)
[7:0]
(0x2C)
[15:8]
(0x2D)
[23:16]
(0x2E)
[31:24]
(0x2F)
AD9914
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Digital ramp upper limit[7:0]
Bit 1
Bit 0
(LSB)
Default
Value
(Hex) 1
0x00
0x00
0x00
0x00
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Rev. D | Page 35 of 48
AD9914
Register
Name (Serial
Address)
Profile 0 (P0)
Phase/
Amplitude
Register
(0x0C)
Profile 1 (P1)
Frequency
Tuning
Word 1
Register
(0x0D)
Profile 1 (P1)
Phase/
Amplitude
Register
(0x0E)
Profile 2 (P2)
Frequency
Tuning
Word 2
Register
(0x0F)
Profile 2 (P2)
Phase/
Amplitude
Register
(0x10)
Profile 3 (P3)
Frequency
Tuning
Word 3
Register
(0x11)
Profile 3 (P3)
Phase/
Amplitude
Register
(0x12)
Data Sheet
Bit Range
(Parallel
Address)
[7:0]
(0x30)
[15:8]
(0x31)
[23:16]
(0x32)
[31:24]
(0x33)
[7:0]
(0x34)
[15:8]
(0x35)
[23:16]
(0x36)
[31:24]
(0x37)
[7:0]
(0x38)
[15:8]
(0x39)
[23:16]
(0x3A)
[31:24]
(0x3B)
[7:0]
(0x3C)
[15:8]
(0x3D)
[23:16]
(0x3E)
[31:24]
(0x3F)
[7:0]
(0x40)
[15:8]
(0x41)
[23:16]
(0x42)
[31:24]
(0x43)
[7:0]
(0x44)
[15:8]
(0x45)
[23:16]
(0x46)
[31:24]
(0x47)
[7:0]
(0x48)
[15:8]
(0x49)
[23:16]
(0x4A)
[31:24]
(0x4B)
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Phase Offset Word 0[7:0]
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex) 1
0x00
0x00
0x00
Open
0x00
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Open
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Open
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Open
Rev. D | Page 36 of 48
N/A
Data Sheet
Register
Name (Serial
Address)
Profile 4 (P4)
Frequency
Tuning
Word 4
Register
(0x13)
Profile 4 (P4)
Phase/
Amplitude
Register
(0x14)
Profile 5 (P5)
Frequency
Tuning
Word 5
Register
(0x15)
Profile 5 (P5)
Phase/
Amplitude
Register
(0x16)
Profile 6 (P6)
Frequency
Tuning
Word 6
Register
(0x17)
Profile 6 (P6)
Phase/
Amplitude
Register
(0x18)
Profile 7 (P7)
Frequency
Tuning
Word 7
Register
(0x19)
Bit Range
(Parallel
Address)
[7:0]
(0x4C)
[15:8]
(0x4D)
[23:16]
(0x4E)
[31:24]
(0x4F)
[7:0]
(0x50)
[15:8]
(0x51)
[23:16]
(0x52)
[31:24]
(0x53)
[7:0]
(0x54)
[15:8]
(0x55)
[23:16]
(0x56)
[31:24]
(0x57)
[7:0]
(0x58)
[15:8]
(0x59)
[23:16]
(0x5A)
[31:24]
(0x5B)
[7:0]
(0x5C)
[15:8]
(0x5D)
[23:16]
(0x5E)
[31:24]
(0x5F)
[7:0]
(0x60)
[15:8]
(0x61)
[23:16]
(0x62)
[31:24]
(0x63)
[7:0]
(0x64)
[15:8]
(0x65)
[23:16]
(0x66)
[31:24]
(0x67)
AD9914
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Frequency Tuning Word 4[7:0]
Bit 1
Bit 0
(LSB)
Default
Value
(Hex) 1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Open
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Open
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Open
n/a
N/A
N/A
N/A
N/A
Rev. D | Page 37 of 48
AD9914
Register
Name (Serial
Address)
Profile 7 (P7)
Phase/
Amplitude
Register
(0x1A)
USR0 (0x1B)
1
2
Data Sheet
Bit Range
(Parallel
Address)
[7:0]
(0x68)
[15:8]
(0x69)
[23:16]
(0x6A)
[31:24]
(0x6B)
[7:0]
(0x6C)
[15:8]
(0x6D)
[23:16]
(0x6E)
[31:24]
(0x6F)
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Phase Offset Word 7[7:0]
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex) 1
N/A
N/A
N/A
Open
N/A
0x00
0x08
0x00
Open
PLL lock
Read
only
A master reset is required after power up. The master reset returns the internal registers to their default values.
The DAC CAL enable bit must be manually set and then cleared after each power-up and every time REF CLK or the internal system clock is changed. This initiates an
internal calibration routine to optimize the setup and hold times for internal DAC timing. Failure to calibrate degrades ac performance or makes the part
nonfunctional.
Rev. D | Page 38 of 48
Data Sheet
AD9914
Mnemonic
Open
VCO cal enable
[23:18]
17
Open
Parallel port streaming
enable
16
15
14
13
12
11
10
Open
Description
1 = initializes the auto internal PLL calibration. The calibration is required if the PLL is to
provide the internal system clock. Must first be reset to Logic 0 before another calibration can
be issued.
Open.
0 = the 32 bit parallel port needs an I/O update to activate or register any FTW, POW, or AMP
data presented to the 32-bit parallel port.
1 = the parallel port continuously samples data on the 32 input pins using SYNC_CLK and
multiplexes the value of FTW/POW/AMP accordingly, per the configuration of the F0 to F3 pins,
without the need of an I/O update. Data must meet the setup and hold times of the SYNC_CLK
rising edge. If the function pins are used dynamically to alter data between parameters, they
must also meet the timing of the SYNC_CLK edge.
0 = cosine output of the DDS is selected.
1 = sine output of the DDS is selected (default).
Ineffective unless CFR2[19] = 1.
0 = normal operation of the digital ramp timer (default).
1 = interrupts the digital ramp timer operation to load a new linear ramp rate (LRR) value any
time I/O_UPDATE is asserted or a PS[2:0] change occurs.
0 = normal operation of the DRG accumulator (default).
1 = the digital ramp accumulator is reset for one cycle of the DDS clock (SYNC_CLK), after
which the accumulator automatically resumes normal operation. As long as this bit remains
set, the ramp accumulator is momentarily reset each time an I/O update is asserted or a PS[2:0]
change occurs. This bit is synchronized with either an I/O update or a PS[2:0] change and the
next rising edge of SYNC_CLK.
0 = normal operation of the DDS phase accumulator (default).
1 = synchronously resets the DDS phase accumulator anytime I/O_UPDATE is asserted or a
profile change occurs.
0 = normal operation of the digital ramp generator (default).
1 = asynchronous, static reset of the DRG accumulator. The ramp accumulator remains reset as
long as this bit remains set. This bit is synchronized with either an I/O update or a PS[2:0]
change and the next rising edge of SYNC_CLK.
0 = normal operation of the DDS phase accumulator (default).
1 = asynchronous, static reset of the DDS phase accumulator as long as this bit is set. This bit is
synchronized with either an I/O update or a PS[2:0] change and the next rising edge of
SYNC_CLK.
Open.
Rev. D | Page 39 of 48
AD9914
Bits
9
Mnemonic
External OSK enable
OSK enable
Digital power-down
DAC power-down
4
3
Open
External power-down control
2
1
Open
SDIO input only
Data Sheet
Description
0 = manual OSK enabled (default).
1 = automatic OSK enabled.
Ineffective unless CFR1[8] = 1.
0 = OSK disabled (default).
1 = OSK enabled. To engage any digital amplitude adjust using DRG, profile, or direct mode via
the 32-bit parallel port, or OSK pin, this bit must be set.
This bit is effective without the need for an I/O update.
0 = clock signals to the digital core are active (default).
1 = clock signals to the digital core are disabled.
0 = DAC clock signals and bias circuits are active (default).
1 = DAC clock signals and bias circuits are disabled.
This bit is effective without the need for an I/O update.
0 = REFCLK input circuits and PLL are active (default).
1 = REFCLK input circuits and PLL are disabled.
Open.
0 = assertion of the EXT_PWR_DWN pin affects power-down.
1 = assertion of the EXT_PWR_DWN pin affects fast recovery power-down.
Open.
0 = configures the SDIO pin for bidirectional operation; 2-wire serial programming
mode (default).
1 = configures the serial data I/O pin (SDIO) as an input only pin; 3-wire serial
programming mode.
0 = configures the serial I/O port for MSB-first format (default).
1 = configures the serial I/O port for LSB-first format.
Mnemonic
Open
Profile mode enable
22
[21:20]
19
18
17
16
15
Programmable modulus
enable
Matched latency enable
14
13
Description
Open.
0 = disables profile mode functionality (default).
1 = enables profile mode functionality. Profile pins are used to select the desired profile.
See the Parallel Data Port Modulation Mode section for more details.
0 = disables parallel data port modulation functionality (default).
1 = enables parallel data port modulation functionality.
See Table 9 for details. Default is 00. See the Digital Ramp Generator (DRG) section for more
details.
0 = disables digital ramp generator functionality (default).
1 = enables digital ramp generator functionality.
See the Digital Ramp Generator (DRG) section for details.
0 = disables no-dwell high functionality (default).
1 = enables no-dwell high functionality.
See the Digital Ramp Generator (DRG) section for details.
0 = disables no-dwell low functionality (default).
1 = enables no-dwell low functionality.
0 = disables programmable modulus.
1 = enables programmable modulus.
0 = simultaneous application of amplitude, phase, and frequency changes to the DDS arrive at
the output in the order listed in Table 2 under data latency (pipe line delay)(default).
1 = simultaneous application of amplitude, phase, and frequency changes to the DDS arrive at
the output simultaneously.
0 = disables frequency jump.
1 = enables frequency jump mode. Must have the digital generator DRG enabled for this feature.
0 = disables the DROVER output.
1 = enables the DROVER output.
Rev. D | Page 40 of 48
Data Sheet
Bit(s)
12
11
Mnemonic
Open
SYNC_CLK enable
10
SYNC_CLK invert
9
[8:0]
Reserved
Open
AD9914
Description
Open.
0 = the SYNC_CLK pin is disabled and forced to a static Logic 0 state; the internal clock signal
continues to operate and provide timing to the data assembler.
1 = the internal SYNC_CLK signal appears at the SYNC_CLK pin (default).
0 = normal SYNC_CLK polarity; Q data associated with Logic 1, I data with Logic 0 (default).
1 = inverted SYNC_CLK polarity.
Keep logic 0.
Open.
Mnemonic
Open
Input divider reset
[21:20]
Input divider
19
Doubler enable
18
PLL enable
17
16
[15:8]
Feedback divider N
7
6
Open
Manual ICP selection
[5:3]
2
ICP
Lock detect enable
[1:0]
Minimum LDW
Description
Open.
0 = disables input divider reset function.
1 = initiates an input divider reset.
Divides the input REF CLK signal by one of four values (1, 2, 4, 8). Bit 17 must be set to Logic 1
to enable the PLL input divider.
00 = divide by 1.
01 = divide by 2.
10 = divide by 4.
11 = divide by 8.
0 = disables the doubler feature.
1 = enables the doubler feature. Must have the doubler clock edge bit set to Logic 1 to utilize
this feature.
0 = disables the internal PLL.
1 = the internal PLL is enabled and the output generates the system clock. The PLL must be
calibrated when enabled via VCO calibration in Register CFR1, Bit 24.
0 = disables the PLL input divider function.
1 = enables the PLL input divider function.
0 = disables the internal doubler circuit.
1 = enables the doubler circuit. Must have doubler enable bit set to Logic 1 to utilize this
feature.
The N divider value in Bits[15:8] is one part of the total PLL multiplication available. The second
part is the fixed divide by two element in the feedback path. Therefore, the total PLL
multiplication value is 2N. The valid N divider range is 10 to 255. The default N value for
Bits[15:8] = 25. This sets the total default PLL multiplication to 50 or 2N.
Open.
0 = the internal charge pump current is chosen automatically during the VCO calibration
routine (default).
1 = the internal charge pump is set manually per Table 7.
Manual charge pump current selection. See Table 7.
0 = disables PLL lock detection.
1 = enables PLL lock detection.
Selects the number of REF CLK cycles that the phase error (at the PFD inputs) must remain
within before a PLL lock condition can be read back via Bit 24 in Register 0x00.
00 = 128 REF CLK cycles.
01 = 256 REF CLK cycles.
10 = 512 REF CLK cycles.
11 = 1024 REF CLK cycles.
Rev. D | Page 41 of 48
AD9914
Data Sheet
24
Mnemonic
Open
Auxiliary divider
power-down
DAC CAL clock
power-down
DAC CAL enable
[23:0]
(See description)
25
Description
Open
0 = enables the SYNC OUT circuitry.
1 = disables the SYNC OUT circuitry
0 = enables the DAC CAL clock if Bit 26 in Register 0x03 is Logic 0.
1 = disables the DAC CAL clock.
1 = initiates an auto DAC calibration. The DAC CAL calibration is required at power-up and
any time the internal system clock is changed.
These bits must always be programmed with the default values listed in the default column
in Table 14.
Mnemonic
Digital ramp lower limit
Description
32-bit digital ramp lower limit value.
Mnemonic
Digital ramp upper limit
Description
32-bit digital ramp upper limit value.
Mnemonic
Rising digital ramp
increment step size
Description
32-bit digital ramp increment step size value.
Mnemonic
Falling digital ramp
decrement step size
Description
32-bit digital ramp decrement step size value.
Rev. D | Page 42 of 48
Data Sheet
AD9914
Mnemonic
Digital ramp negative slope
rate
Digital ramp positive slope
rate
Description
16-bit digital ramp negative slope value that defines the time interval between decrement
values.
16-bit digital ramp positive slope value that defines the time interval between increment
values.
Mnemonic
Lower frequency jump
point
Description
32-bit digital lower frequency jump value. Any time the lower frequency jump value is
reached during a frequency sweep, the output frequency jumps to the upper frequency
value instantaneously and continues frequency sweeping in a phase-continuous manner.
Mnemonic
Upper frequency jump
point
Description
32-bit digital upper frequency jump value. Any time the upper frequency jump value is
reached during a frequency sweep, the output frequency jumps to the lower frequency
value instantaneously and continues frequency sweeping in a phase-continuous manner.
Rev. D | Page 43 of 48
AD9914
Data Sheet
Profile Registers
There are 16 serial I/O addresses (Address 0x0B to Address 0x01A)
dedicated to device profiles. Eight of the 16 profiles house up to
eight single tone frequencies. The remaining eight profiles contain
the corresponding phase offset and amplitude parameters
relative to the profile pin setting. To enable profile mode, set the
profile mode enable bit in CFR2 (0x01[23]) = 1. The active
profile register is selected using the external PS[2:0] pins.
Profile 0 to Profile 7, Single Tone Registers0x0B, 0x0D, 0x0F, 0x11, 0x13, 0x15, 0x17, 0x19
Four bytes are assigned to each register.
Table 26. Bit Descriptions for Profile 0 to Profile 7 Single Tone Registers
Bit(s)
[31:0]
Mnemonic
Frequency tuning word
Description
This 32-bit number controls the DDS frequency.
Profile 0 to Profile 7, Phase Offset and Amplitude Registers0x0C, 0x0E, 0x10, 0x12, 0x14, 0x16, 0x18, 0x1A
Four bytes are assigned to each register.
Table 27. Bit Descriptions for Profile 0 to Profile 7 Phase Offset and Amplitude Registers
Bit(s)
[31:28]
[27:16]
Mnemonic
Open
Amplitude scale factor
[15:0]
Description
Open.
This 12-bit word controls the DDS frequency. Note that the OSK enable bit (0x00[8]) must
be set to logic high to make amplitude adjustments.
This 16-bit word controls the DDS frequency.
Mnemonic
Open
PLL lock
[23:0]
(See description)
Description
This is a readback bit only. If Logic 1 is read back, the PLL is locked. Logic 0 represents a
nonlocked state.
These bits must always be programmed with the default values listed in the default column
in Table 14.
Rev. D | Page 44 of 48
Data Sheet
AD9914
OUTLINE DIMENSIONS
12.10
12.00 SQ
11.90
0.30
0.23
0.18
0.60 MAX
0.60
MAX
88
67
66
PIN 1
INDICATOR
PIN 1
INDICATOR
0.50
BSC
11.85
11.75 SQ
11.65
0.50
0.40
0.30
22
23
45
44
BOTTOM VIEW
TOP VIEW
0.70
0.65
0.60
12 MAX
0.85
0.75
SEATING
PLANE
10.50
REF
0.045
0.025
0.005
COPLANARITY
0.08
0.138~0.194 REF
07-02-2012-B
*0.90
6.70
REF SQ
EXPOSED PAD
ORDERING GUIDE
Parameter 1
AD9914BCPZ
AD9914BCPZ-REEL7
AD9914/PCBZ
1
Temperature Range
40C to +85C
40C to +85C
Package Description
88-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
88-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
Rev. D | Page 45 of 48
Package Option
CP-88-5
CP-88-5
AD9914
Data Sheet
NOTES
Rev. D | Page 46 of 48
Data Sheet
AD9914
NOTES
Rev. D | Page 47 of 48
AD9914
Data Sheet
NOTES
Rev. D | Page 48 of 48