Nadeem Zaki

EEG Design Graduate Project

Graduate Design Project

EEG by Nadeem Zaki
Fall 2014 EE 385J
Dr. Pearce

EE 385J Dr. Pearce

Nadeem Zaki

EEG Design Graduate Project

EE 385J Dr. Pearce

Electroencephalography Signal Properties (from Webster textbook)

Signal Range: 25 100 V
Frequency Range: 0.1 100 Hz
Smaller electrodes lead to high source impedance must have high input impedance
Small signals lead to common mode voltages need high CMRR and low noise amplifiers
Analog to Digital Converter
I will assume an ADC with a signal range of 10 V
Gain=

10 V
=133,333
75 V

Block Diagram
Fp1
Ref
GND

INA
AD620
G = 11

Passive HPF
Fc = 0.1 Hz

Non-Inverting Amp Inverting AmpActive LPF CA3140

CA3140
CA3140
Fc = 100 Hz G = 20
G = 20
G = 30
VOu

The Fp1 electrode is placed on the forehead of the patient offset slightly to the left, the reference
electrode is placed directly in the center of the patients forehead. An identical circuit design can
be used to incorporate more electrodes (Fp2). The first stage must be an Instrumentation
Amplifier to reject the common mode noise between the Fp1 and Reference electrodes.
Optimally, as much gain as possible would be put on the first stage (INA) to reduce total noise.
However, a DC common mode voltage of on the order of 100 mV is to be expected and
amplifying this gain too much will cause the output voltage to exceed the limits of the following
stages. The passive HPF filter rejects the DC component of the signal and is the second stage to
prevent railing out the following amplifiers. The total gain of this design is 132,000 slightly less
than 133,333 to ensure the no signal is amplified past the range of the ADC. DC offset
calibration for this design can be performed by adding a potentiometer between the offset pins of
the CA3140 in the final stage. Gain calibration can be adjusted by replacing R9 with a
potentiometer (or resistors in series with a potentiometer to allow for finer tuning, also it is
recommended to use a potentiometer with a high number of turns) then passing known signals
within the acceptable range into the Fp1 and Ref nodes and adjusting the gain accordingly.
However, measures were taken in the initial design to leave a margin for error in both gain and
DC offset that can be compensated digitally.

Nadeem Zaki

EEG Design Graduate Project

EE 385J Dr. Pearce

First Stage: Instrumentation Amplifier

I chose to use AD620 for the first stage because it has a great CMRR and high input impedance
needed for an EEG. It also has a large supply voltage range which will alleviate constraints on
power supply design.
RG =

49.4 k
Gain1

Gain=11 RG =4.9 k =200 + 4.7 k

I decided to use two resistors in series to provide the exact gain I planned for rather than readjust
the gain of the other stages. The drawback is that two resistors will have a separate errors and
that could increase variability in my expected gain. However, I have left room for error in the
gain without losing any signal, if possible I will purchase higher quality resistors for this section.
Since, EEG analysis is generally based on frequency and not amplitude this will also not be a
huge factor in the final use of the product. If my boss/customer requires an exact amplitude I can
readjust the gain across the stages of my design, or I can order non-standard resistors for this part
of the design. In addition, I can add an offset adjustment to one of the later stages, but currently
as signal amplitude is not an important part of EEG read outs or analysis I have not decided to
add these constraints to my design.
Second Stage: Passive High Pass Filter

Fc = 0.1 Hz
0.1

1
2 RC

RC 1.59

R1=1.8 M C 1=910 nF
3

Nadeem Zaki

EEG Design Graduate Project

EE 385J Dr. Pearce

A passive high pass filter was chosen instead of an active high pass filter because a low cutoff
frequency is required. The resistor required to produce a filter with such a low cutoff frequency
is going to be very large and to produce gain an even larger resistor will be needed which will
introduce significant capacitive resistance. However, with a passive low pass filter follow by a
non-inverting amplifier this issue is avoided. A 910 nF capacitor is selected because larger
capacitance requires polar capacitors, combined with a 1.8 M resistor we will have a cutoff
frequency of 0.097 Hz. A cutoff frequency slightly lower than required ensures no signal will be
lost.
Third Stage: Non-Inverting Amplifier

Gain=20=1+

R2
R3

R2=19 R3

R4 =R1R2 R 3

R2=4.3 k R 3=2.2 k R 4=1.8 M

The non-inverting amplifier provides the high input impedance needed following the passive
high pass filter. R2 and R3 are selected to provide a gain slightly above 19 (error is less than 5%
which is makes it insignificant relative to expected error of resistors themselves). R4 must be 1.8
M to compensate input bias currents from the previous stage. 1.8 M is at the limit of
recommended feedback resistor values, but this is the design trade off necessary to meet the
constraints of the previous stage. Other potential solutions would involve using two polar
capacitors to allow for a higher capacitance and lower resistance in the HPF. I chose the CA3140
for the op amps in my design due to its high input resistance, low input bias current and high
speed performance. The high input resistance is essential in this stage since it follows a passive
high pass filter (although late an isolation amplifier is inserted before this stage). The low input
bias current helps account for any error in the balancing between resistors connected to the
differential input terminals of my op amps. The high speed performance is a benefit for analog
applications although the 100 Hz cutoff in the following stages is not an extremely high
frequency. In addition the wide supply voltage range that the CA3140 can handle eases the
design constraints on my power supply and matches the AD620s range.
Fourth Stage: Inverting Amplifier

Nadeem Zaki

Gain=30=

EEG Design Graduate Project

R5
R6

R7=R 5 R6

EE 385J Dr. Pearce

R5=360 k R6 =12k R7 =11 k

Here values were chosen for R5 and R6 to provide a gain of 30 and the ability to compensate for
input current bias with a common resistor value for R7. Note that the inversion of the signal that
occurs in this stage is reversed in the next stage with an active low pass filter.
Fifth Stage: Active Low Pass Filter

Fc =100 Hz

Gain=20=

1
2 R9C2

R8
R9

R9 C2 0.00159

R10=R8 R 9

R8=240 k R9 =12 k R10 =11 C 2=6.2 nF

The combination of R9 and C2 yields a cutoff frequency of 106 Hz, which is higher than the
required cutoff ensuring all signal will pass through. The resistor values were chosen to provide a
gain of 20 and good values for using R10 to compensate for input current bias.
Combined Stages Schematic
5

Nadeem Zaki

EEG Design Graduate Project

EE 385J Dr. Pearce

Power Supply
The power supply needs to convert 120 Vac to 15Vdc because that is within the range of the
potential supply voltages for the AD620 and CA3140. Since, the power supply is only being used
to provide supply voltages and I have already taken precautions to keep the signals DC
component from being amplified (low INA gain and HPF as the second stage) I can afford a
larger ripple in the power supply voltage. Strictly speaking I need to keep the supply voltages
between 10V and 18V to avoid railing in the final stage and to stay within the recommended
supply voltages for the parts I have chosen. I will choose a conservative ripple of 2 V which will
keep me well within that range (more than 2 V above minimum 10V requirement). The AD620
needs 90 mA current, I will supply more current to allow for multiple channels with a single
power supply in the future. Each of the op amp stages requires 4 mA of power supply and once
again I will overestimate to allow for expansion of my design (potentially power ADC) without
changes to the power supply. For safety, I will add an ISO122 (isolation amplifier) between the
passive HPF and the non-inverting amplifier. The high input impedance of the isolation amplifier
will maintain optimal operation of the HPF while still allowing DC signals to be rejected in the
second stage. All the active components will be connected to earth ground while the AD620 is
connected to an isolated power supply.
I will implement double shielded transformers with a 5:1 ratio to step down the voltage from 120
Vrms to 24 Vrms and limit capacitive coupling to provide isolation for electrical safety. Even
though shielding is more expensive, it is worth the expense to ensure safe operation. I will use a
center-tapped secondary transformer to split the 24 Vrms into two 12 Vrms leads that are 180 out
of phase. Connecting each of these leads to a diode bridge which will allow for a fully rectified
16.3 Vpeak signal with a peak-to-peak time of 8.33 ms assuming 60 Hz power (US standard). I
will add a filter capacitor to reduce the ripple between voltage peaks and allow for a DC signal.
As discussed above, my design does not have stringent requirements on the ripple so I will not
need to add a regulator. However, future design iterations and further consideration of the final
ADC might require a regulator to be added.

Nadeem Zaki

EEG Design Graduate Project

12V rms1.4140.7=16.3 V peak

V ripple =

IC t
C

C=

EE 385J Dr. Pearce

180 mA8.33 ms
=750 F
2V

V peak 16.3
=
=90.3 R11=82
IC
0.180
Using a 750 F filter capacitor and 82 load resistor will allow more supply current than
required while ensuring the use of easily accessible parts. The isolated power supply is shown
below with the primary transformer connected to earth ground and a wall outlet and the
secondary transformer connected to an isolated ground from the central reference lead.

Nadeem Zaki

EEG Design Graduate Project

EE 385J Dr. Pearce

Complete Design

Final Thoughts
The next time I review this design I would like to review a few possibilities for changes. Can I
add more channels and sensors without entirely duplicating the circuit, for instance more EEG
channels with the same reference sensor for calibration and one power supply to fuel all
channels. I put no constraints on this design for portability or size which are both important
facets of a usable EEG, I can other parts or different topologies that would make this design
more portable. In addition I could review the possibility of a battery powered design. A review of
the noise production and common mode rejection of this circuit would indicate whether a driven
right leg is advisable or fewer stages could be considered. I am currently leaving it to the user to
digitally provide a 60 Hz notch filter to avoid removing any signal they may want to observe.
However, the presence of such a strong noise component is probably decreasing the quality of
my signal and could potentially cause some stages to hit their supply voltage if the noise is very
strong. Other noise components from the clinical setting could also have an effect on an EEG and
they should be considered. In addition, there is possible error in my gain and DC offset that will
arise over time, a design with adjustable offset or gain may be feasible in future iterations.
Another potential change is the power supply design, I am not using a voltage regulator and
unreliable power source may have undesirable effects on my design. Consideration should be
given to the reliability and cost of implementing a voltage regulator. Finally, financial costs and
power consumption of this design were not heavily considered in the design process. Before
8

Nadeem Zaki

EEG Design Graduate Project

EE 385J Dr. Pearce

implementing this design heavy consideration should be given to changes that will reduce cost
and conserve power.