Design and Implementation of An SDR Receiver For The VHF Band

Institutionen fr systemteknik
Department of Electrical Engineering

Examensarbete
Design and Implementation of an SDR receiver for

the VHF band
Examensarbete utfrt i Elektroniksystem

vid Tekniska hgskolan i Linkping
av
Emad Athari & Petter Lerenius
LITH-ISY-EX--07/3946--SE
Linkping 2007

Linkpings universitet
SE-581 83 Linkping, Sweden
Linkpings tekniska hgskola

581 83 Linkping
Design and Implementation of an SDR receiver for

the VHF band
Examensarbete utfrt i Elektroniksystem

vid Tekniska hgskolan i Linkping
av
Emad Athari & Petter Lerenius
Handledare:
Per Lwenborg
ISY, Linkpings universitet
Jonas Nilsson
Signal Processing Devices Sweden AB
Examinator:
Per Lwenborg
ISY, Linkpings universitet
Linkping, 31 January, 2007
Avdelning, Institution
Division, Department
Datum
Date
Elektroniksystem
SE-581 83 Linkping, Sweden
Sprk
Language
Rapporttyp
Report category
ISBN
Svenska/Swedish
Licentiatavhandling
ISRN

Engelska/English

Examensarbete
C-uppsats
D-uppsats
vrig rapport
2007-01-31
Serietitel och serienummer ISSN
Title of series, numbering

URL fr elektronisk version
http://www.es.isy.liu.se
http://www.ep.liu.se/2007/3946
Titel
Title
Design och implementation av en SDR-mottagare fr VHF-bandet

Design and Implementation of an SDR receiver for the VHF band
Frfattare Emad Athari & Petter Lerenius

Author
Sammanfattning
Abstract
The purpose of this thesis work is to examine the possibility of building a softwaredefined radio (SDR) for the VHF-band. The goal is to accomplish this with as few
components as possible, thus cutting down the size and the production cost.
An SDR solution means that the sampling of the signal is done as close to the
antenna as possible. The wide bandwidth needed in such a product is achieved
by using SP Devices algorithm for time-interleaved ADCs. Two hardware prototypes and two versions of the software were designed and implemented using this
technology.
They were also analyzed within this thesis work. The results proved to be good,
and the possibilities to produce a commercial software-defined radio receiver for
the VHF-band are good.
Nyckelord
Keywords
SDR, software-defined radio, radio, GMSK, receiver, FPGA
Abstract
The purpose of this thesis work is to examine the possibility of building a softwaredened radio (SDR) for the VHF-band. The goal is to accomplish this with as few
components as possible, thus cutting down the size and the production cost.
An SDR solution means that the sampling of the signal is done as close to the
antenna as possible. The wide bandwidth needed in such a product is achieved
by using SP Devices algorithm for time-interleaved ADCs. Two hardware prototypes and two versions of the software were designed and implemented using this
technology.
They were also analyzed within this thesis work. The results proved to be good,
and the possibilities to produce a commercial software-dened radio receiver for
the VHF-band are good.
Sammanfattning
Syftet med det hr examensarbetet r att utreda mjligheten att bygga en mjukvarudenierad radiomottagare (SDR) fr VHF-bandet. Mlet r att gra detta
genom att anvnda s f komponenter som mjligt, och drigenom minska storleken och produktionskostnaden.
En SDR lsning ger att samplingen kommer att ske s nra antennen som
mjligt. Den stora bandbredd som behvs fr en sdan produkt uppns genom
att anvnda SP Devices algoritm fr att tidsinterleava hghastighets ADC:er.
Tv hrdvaruprototyper och tv versioner av mjukvaran har designats och implementerats.
Analyserna har visat bra resultat, och mjligheterna att bygga en komersiell
mjukvarudenierade radiomottagare fr VHF-bandet ses som goda.
Acknowledgments
The completion of this thesis had not been possible without the help and support
that we have received throughout this work. Therefore we would like to thank the
people the persons that has made this possible.
Firstly we would like to thank our supervisors Per Lwenborg, at the Division
of Electronics Systems at Linkping University, and Jonas Nilsson, at SP Devices,
for their enormous support and for believing in us.
We would also like to thank all of the personnel at SP Devices and Peter,
Christian, Marcus and Anders for great help and support.
Last but not least we would like to thank our families and friends for their
endless love and support.
vii
Abbreviations
ACK
AD
ADC
AGC
BB
BER
BPF
BW
BWch
DAC
dB
dBc
dBFS
dBm
DC
DDS
DSP
DR
EMC
ENOB
FFT
FIR
FPGA
FSR
GMSK
HDLC
IF
IP3
IIP3
IMD
IMD3
IQ
IR
LNA
LO
Acknowledgement
Analog-to-Digital
Analog-to-Digital Converter
Automatic Gain Control
Baseband
Bit Error Rate
Bandpass Filter
Bandwidth
Channel Bandwidth
Digital-to-Analog Converter
Decibel
Decibel relative to the carrier
Decibel relative to Full Scale Range
Decibel relative to 1 mW
Direct Current
Direct Digital Sythesis
Digital Signal Processing
Dynamic Range
Electromagnetic Compatibility
Eective Number of Bits
Fast Fourier Transform
Finite length Impulse Response
Field-Programmable Gate Array
Full Scale Range
Gaussian Minimum Shift Keying
High Level Data Link Control
Intermediate Frequency
Third-Order Intercept Point
Third-Order Input Intercept Point
Intermodulation Distortion
Third-Order Intermodulation Distortion
In phase and Quadrature
Image Rejection
Low Noise Amplier
Local Oscillator
ix
x
LPF
LSB
MAC
NF
NRZ
NRZI
OIP3
PER
PG
RF
SAW
SDR
SFDR
SNDR
SNR
SNRreq
v4
v5
VGA
VHF
Lowpass Filter
Least Signicant Bit
Multiply and Accumulate
Noise Figure
Non Return to Zero
Non Return to Zero Inverted
Third-Order Output Intercept Point
Packet Error Rate
Process Gain
Radio Frequency
Surface Acustic Wave
Software Dened Radio
Spurious-Free Dynamic Range
Signal-to-Noise and Distortion Ratio
Signal-to-Noise Ration
SNR required
Xilinx virtex 4
Xilinx virtex 5
Variable Gain Amplier
Very High Frequency
Contents
1 Introduction
1.1 Background . . . . . . . . . . .
1.2 Purpose and Method . . . . . .
1.3 Prerequisites . . . . . . . . . .
1.4 Tools . . . . . . . . . . . . . . .
1.4.1 Protel . . . . . . . . . .
1.4.2 Matlab and Simulink . .
1.4.3 Xilinx ISE . . . . . . . .
1.4.4 Microsoft Visual Studio
1.5 Restrictions . . . . . . . . . . .
1.6 Report Disposition . . . . . . .
1.7 Reading Instructions . . . . . .
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1
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3
3
ADCs
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5
5
6
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7
8
3 Superheterodyne vs. SDR

3.1 Introduction . . . . . . . . . . . . . . . . .
3.2 Traditional Superheterodyne RF Receiver
3.2.1 Advantages . . . . . . . . . . . . .
3.2.2 Disadvantages . . . . . . . . . . . .
3.3 Software-Dened Radio Receiver . . . . .
3.3.1 Advantages . . . . . . . . . . . . .
3.3.2 Disadvantages . . . . . . . . . . . .
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11
11
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4 Basic RF Receiver Concepts

4.1 Signal-to-Noise Ratio . . . . . . . . . . . . . .
4.2 Receiver Noise . . . . . . . . . . . . . . . . .
4.3 Intermodulation Distortion & Intercept Point
4.4 Dynamic Range . . . . . . . . . . . . . . . . .
4.5 Spurious-Free Dynamic Range . . . . . . . . .
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15
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18
2 Linearizer
2.1 Problems with Interleaved
2.1.1 Gain Mismatch . .
2.1.2 Oset Error . . . .
2.1.3 Time-Skew . . . .
2.2 The Solution . . . . . . .
xi
xii
Contents
4.6
4.7
Eective Number of Bits . . . . . . . . . . . . . . . . . . . . . . . .

Oversampling in Analog-to-Digital
Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Requirements
5.1 Bandwidth . . . . . . . . . . . . . . . .
5.2 Sensitivity . . . . . . . . . . . . . . . . .
5.3 Intermodulation Response Rejection and
Blocking . . . . . . . . . . . . . . . . . .
5.4 Adjacent Channel Selectivity . . . . . .
5.5 Signal-to-Noise Ratio . . . . . . . . . . .
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22
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6 Analog Front-End
6.1 Front-End Architecture . . . . . . . . . . .
6.2 Choise of Components . . . . . . . . . . . .
6.2.1 ADC . . . . . . . . . . . . . . . . . .
6.2.2 LNA and VGA . . . . . . . . . . . .
6.2.3 Analog Filters . . . . . . . . . . . .
6.2.4 FPGA . . . . . . . . . . . . . . . . .
6.2.5 USB-to-UART Interface . . . . . . .
6.2.6 DAC . . . . . . . . . . . . . . . . . .
6.2.7 Crystal Oscillator and Clock Buer .
6.2.8 Linear Voltage Regulators . . . . . .
6.3 Theoretical Calculations . . . . . . . . . . .
6.3.1 SNR . . . . . . . . . . . . . . . . . .
6.3.2 IMD3 . . . . . . . . . . . . . . . . .
6.4 PCB and EMC[13] . . . . . . . . . . . . . .
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25
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31
31
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36
37
7 Data Packets
7.1 The Packet . . . . . . . . . .
7.1.1 Training Sequence . .
7.1.2 Start Flag . . . . . . .
7.1.3 Data . . . . . . . . . .
7.1.4 Frame Check Sequence
7.2 Bit Stung . . . . . . . . . .
7.3 NRZI . . . . . . . . . . . . .
7.4 GMSK . . . . . . . . . . . . .
7.4.1 Gaussian lter . . . .
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39
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8 FPGA
8.1 Hardware Prerequisites . .
8.1.1 DSP-slices . . . . .
8.2 First Attempt . . . . . . .
8.2.1 Linearizer . . . . .
8.2.2 First Decimation .
8.2.3 I - Q Modulation .
8.2.4 Second Decimation
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Contents
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47
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57
58
9 PC
9.1 Communication . . . . . . . . .
9.2 Matlab . . . . . . . . . . . . . .
9.2.1 Symbol Syncronization .
9.2.2 Decode NRZI . . . . . .
9.2.3 Extraction of the Data .
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61
61
61
61
63
63
10 Tests and Results

10.1 Filter Bandwidths . . . . . . . . . . . . .
10.1.1 Board 1 . . . . . . . . . . . . . . .
10.1.2 Board 2 . . . . . . . . . . . . . . .
10.2 External LNA . . . . . . . . . . . . . . . .
10.3 SNR . . . . . . . . . . . . . . . . . . . . .
10.3.1 Variable Gain - Fixed Signal Level
10.3.2 Fixed Gain - Variable Signal Level
10.4 Sensitivity Test . . . . . . . . . . . . . . .
10.4.1 Board 1 . . . . . . . . . . . . . . .
10.4.2 Board 2 . . . . . . . . . . . . . . .
10.5 Blocking Test . . . . . . . . . . . . . . . .
10.6 Intermodulation Test . . . . . . . . . . . .
10.7 Adjacent Channel Selectivity . . . . . . .
10.8 Power Consumption . . . . . . . . . . . .
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65
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74
75
75
11 Conclusions and Future Work

11.1 Conclusions . . . . . . . . . .
11.1.1 Test Results . . . . . .
11.1.2 Hardware . . . . . . .
11.1.3 FPGA . . . . . . . . .
11.2 Future Work . . . . . . . . .
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77
77
77
78
78
79
8.3
8.4
8.2.5 Third Decimation .

8.2.6 Phase Dierentiator
8.2.7 FIFO . . . . . . . .
8.2.8 Data Transfer . . . .
8.2.9 DAC Controller . . .
Second attempt . . . . . . .
8.3.1 Linearizer . . . . . .
8.3.2 IQ-modulation . . .
8.3.3 Decimation . . . . .
8.3.4 Phase Dierentiator
8.3.5 FIFO . . . . . . . .
8.3.6 Serial Interface . . .
8.3.7 DAC Controller . . .
Calculations . . . . . . . . .
8.4.1 Scaling . . . . . . .
8.4.2 Word Length . . . .
xiii
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xiv
References
Contents
81
Contents
xv
List of Figures
2.1
2.2
2.3
2.4
2.5
2.6
Eect of problems that occur when interleaving ADCs. . . . . . . .

Result of a gain error in an ADC. . . . . . . . . . . . . . . . . . . .
Result of an oset error in an ADC. . . . . . . . . . . . . . . . . .
Result of time-skew in an ADC. . . . . . . . . . . . . . . . . . . . .
The block diagram of the linearizer . . . . . . . . . . . . . . . . . .
Interleaved sequencies with missmatch, before and after linearization.
3.1
Superheterodyne receiver architecture . . . . . . . . . . . . . . . .
11
4.1
Intercept Points/1-dB Compression Points . . . . . . . . . . . . . .
17
6.1
6.2
6.3
6.4
6.5
The architecture of the analog front-end. .

BPF1 - 1st order bandpass lter. . . . . .
BPF2 - 2nd order bandpass lter. . . . . .
BPF1 - 1st order bandpass lter. . . . . .
The conguration for IMD measurements.
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25
29
29
30
36
7.1
7.2
7.3
7.4
7.5
Block schematic for the modulation. . . . . . . . . . . .

A packets dierent components. . . . . . . . . . . . . .
The training sequence before and after NRZI encoding.
An example bit stream which has been bit stued. . . .
An example bit stream encoded with NRZI . . . . . . .
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39
39
40
41
41
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.14
8.15
8.16
8.17
8.18
DSP48-slice in virtex 4. . . . . . . . . . . . . . . . . . . . . .
DSP48E-slice in virtex 5. . . . . . . . . . . . . . . . . . . . .
System overview for the rst attempt. . . . . . . . . . . . . .
The frequency response for the rst decimation lter. . . . . .
Impulse response for the second decimation lter. . . . . . . .
Impulse response for the third decimation lter. . . . . . . . .
System overview for the second attempt. . . . . . . . . . . . .
The dierence between the two DDS blocks. . . . . . . . . . .
The frequency response for the complete decimation lter. . .
A zoomed in portion of the frequency response in Figure 8.9.
Impulse response for the rst decimation lter. . . . . . . . .
Impulse response for the lter h2 . . . . . . . . . . . . . . . .
Impulse response for the lter h3. . . . . . . . . . . . . . . . .
Impulse response for the lter h4 . . . . . . . . . . . . . . . .
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44
45
45
46
47
48
50
51
52
52
53
53
54
54
55
55
56
56
9.1
9.2
9.3
The impulse response for the correlation lter. . . . . . . . . . . .

An example output from the correlation lter. . . . . . . . . . . . .
Zoomed in on the detected message. . . . . . . . . . . . . . . . . .
62
62
63
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5
7
7
8
8
9
xvi
Contents
9.4
An example bit stream decoded from NRZI. . . . . . . . . . . . . .
63
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
Frequency response for board 1. . . . . . . . . . . . . . .

Frequency response for board 2. . . . . . . . . . . . . . .
Setup for SNR test, without and with external LNA. . .
The setup for the sensitivity test for board 1. . . . . . .
The setup for the sensitivity test for board 1 with LNA.
The setup for the sensitivity test for board 2. . . . . . .
The setup for the sensitivity test for board 2 with LNA.
The setup for the blocking test. . . . . . . . . . . . . . .
Plot from the IMD3 test on board 2. . . . . . . . . . . .
66
66
67
70
71
72
72
73
74
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List of Tables
2.1
Time-interleaved ADC matching requirements at 180 MHz clock

frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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6.1
6.2
6.3
6.4
6.5
SNR requirement at dierent sampling frequencies.

Properties for the VGA. . . . . . . . . . . . . . . .
Component values for the analog bandpass lters. .
Current consumption of the rst PCB . . . . . . .
Current consumption of the second PCB . . . . . .
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27
28
31
32
33
7.1
Packet components and their sizes. . . . . . . . . . . . . . . . . . .
40
8.1
8.2
L2 -norm scaling of the decimation lters. . . . . . . . . . . . . . .

SNR for dierent word lengths. . . . . . . . . . . . . . . . . . . . .
58
59
10.1
10.2
10.3
10.4
Properties for the external LNA. . . . . . . . . . . . . . . . . . . .

SNR for a -70dBm signal without and with external LNA on board 1.
SNR for a -70dBm signal without and with external LNA on board 2.
SNR for various signal levels without and with external LNA on
board 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.5 SNR for various signal levels without and with external LNA on
board 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.6 Sensitivity test using PCB 1. . . . . . . . . . . . . . . . . . . . . .
10.7 Sensitivity test using PCB 1 with external LNA. . . . . . . . . . .
10.8 Sensitivity test using PCB 2. . . . . . . . . . . . . . . . . . . . . .
10.9 Sensitivity test using PCB 2 with external LNA. . . . . . . . . . .
10.10IMD test performed on board 2. . . . . . . . . . . . . . . . . . . .
67
68
68
69
70
71
72
73
74
11.1 Results from the tests . . . . . . . . . . . . . . . . . . . . . . . . .
77
69
xviii
Contents
Chapter 1
Introduction
1.1
Background
Signal Processing Devices Sweden AB (SP Devices) was started in 2003, with
an algorithm that solves the problems that occur when time-interleaving high
precision ADCs. The algorithm was a result of research done by Hkan Johansson
and Per Lwenborg at Linkping University.
The possibility of time-interleaving ADCs opens up many new elds for digitalization. For example, with two 14-bit time-interleaved ADCs, sampling speeds
of above 400 MSps can be achieved. This means that the Nyquist criterion can be
met for a 200 MHz bandwidth.
The eld of software-dened radios (SDR) is a big research area. The SDR
can revolutionize the market of radio receivers. They are much more exible and
in some cases cheaper to produce than todays receivers.
The goal with this thesis is to show that SP Devices algorithm applied on
two ADCs can be used to build a software-dened radio receiver for the VHFband (112-174 MHz) with as few components as possible. This thesis work was
conducted at SP Devices in Linkping.
1.2
Purpose and Method
The purpose of this thesis is to design, implement and analyze a prototype of

a software-dened radio for the VHF frequencies 112-174 MHz from idea all the
way to a working prototype. The SDR architechture will be compared with the
superheterodyne receiver architechture, which is commonly used today.
During this work an incremental method of development will be used. By
improving the design in small steps, the work will advance in steps that are easily
controlled. This will be achieved by rst building a model of the SDR in Matlab
and then implement it as a prototype in two steps.
Two versions of both the hardware and the software will be completed during
the thesis. This will make it possible to make an attempt and then rene it
1
Introduction
and correct possible errors. The two versions are analyzed and their performance
measured and compared.
1.3
Prerequisites
To grasp this thesis the reader should have some previous knowledge of electronics
and concepts like eld-programmable gate arrays (FPGAs). Also some understanding of digital signal processing and radio technology could be useful.
1.4
Tools
During the work of this thesis some software tools have been used to complete the
tasks of building a prototype. Here follows a description of the programs used and
a description of their purpose.
1.4.1
Protel
Protel is a CAD program for designing printed circuit boards (PCB) and it also
provides the possibility to do simulations on schematic level.
The schematic of the front-end architechture was drawn and simulated before
the PCB was designed. The PCB was then routed by hand before it was sent for
manufacturing at Elprint1 .
1.4.2
Matlab and Simulink
Matlab and Simulink was used to make a model of the system and to predict its
behavior. Matlab is convenient to use when dealing with simulations of digital
processing. For simulations of the analog parts it is better to use Protel.
Matlab was also used for the decoding process and to present the results during
the performance tests.
1.4.3
Xilinx ISE
Xilinx ISE is an integrated development environment (IDE) for Xilinx FPGAs. It

translates, synthesizes and routes the Verilog or VHDL code onto the designated
FPGA. In this project only Verilog was used. ISE is easy to work with and allows
code modules to be in dierent les, which makes the development process much
easier. It is free if developing for Xilinx Virtex 4 FPGAs, but needs a license when
using a Xilinx Virtex 5.
1.4.4
Microsoft Visual Studio
C code was written to produce a dynamically linked library (dll) le used by

matlab to fetch data from the usb port. It was written and compiled in the
1 http://www.elprint.se
1.5 Restrictions
Microsoft Visual Studio environment. Visual Studio is Microsofts IDE for C,

C++ and many more languages.
1.5
Restrictions
This thesis work will produce a prototype for decoding a specic kind of digital
messages that are modulated with GMSK. No other modulations will be treated
or discussed. This report analyzes the prototypes designed and it will not cover
any other solutions.
1.6
Report Disposition
This report will present the work performed during this thesis and its results. The
rst chapters cover the more theoretical parts while the later chapters describe the
work and the results.
Chapter 2 explains the problems that come up when time-interleaving ADCs,
and the solution that SP Devices has developed. Chapter 3 will explain more
about how SDR works and what the advantages are compared to the common
superheterodyne receivers that are commonly used today. It is followed by Chapter
4 that discusses the parameters of a receiver performance, while Chapter 5 presents
the requirements for this project.
The work performed in this thesis will then be presented. It starts with the
PCB and its analog front-end in Chapter 6. The data packages that are used for
testing the receivers performance is explained in Chapter 7. It is followed by the
description of the digital signal processing performed in the FPGA in Chapter 8
and the PC in Chapter 9.
The tests and their results are described in Chapter 10. Finally the conclusions
made in this thesis are presented in Chapter 11 together with some ideas of how
to continue with this work.
1.7
Reading Instructions
Those who have good knowledge in electronics and radio technologies could skip
the rst theoretical chapters, except for Chapter 5 which could be good to have
read to understand the decisions made in Chapter 6.
The most interesting chapter is probably Chapter 10 where the results are
presented.
Introduction
Chapter 2
Linearizer
To achieve high speed analog-to-digital conversion, time-interleaving multiple ADCs
seems to be a good solution. This has been used for low resolution ADCs since
1980, but higher resolutions matching problems deteriorate the quality of the signal.
An 8-bit system that provides a dynamic range of 50 dB can tolerate a gain
mismatch of 0.25% and a clock-skew error of 5 ps. This accuracy can be met by
traditional methods like, matching the physical channel layouts, using common
ADC reference voltages, prescreening devices, and active analog trimming, but
this is not enough for higher resolutions[10].
The problems that need to be considered when ADCs are interleaved are shown
in gure 2.1 were four ADCs have been time interleaved.
In this chapter the problems caused by interleaving will be discussed and then
SP Devices algorithm for solving these problems will be presented.
Resulting digital signal
Desired digital signal
Figure 2.1. Eect of problems that occur when interleaving ADCs.
2.1
Problems with Interleaved ADCs
There are three main categories of problems that arise when ADCs are interleaved.
They all come from the fact that it is impossible to manufacture two silicon chips
5
Linearizer
that are identical. The surrounding environment also aects how well the ADCs
match, e.g., if they have dierent temperature. This results in dierences in gain,
oset and timing, which aects the output in a way depicted by the Figure 2.1.
For narrowband signals, there will be unwanted spurious frequencies in the output
signal, called spurs.
ISgain(dB)
Ge
ISphase(dB)
ep
a
te
=
=
IStot(dB)

Ge
20 log(ISgain ) = 20 log
2

VF SA
gain error ratio = 1
VF SB

ep
20 log(ISphase ) = 20 log
2
a te (radians)
analog input frequency
clock skew error

20 log
(ISgain )2 + (ISphase )2
(2.1)
(2.2)
(2.3)
(2.4)
(2.5)
(2.6)
(2.7)
From equations 2.1 - 2.7 it is possible deduce that even very small divergences
between the ADCs will result in large spurs that will deteriorate the dynamic range.
Table 2.1 shows the matching requirements for a time-interleaved system[10].
Number of bits
12
12
12
14
14
14
SFDR
(dBc)
74
74
74
86
86
86
Gain Matching
(%)
0.04
0
0.02
0.01
0
0.005
Aperture Matching
(fs)
0
350
300
0
88
77
Table 2.1. Time-interleaved ADC matching requirements at 180 MHz clock frequency.
2.1.1
Gain Mismatch
The gain error cause the ADC to aect the output by changing the signal amplitude. As seen in Figure 2.2, this would not aect the signal noticeably if only
one ADC was used, but when two ADCs are interleaved it will result in aliasing
distortion. The dierences in gain between two ADCs aects the output even if it
is as small as 0.01%, as shown in equations 2.1 and 2.2. The spurs deteriorate the
signal quality, or destroy the wanted signal if they coincide.
2.1 Problems with Interleaved ADCs
Gain error
Figure 2.2. Result of a gain error in an ADC.
2.1.2
Oset Error
An ADC has a small DC oset in its output, and when using two ADCs they will
have dierent osets. When two ADCs are time-interleaved dierent osets will
result in a spur at . The gure 2.3 shows an exaggerated oset error.
Offset error
Offset
Figure 2.3. Result of an oset error in an ADC.
2.1.3
Time-Skew
Time-skew errors, or phase errors, arise when the ADCs samples are taken at the
wrong instants in time. When more than one ADC samples the signal the timeskew will be experienced as a phase error. This will cause aliasing distortion that
coincide with the gain error[10]. The time-skew is depicted in Figure 2.4, where
the samples are taken with a delay in time.
Linearizer
Time skew
Figure 2.4. Result of time-skew in an ADC.
2.2
The Solution
SP Devices has developed a clever algorithm, called linearizer, that corrects these
errors by ltering the digital result. Figure 2.5 shows a block diagram of the
linearizer.
Linearizer
ADC 1
Reconstructor
Monitor
&
Control
ADC 2
Estimator
Figure 2.5. The block diagram of the linearizer
The linearizer is purely digital and uses advanced signal processing algorithms
to correct the errors mentioned in the previous section. Since the correction is
done digitally it can function with any ADC. The linearizer could also be used to
increase the resolution while maintaining the speed.
The estimator uses a batch of data to estimate the dierent errors. These
estimates are used for calculating the lter coecient values. The coecients are
then passed on to the reconstructor. The reconstructor block consists of a lter
that corrects the errors from the dierencies in the ADCs in real time.
By using the linearizer, as depicted in Figure 2.6 it is possible to construct very
fast ADCs with high performance, that opens up many new possibilities in elds
previously not conceivable. The software-dened radio developed in this thesis is
2.2 The Solution
ADC
ADC
ADC
ADC
L
i
n
e
a
r
i
z
e
r
Figure 2.6. Interleaved sequencies with missmatch, before and after linearization.
just one example made possible by the linearizer.
10
Linearizer
Chapter 3
Superheterodyne vs. SDR

3.1
Introduction
This chapter will explain the pros and cons of the commonly used superheterodyne
radio frequency (RF) receiver and a software-dened radio (SDR) receiver. It also
covers the dierences between the two types and why the SDR receiver together
with SP Devices technology is preferred in a broadband RF receiver where small
area, low power consumption and low cost are the main requirements.
3.2
Traditional Superheterodyne RF Receiver
One of the most common RF receiver architecture types used in radio applications
for the last century and today is the superheterodyne receiver. This receiver type
is often preferred because of its great performance regarding receiver characteristics such as sensitivity and selectivity. A simple description of the traditional
superheterodyne architecture can be seen in the block diagram in Figure 3.1.
LO
LNA
RF
Filter
IF Amp
AGC Amp
BPF
BPF
IQdemodulator
Rx
IQ
Figure 3.1. Superheterodyne receiver architecture
The rst block after the antenna is an RF bandpass lter (BPF) which attenuates the undesired out-of-band frequencies. The signal is then amplied in a low
noise amplier (LNA) which amplies the signal with relatively low noise contribution. This device is the most crucial part of the receiver chain because of the
many system requirements depending on it. After the amplication and bandpass
ltering the signal is down-converted by a mixer. This process is the principle of
11
12
heterodyning which is the generation of an intermediate frequency by mixing (multiplying) the incoming high frequency signal with another high frequency signal
generated by a local oscillator (LO). The mixer circuit has signicant requirements
on linearity and noise and can cause severe DC-oset problems in the receiver.
The generated IF-signal is amplied in the IF-amplier before selection of the
desired channel in the last BPF. In the last stage the signal amplitude is adjusted
by the automatic gain control (AGC) to t the dynamic range of the analog-todigital converter(s) (ADC).
3.2.1
Advantages
A major advantage of the superheterodyne receiver is that by mixing down

the signal to lower frequencies the cost of the components reduces. Generally for RF components, such as lters and mixers, cost is proportional to
frequency[4]. This is due to the fact that low frequency components are less
complex and easier to nd/build.
The down-conversion to IF gives the receiver high selectivity i.e. high ability
of sorting out the desired signal by supressing the undesired signals. This is
because the requirements on the lters are relaxed when operating at lower
frequencies (IF), which makes it easier to build more eective selective lters
with much narrower passband.
3.2.2
Disadvantages
One of the biggest cons of the superheterodyne receiver is the amount of

external components. The wider frequency spectrum the harder it is to nd
or build narrow-passband lters to a reasonable cost, if not impossible. More
components means higher cost, higher power consumption, larger area and
higher architecture complexity.
The complexity mentioned above leads to another problem which is the low
achievable level of integration. This also depends on the fact that the high
performance of discrete components is hard to achieve in an integrated solution.
Another problem in this architecture is the mixer and local oscillator stages.
One problem that is associated with mixer circuits, besides the cost, is the
so called LO-leakage. This leakage can get mixed with the oscillator itself
and/or get picked up by the antenna and get amplied in the LNA producing
a spur.
The wanted channel is predened by hardware. Each channel require a
separate receiver which increases the need of hardware if multiple channels
are desired.
3.3 Software-Dened Radio Receiver
3.3
13
Software-Dened Radio Receiver
One of the newest and most interesting concepts in radio architecture development
is software-dened radio (SDR). In this thesis project only the receiver part is
discussed.
The basic idea of the SDR receiver is to digitalize the incoming analog RF signal
as close to the antenna as possible and then do the signal processing digitally. In an
ideal SDR receiver the ADC(s) would be attached directly to the antenna sending
the samples to some kind of processor (FPGA, DSP etc.) where the data would be
transformed/shaped as desired by software. The sampling frequency (fs ) would
have to be greater than twice the signal bandwidth to be able to reconstruct the
signal from the digital samples (Nyquist theorem)[11]. In practice this is hard to
achieve due to the fact that todays ADC:s with the required resolution, are yet
too slow to receive radio signals at higher frequencies.
In current commercial software receivers the problem mentioned above is solved
by mixing down the radio signal to a lower frequency using local oscillators, as
mentioned above in Section 3.2. This will not be the case here hence the main goal
is to signicantly reduce the use of analog hardware. Instead the problem is approached by taking advantage of time-interleaving. As it was described in Chapter
2, interleaving allows faster fs than the specied fs of the ADC. By interleaving N
ADCs the fs could be N times the fs of a single ADC. Also described in Chapter
2 was that SP Devices algorithm makes it possible to interleave high-speed ADC:s
without degrading the resolution. This technology allows high enough sampling
frequency for sampling the signal without requiring down-conversion, i.e. no mixers or local oscillators are needed.
The hardware architecture used in this project is further explained in Chapter
6.
3.3.1
Advantages
The SDR receiver has the ability to receive dierent modulation types while
using the same hardware platform.
Its funcionality can be changed by downloading and running new software
whenever desired, without any change of hardware.
Reduction/elimination of the use of analog hardware which means lower
cost, lower power consumption, smaller area needed and lower architecture
complexity.
The channel is not predened by hardware which means that any channel
within the bandwidth can be chosen by software. It is even possible to receive
several channels in parallel.
3.3.2
Disadvantages
Finding the right components, such as ampliers, for a exible front-end can
be rather hard due to problems like linearity, dymanic range, noise gure.
14

Filters are expensive and hard to design for such broadband applications.
Writing software for dierent applications can be quite complex.
Chapter 4
Basic RF Receiver Concepts

4.1
Signal-to-Noise Ratio
Signal-to-noise ratio (SNR) is the ratio between the power of the desired signal and
the average power of the noise in the system. In other words, the higher SNR the
less noise in the system and the clearer signal. SNR is calculated using Equation
4.1[11].

Psignal
SN R = 10 log
(4.1)
Pnoise
In the process of choosing components for the receiver it must be considered
how much a specic component aects the overall SNR, due to its noise contribution. This means that in order to do an approximate calculation of the systems
SNR for a specic signal level the total receiver noise must be calculated. The
section below shows the equations used for noise calculation. The SNR calulations
for this system are done in Section 6.3.1.
4.2
Receiver Noise
In order to do a calculation of the receiver noise the thermal noise at the antenna
must be calculated by using Equation 4.3[21] is Boltzmanns constant, T is absolute temperature in kelvins and B is the Nyquist bandwidth, fs /2. Usually in
receiver noise calculations T is chosen to be 290K and gives 10log kT = -174 dBm.
dBm is a representation of a power level in dB relative to 1 mW. This representation gives a clue of how much stronger the measured signal is in comparison with
1 mW.
Nth
Nth (dBm)
=
=
kT B
10 log kT + 10 log B =
(4.2)
174dBm + 10 log B
(4.3)
15
16
After the calculation of the thermal noise the noise and gain contribution of all
parts in the receiver are added, as shown in Equations 4.4 - 4.5. Nin is the total
noise power of the receiver before the A/D-conversion.
Fi
Nin
Ni1 + Ni
Ni
=1+
Ni1
Ni1
Ni
= Fi 1
Ni1
= G1 G2 kTB + G1 G2 [F1 - 1]kTB + G2 [F2 - 1]kTB =
F2 1
= G1 G2 [F1 +
]kTB =
G1
= Gsys Fsys kTB[W]
=
(4.4)
(4.5)
Equation 4.5 represents the noise in a system containing two gain and/or noise
contributing devices. Fi is the noise factor of the i:th device after the antenna
and Gi is the gain factor of ditto. As shown in Equation 4.5, the noise factor of
a device is divided by the gain factor of all previous devices. This means that
devices that are placed far from the antenna contributes less to the overall noise
than the ones closer to the antenna.
Notice that all noise and gain factors for the cascaded parts are linear values
not logarithmic. Usually in the devices data sheets the noise is represented as
noise gure (NF). NF is the common logarithm of the noise factor.
4.3
Intermodulation Distortion & Intercept Point
Intermodulation distortion (IMD) occurs when two or more dierent input frequencies exist in a device, resulting in production of undesired output signals
(intermodulation products) at other frequencies. This is a problem in all ampliers and mixers but also in passive components. In this project only ampliers
and passives are taken into account because of the absence of mixers. These intermodulation products (IMD products) are produced at the sum and dierence
of integer multiples of the existing frequencies. Equation 4.6 expresses the output
frequency components when two dierent input frequencies exist in the device,
which results in two-tone intermodulation distortion.
IM D = m f 1 n f 2
(4.6)
The sum of the integers m and n in Equation 4.6 denes the order of the IMD
product. Most of these products are either too weak to be detected or too far away
to interfere with the desired frequencies. Generally in RF systems, and in the case
of this project, the third-order products (IMD3: 2f1 + f2 , 2f1 f2 , 2f2 f1 ,
2f2 + f1 ) are of great concern, since the probability of them falling inband and
interfere with the desired frequency is high[21]. Intermodulation rejection raito
is the ratio between the desired signal and the highest IMD3 product. It is an
4.3 Intermodulation Distortion & Intercept Point
17
imortant parameter which describes the receivers ability to handle strong IMD
products.
Commonly IMD3 products are specied in terms of third-order intercept point
(IP3 ). This is a measure of the devices tolerance against interfering signals outside
the desired passband. In Figure 4.1[7] the output power is plotted versus the input
power, both in logarithmic scale. It is shown that both the output signal and the
IMD3 product increase linearly with increased input signal. For every 1-dB of
signal increase the IMD3 product amplitude increases 3 dB because of increased
distortion in the device. At a certain level of input signal strength the wanted
signal and the IMD3 product will be equal. This point is called the IP3 which
usually is referenced to either the input or the output of the device. IIP3 is the
input power at the IP3 and OIP3 is the output power at the IP3 . The relationship
between the two is OIP3 = IIP3 + system gain.
Figure 4.1. Denition of Intercept Points and 1-dB Compression Points for Ampliers
Also seen in Figure 4.1 is the 1-dB compression point which shows the input
signal level at which the receiver begins to get a non-linear amplitude response.
This means that the device is linear up to a certain input signal level after which
the output becomes saturerad and stop increasing with increased input signal.
Both IP3 and 1-dB compression point are important parameters in the choice of
ampliers and most often one or both these values are given in the devices data
sheet.
The power of an intermodulation product is calculated using Equation 4.7[5].
PIMout is the power of the IMD product at the output of the device and Pout is
the signal power at the output.
PIMout = 3 Pout 2 OIP3
(4.7)
18
This equation will be used in Section 6.3.2 to calculate a theoretical value of

the total PIM generated in the chosen system conguration.
4.4
Dynamic Range
Dynamic Range (DR) is the ratio between the maximum and the minimum signal
that a receiver is designed to handle simultaneously. This measure is used for
describing the limits of receivers. DR is of great concern in SDR solutions because
of the wide frequency band of interest where signal levels can dier signicantly.
4.5
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) measures the ratio between the root-meansquare (rms) level of the desired signal and the rms level of the highest spur in the
spectrum. It is an important parameter in cases where harmonic distortion and
spurious signals are undesirable. One example of these cases is analog-to-digital
converters (ADCs) in which noise and harmonics limit the dynamic range.
4.6
Eective Number of Bits
The ADC resolution is dened as the number of bits at its output, i.e. the size
of the binary word which represents the sampled analog signal. An alternative
denition is the size of the least signicant bit (LSB), Equation 4.10. It should be
noted that it is not a measure of the conversion quality. There are dierent error
sources in an ADC degrading its performance. When all sources are included, the
resolution is usually lower than the specied number of bits of the converter[11].
That is why the eective number of bits (ENOB) of an ADC is such an important
parameter and represents the noise-free bits. ENOB is a measure of the ADCs
accuracy at a specic input frequency. It is calculated using Equation 4.9[11]. As
seen in the equation the value of SNDR is needed for the calculation of ENOB.
SNDR is signal-to-noise-and-distortion ratio and is dened similarly as SNR except
it also includes distortion. See Equation 4.8[11]
4.7
SN DR
EN OB
Psignal
Pnoise + Pdistortion
SN DR 1, 76
6.02
10 log
(4.8)
(4.9)
Oversampling in Analog-to-Digital
Converters
As mentioned earlier in Section 3.3, in order to reconstruct a signal from its digital
samples it must be sampled at a frequency that is greater than twice the bandwidth
4.7 Oversampling in Analog-to-Digital

Converters
19
i.e. Nyquists criterion. If fs /2 is higher than the Nyquist frequency the ADC is
considered to be oversampled. By oversampling the ADC(s) the overall SNR is
increased. The reason of this is explained below.
Quantization noise is introduced in the ADC when the continuous analog signal
is quantized to discrete values[11]. This quantization noise is a xed power and is
independent of the input signal, as shown in eq 4.11[21] This noise is spread out
over the Nyquist bandwidth, which is dc up to fs /2. If the ADC is oversampled
the noise is spread out over a wider range of frequencies. So the wider fs the lower
noise oor, i.e. higer SNR. This improvement of the SNR is called oversampling
gain or process gain, see Equation 4.12.
Vlsb
Pqn
process gain =
Vpp
2N
Vlsb 2
12R

fs /2
10 log
BW
(4.10)
(4.11)
(4.12)
20
Chapter 5
Requirements
Several requirements regarding the receivers performance are set up for this
project. These requirements will be presented in this chapter. Also some basic RF receiver concepts will be explained in order to make the understanding of
the requirements easier.
5.1
Bandwidth
The bandwidth (BW) of the receiver in this project is desired to be between 112174 MHz. This wide BW of 62 MHz sets major requirements on the analog lters
in the receiver. The lter requirements and problems caused by the wide BW are
explained in Section 6.2.3.
5.2
Sensitivity
Receiver sensitivity is the lowest signal level that is detectable by the receiver.
The requirements regarding sensitivity in this project is that the receiver must be
able to decode a modulated message at 162 MHz with a signal level of -107 dBm.
A packet error rate (PER) of 20% is allowed. The modulation type of the signal
is discussed in Chapter 7.
The highest detectable signal is required to be -7 dBm. The number of uncorrectly received messages at this level should not dier by more than 10 from
those received at -77 dBm. These boundary values of the signal level give a span
of 100 dB. It should be kept under consideration that all the components used
in the analog front-end must have proper performance at all levels of the 100 dB
interval.
21
22
5.3
Requirements
Intermodulation Response Rejection and

Blocking
Intermodulation response rejection is the receivers ability to supress IMD products

caused by two or more undesired signals. The frequencies of these signals have a
specic relationship to the desired signal frequency. A blocker on the other hand
is a strong out-of-band interferer that sets requirement on the receivers DR. The
blocker signal sets limitation on the maximum allowed receiver gain.
In this project the receiver must be able to decode messages with 20% PER at
a level of -101 dBm in presence of two IMD products at -27 dBm and a blocker
signal at -15 dBm. One of the IMD products is adjusted 500 kHz below or above
the wanted frequency and the other is adjusted 1000 kHz below or above it. The
blocker signal is adjusted 5MHz below the wanted frequency. The input desired
signal is adjusted to the same frequency as the previous test. This test is considered
to simulate the worst case scenario.
5.4
Adjacent Channel Selectivity
The adjacent channel selectivity is the receivers ability to receive desired signals in
presence of an undesired interfering signal at the frequency of the channel directly
above that of the desired signal. The requirment on the adjacent channel selectivity
of the receiver is that it shall not be less than 70 dB.
5.5
Signal-to-Noise Ratio
As mentioned in Section 5.3 the receiver must be able to operate despite the
existence of a blocker signal and two IMD products. In this worst case scenario
it is possible that the mentioned signals interfere with each other, hence their
amplitudes will be added together, creating an amplitude even higher than the
amplitude of the blocker signal alone. This amplitude is calculated by using the
equations below.
A =
P =
Atot
Ptot,dBm
DR =

50 103 10PdBm /10 , conversion of dBm to V
A2
R
Asig + Ablocker + AIMD1 + AIMD2

A2tot
10 log
R 103
Ptot,dBm Psignal
(5.1)
(5.2)
(5.3)
(5.4)
(5.5)
The resistor value R in Equation 5.2 is 50 and is the antennas load resistance.
In this case the signal caused by the mentioned interference is at a level of -11.5
dBm. The dierence between this level and the desired signal level at -101 dB
5.5 Signal-to-Noise Ratio
23
gives a DR of 89.5 dB. The decoder that is used for decoding the received messages
requires an SNR of 12 dB. This means that the receiver need an overall SNR of at
least 89.5 + 12 = 101.5 dBFS to be able to decode a received message. dBFS is a
representaion of the ratio between a signal and the full-scale signal of a system.
For the sensitivity test the required SNR is dierent from above due to the
receiver gain which is decided by the gain in the ampliers and possibly the lters.
Thus the SNR of this test will be presented after the components has been chosen,
see Chapter 6.
24
Requirements
Chapter 6
Analog Front-End
This chapter covers the chosen architecture of the analog front-end and motivates
the choice of components for both PCB versions. Also both PCB designs are
presented together with the measures taken to prevent EMC problems.
6.1
Front-End Architecture
As mentioned earlier the main goal of this project is to build an RF receiver for the
required frequency band containing as few analog parts as possible. This achievement is possible due to the concept of SDR together with SP Devices technology.
As was mentioned in Section 3.3 this technology makes it possible to build a so
called direct sampling receiver witout using mixer circuits and local oscillators for
frequency down-conversion. Despite this fact the ADCs can not be directly attached to the antenna due to a couple of reasons. One reason is that without some
attenuating bandpass lters strong undesired signals could saturate the ADCs.
Another reason is that without amplication the weakest signals would never get
strong enough to get sampled properly by the ADC. The closer a signal is to the
ADCs input voltage range the more bits of the ADC are used. Figure 6.1 shows
the chosen architecture for the analog front-end.
DAC
ADC1
BPF1
LNA
BPF2
AGC
ADC2
F
P
G
A
Figure 6.1. The architecture of the analog front-end.
The rst bandpass lter (BPF1) is intended to attenuate undesired out-of-band

frequencies. The signal is then dierentiated passing through a 1:1 transformer.
25
26
Analog Front-End
The reason for dierentiating the signal path is to reduce the sensitivity of disturbance in the transmission lines. This is further explained in Section 6.4.
After the rst lter the signal is amplied in a low noise amplier (LNA), which
is the most crucial part of this design due to the noise and IMD requirements
depending on it, see Section 6.2.2. The second bandpass lter (BPF2) is meant
to lter out the wanted signal further before its amplitude is adjusted by the
variable gain amplier (VGA). The VGA is controlled to either amplify the signal
or attenuate it, depending on the signal level. This is called automatic gain control
(AGC) and is intended to push the signal amplitude as close as possible to the
ADC:s input voltage range.
The last stage of the front-end is the A/D-conversion. Here the two interleaved
ADCs digitalize the received signal and feeds it through to a eld-programmable
gate array (FPGA) where the data is processed. The data processing in the FPGA
is explained in Chapter 8.
This front-end architecture is used on both PCB:s. The only dierence is that
in the rst case the FPGA is o-board and is placed on a development board. On
the second PCB the FPGA is placed on-board.
6.2
Choise of Components
In this section the chosen components are presented together with the motivation
of why they were chosen. Choosing and nding the right components for the analog
front-end is very challenging. The choice of the dierent parts of the receiver must
be done in parallel, because the properties of all parts depend on each other. In
this project the ADC is chosen to be the starting point.
The components used in the front-end alone do not dier between the two
boards. The major dierence is that the FPGA is mounted on-board in the second
attempt while in the rst case an external development board handled the signal
processing.
6.2.1
ADC
The analog-to-digital conversion is usually the part that limits the performance
of the receiver. The most important parameters in choosing this component are
resolution, sampling frequency, SNR and SFDR.
SNR and fs
Some calculations were done on the some of the ADC parameters, mentioned in
Chapter 4, at dierent sampling frequencies, see Equations 6.1 - 6.3. As it is
shown, the channel bandwidth is chosen to be 25 kHz which is usually the case in
the VHF band[14]. The results of the calculations can be seen in table 6.1.
The ADC resolution is dened as the number of bits at its output, i.e. the size
of the binary word which represents the sampled analog signal. An alternative
denition is the size of the least signicant bit (LSB), Equation 4.10. It should be
noted that it is not a measure of the conversion quality. There are dierent error
6.2 Choise of Components
27
sources in an ADC degrading its performance. When all sources are included, the
resolution is usually lower than the specied number of bits of the converter[11].
That is why the eective number of bits (ENOB) of an ADC is such an important
parameter and represents the noise-free bits.
Some calculations were done on the mentioned ADC parameters at dierent
sampling frequencies, see Equations 6.1 - 6.3. As it is shown, the channel bandwidth is chosen to be 25 kHz which is usually the case in the VHF band[14]. The
results of the calculations can be seen in table 6.1.
SNRreq
BWch
SNRideal
=
=
=
101.5dB
25kHz
SNRreq 10 log
fs
340
380
420
460
500
fs /2
BWc h
(6.1)
(6.2)
(6.3)
SNR
63.2105
62.7274
62.2928
61.8977
61.5356
Table 6.1. SNR requirement at dierent sampling frequencies.
The table above shows that the required values of SNR lessens with increasing
fs , which is a good reason to choose a high fs . Besides, considering the advantages
of oversampling that were mentioned in Section 4.7, choosing fs high would help
relaxing the requirements on the analog lters and improve the overall SNR.
The chosen architecture includes two interleaved ADC:s, as mentioned earlier.
After spending relatively short time searching among the leading manufaturers,
it was noted that the 14-bit ADC called ADS5546 from Texas Instruments was
best suited for this applicaion. The maximum fs is 190 MHz which means a total
fs of 380 MHz after interleaving. The ideal SNR of this converter is 72.2 dB
which is almost 10 dB higher than the required SNR for this fs , also shown in
the same table. Some calculations are done in Section 6.3 to show that this ADC,
theoretically, fullls the system requirements mentioned in the previous chapter.
6.2.2
LNA and VGA
When choosing ampliers for this project the most important parameters are the
NF and the OIP3 . Due to the inecient analog ltering in this project it is preferable to have as linear components as possible to avoid intermodulation products
in the system. Because of this the OIP3 and the 1-dB compression point of the
ampliers must be as high as possible.
28
Analog Front-End
As mentioned in Section 4.2 it is extra important that the components nearest

to the antenna have low NF because the noise contribution aects the overall noise
more in the early stages of the receiver chain. So it is of great importance that
the LNA has low NF. As it was shown in Equation 4.5, it is also preferable to
have high gain in the LNA or the other parts in the begining of the receiver chain.
This makes the noise contribution of the following parts less important due to
the division with the gain factor of the previous parts. Because of the dierential
signaling used in the design, the LNA should have dierential input and output.
Finding an LNA with the mentioned characteristics is hard. After evaluating
the data sheet of many LNA:s it was decided to use the ADL5330 from Analog
Devices. This amplier is a VGA which gain can be xed by attaching the control
pin to a x voltage. The level of the xed gain depends on the voltage level on
the control pin. The amplier has an acceptable NF and a high OIP3 . Some
properties of the circuit are presented in Table 6.2.
The same amplier circuit is used for the AGC in this project. As it is presented
in Table 6.2 the gain can be adjusted between -34-22 dB. The control signal range
is between 0-1.4V which means that if the control signal is 0V the gain of the VGA
is -34 dB, and if the control signal is 1.4 V the gain is 22 dB.
Calculations in Section 6.3 shows that this amplier fullls the requirements
theoretically.
Gain
NF
OIP3
1dB Compression point
-34 - 22 dB
7.8 dB
38 dBm
22 dBm
Table 6.2. Properties for the VGA.
6.2.3
Analog Filters
BPF1 and BPF2 in Figure 6.1 are two analog BP-lters that are intended to
select out the desired band and attenuate the neighbouring undesired bands. The
frequency range of interest in this project is required to be 112-174 MHz, which
belongs to the VHF-band. This means that the lters should have a passband of
62 MHz with a center frequency of 143 MHz. This passband should not attenuate
the test signal at 162 MHz mentined in the test sections. The absence of mixer
circuits, i.e. frequency down-conversion, in the receiver makes it very hard to nd
highly selective lters with such wide passband at such high frequencies with low
insertion loss. Insertion loss in a lter is the ratio between the input power and
the output power. It is a measure of the power loss in the device. In other words
the passband attenuation in the lter.
However, a lter type commonly used in RF applications is surface acoustic
wave lter (SAW). Their main properties are that they can be designed physically
small providing good out-of-band rejection, broad pass-band and steep transition
edges. With these lter characteristics the SAW lter appears to be the right
29
choice for this application. But after spending hours and hours searching among
manufacturers standard products, it was noted that nding a suitable SAW lter is an impossible task due to their extremely high insertion loss. The chosen
architecture can not aord this high level of insertion loss, hence with even zero
insertion loss in the lters it still is a challenge achieving the required sensitivity of
-107 dBm. Some manufaturers have the possibility of building customized lters
but for a cost that is over budget in this thesis project.
After considering the facts and the given options it was decided to build the
lters as passive bandpass lters with discrete components. A lter with the
mentioned characteristics require high lter order. The higher the lter order
the more discrete components are required. So a decision was made to loosen the
requirements to be able to build low-order lters with a few components. It should
be noted that with more time and higher budget the lters could be built much
better, but for now passive low-order lters will do.
The rst bandpass lter is a second order LC-lter with only one inductor
and one capacitor, see Figure 6.2. The second lter is a fourth order LC-lter, as
shown in Figure 6.3. An advantage of the implemented lters are that they have
no insertion loss.
Zi=50 Ohm
Ro=50 Ohm
Figure 6.2. BPF1 - 1st order bandpass lter.
L2
C2
L1
Zi=50 Ohm
C1
Ro=50 Ohm
Figure 6.3. BPF2 - 2nd order bandpass lter.
As it is shown in the gures above both analog lters have 50 impedance on

both input and output. This depends on the output and input impedances of the
components attached before and after the lters. In order to get the impedances
matched it is necessary to choose the component values so that the resonance
frequency of the lter circuits is equal to the desired signal frequency. Impedance
matching between components is very important in order to avoid reections in
30
Analog Front-End
the signal path. The resonance frequncy is easily calculated in both these cases,
see equations 6.4[16].
Zi = Ro +
1
+ jL
jC
(6.4)
The impedance is matched if Zi = Ro . In order to make this happen the

1
+ jL = 0. This leads to equation
component values must be chosen so that jC
6.6 which is used for calculating the resonance frequency of the lter, which in this
case means the least ltered frequency.
The chosen component values, see table 6.3 give an overall bandwidth of about
60 MHz with a center frequency around 160 MHz, which suits this project hence
the required test signal is situated at 162 MHz. A frequency analysis was done in
Protel on the two lters, which frequency responce can be seen in Figure 6.4.
0.000 dB
-2.500 dB
Amplitude [dB]
-5.00 dB
-7.50 dB
-10.00 dB
-12.50 dB
-15.00 dB
75.00MHz
100.0MHz
125.0MHz
150.0MHz
175.0MHz
200.0MHz
225.0MHz
250.0MHz
275.0MHz
300.0MHz
Frequency [MHz]
Figure 6.4. BPF1 - 1st order bandpass lter.
1
=
LC
1
f=
2 LC
(6.5)
(6.6)

Filter
BPF1
BPF2
31
Component
C
L
C1
L1
C2
L2
Value
100pF
10nH
100pF
10nH
100pF
10nH
Table 6.3. Component values for the analog bandpass lters.
6.2.4
FPGA
As shown in Figure 6.1 the digitalized signal from the ADC:s is fed through to an
FPGA where the data is processed. The rst PCB does not include the FPGA.
Instead the front-end PCB is attached to a development board which includes a
Virtex 4 FPGA from Xilinx. On the second board the front-end and the FPGA
are placed on the same PCB. This time the Virtex 5 from Xilinx was used. These
FPGAs can be programmed in two ways. One way is to directly program it via a
JTAG-connection from the PC. This way the program is erased when the power
is switched o and the FPGA must be reprogrammed at power on. The second
way is to use the ash memory placed on-board. By programming the ash the
FPGA can reprogram itself everytime the power is switched on.
After the FPGA the processed data is sent to a PC where the data is decoded. For transmitting and receiving data to and from the PC a UART-interface
was implemented in the FPGA. In the PC however the USB port was chosen as
communication link. This means that a USB-to-UART converter is needed. The
converter used is presented in the next section.
6.2.5
USB-to-UART Interface
For converting the FPGA:s UART-signals to the PC:s USB-signals and vice versa
a converter from FTDI called FT232R was used. In the case of the rst PCB this
converter is built-in in a cable that is used for the communication between the
development board and a PC. In the second case the converter is built-in in a chip
which is placed directly on the PCB between the FPGA and a type B USB-port.
According to the data sheet of FT232R it can handle up to 3 Mbits/s.
6.2.6
DAC
As mentioned above the chosen VGA has an analog control signal input. So the
digital control signals from the FPGA must be converted to an analog signal with
a digital-to-analog converter (DAC), as shown in gure 6.1. For this task a DAC
called AD7302 from Analog Devices was chosen. It has a parallel 8-bit input and
an output voltage range of 5V, which means that the output changes by steps of
5/28 0.0195 V. This step size gives the VGA 1.4/0.0195 72 dierent gain
32
Analog Front-End
settings. So only 7 bits of the DAC are needed, thus 26 = 64 is too few and
28 = 256 is too much.
6.2.7
Crystal Oscillator and Clock Buer
The ADCs need to have a clock signal that determines the sampling frequency.
As mentioned in the ADC section the decided sampling frequency in this project
is 380 MHz. This means that the interleaved ADCs have an fs of 190 MHz each.
On the rst board the clock signal is provided from an external signal generator.
The generator provides a 380 MHz signal which gets divided into two 190 MHz
clock signals by a clock buer called CDCP1803 from Texas Instruments. The
divided clock signal is then distributed to the ADC:s.
On the second board the signal is generated from a crystal oscillator which
provides a 380 MHz signal. The oscillator is a Si530 from SiLab. In the same way
as the rst board the signal from the oscillator is divided into two 190 MHz signals
in a clock buer.
6.2.8
Linear Voltage Regulators
There are two dierent supply levels used on the rst board and four dierent
levels on the second. The rst board contains 3.3V digital, 3.3V analog and 5V
analog supply. The second board contains 1V digital, 2.5V digital, 3.3V digital,
3.3V analog and 5V analog supply.
The reason of why the digital and the analog supplys are split up will be
explaind in Section 6.4. For the supply management some linear voltage regulators
from Texas Instruments and Maxim are used. See Table 6.4 for the rst board
and Table 6.5 for the second. The TPS786xx is from Texas Instruments and has
a maximum output current of 1.5A and the MAX8869 has a maximum output
current of 1A. As it can be seen in the Tables 6.4 and 6.5 the amount of current
that needs to be supplied is kept under the maximum limit on all regulators.
Regulator
TPS78601
(Analog, 5V)
TPS78633
(Analog, 3.3V)
TPS78633
(Digital, 3.3V)
Sum(tot.)
Component
DAC
VGA
Sum
ADC
Sum
ADC
Clk buer
Sum
Quantity
1
2
2
2
1
Supply Current(mA)
5
215
435
300
600
51
140
242
1277
Table 6.4. Current consumption of the rst PCB
Regulator
TPS78601
(Analog, 5V)
TPS78633
(Analog, 3.3V)
TPS78633
(Digital, 3.3V)
TPS78625
(Digital, 2.5V)
MAX8869
(Digital, 1V)
Sum(tot.)
Component
DAC
VGA
Sum
ADC
Sum
ADC
FPGA(I/O)
Crystal Osc.
Clk buer
Flash
FTDI
Linear reg.(1A)
Sum
AFPGA(Aux)
FPGA(I/O)
Sum
FPGA(Core)
Sum
33
Quantity
1
2
2
2
1
1
1
1
1
1
1
1
1
Supply Current(mA)
5
215
435
300
600
51
10
100
140
20
100
0.5
473
73
325
398
500
500
2406
Table 6.5. Current consumption of the second PCB
34
6.3
Analog Front-End
Theoretical Calculations
In this section some theoretical calculations are done to show that the chosen components fulll the SNR and the third-order intermodulation requirements, hence
these are the main requirements in this project.
6.3.1
SNR
In this section the two most crucial cases are studied, i.e. the sensitivity test and
the intermodulation/blocking test.
Calculating the overall SNR of the receiver in dBFS can be done as follows:
Vnoisetotal
SNRtot

VnoiseADC 2 + Vnoisein 2

VF SADC
= 20 log
+ Process Gain
Vnoisetotal
=
(6.7)
(6.8)
Vnoisetotal [21]is the total noise voltage of the system including the noise voltage
at the ADC input and the noise voltage contributed by the ADC itself. the noise
VF SADC in the equation above is the rms value of the full-scale (FS) signal of the
ADC, which is derived by using Equation 6.9. The noise in the ADC is independent
of the input signal and will be the same value in both tests. The rms value of the
ADCs noise voltage is calculated as shown below[6]:
VF SADC
VnoiseADC 2
=
=
2
1
VppADC
= = V
2 2
2 2
2

2
SNRADC
20
VF SADC 10

2
72.2
2
10 20
3.013 108 V2
2 2
(6.9)
This value is used in the secitons below for calculating the overall noise in the
receiver in both test environments.
Intermodulation and Blocking
As mentioned in the requirements, the receiver must be able to operate despite
interference with unwanted signals. In section 5.5 it was explained that the level
caused by the interference can get as high as -11.5 dBm. This level limits the
maximum allowed amplication in the receiver. The ADCs have a specied input
voltage range which sets the limit of the maximum allowed signal level. If the
amplied signal passes this limit the ADC will be saturated. The chosen ADC has
an input voltage range of 2V which gives a full-scale signal at 10 dBm. This gives a
maximum allowed gain of 10 (11.5) = 21.5 dB for this test. By using equation
4.5 together with the given maximum gain and the given amplier NFs, the rms
value of the total noise voltage at the ADCs input can be calculated. The total
6.3 Theoretical Calculations
35
NF of the system includes only the specied noise contribution of the ampliers.
Other, unspecied, noise sources are hard to estimate. The SNR calculations are
done as follows:
Nin,dBm
= 10 log Nin =
= 174 + 10 log(190MHz) + 20 log(10
7.8
20
7.8
10 20 1
= 61.4898dBm
Vnoisein
10
21.5
20
) + 21.5 =
= 1061.4898/10 10-3 50 = 3.548 108 V2

(6.10)
The calculations above give the total noise voltage for the system.
Vnoisetotal =

3.013 108 + 3.548 108 2.5614 104 V
Now the overall full-scale SNR of the system can be calculated using Equation
6.8:

SNRtot = 20 log
0.7071
2.5614 104

+ 10 log
190MHz
25kHz

= 107.6282dBFS
This means that with the chosen components an SNR of 107.6 dBFS can be
achieved theoretically, which is more than 6 dB greater than the required SNR
of 101.5 dBFS in this test. Theoretically it would be possible to also fulll the
sensitivity requirement with the same amplication thus the required SNR would
be 107.5 dBFS. This would mean that the VGA is not needed. But in reality this
will not be the case thus the noise contribution of the analog lters and other noise
sources are not included in this calculation. The 0.1dB margin is not enough to
fulll the requirement when all noise sources are included.
Sensitivity
In this test there are no other signals present but a weak signal of -107 dBm, thus
maximum possible gain can be used. Theoretically, the full-scale SNR needs to
be 10dBm - (-107dBm + 44dB) + 12dB = 85dBFS. This is the ratio between the
ADCs full-scale signal and the amplied test signal plus the 12dB required by
the decoder. Here follows the SNR calculations that are done similairly as the
calculations above:
36
Analog Front-End
Nin,dBm
= 174 + 10 log(190MHz) + 20 log(10
7.8
20
= 39.0129dBm
Vnoisein
Vnoisetotal
SNRtot
7.8
10 20 1
22
10 20
) + 44 =
= 1039.0129/10 10-3 50 = 6.2759 106 V2

=
3.013 108 + 6.2759 107 0.0025V

0.7071
190MHz
= 20 log
+ 10 log
= 87.8003dBFS
0.0025
25kHz
Also in this test the SNR requirement is fullled. The achieved SNR of 87.8
dBFS is more than 2dB higher than the required 85 dBFS. Theoretically this
margin is more than enough, but in reality the actual SNR could dier from the
calculated SNR due to non-included noise sources. SNR measurements are done
on both PCBs in Chapter 10.
6.3.2
IMD3
As mentioned in Section 4.3, third-order intermodulation distortion can cause

major problems in the receiver if they fall inband in the desired signal bandwidth.
In this section som theoretical calculations are done to conrm that the chosen
components, in the chosen conguration, fulll the requirements that are set up to
avoid this kind of problem. This is a theoretical measure of the so called two-tone
test that is commonly used for estimating the non-linearity of systems. The value
of parameters that are needed for this calculation are presented in Figure 6.5. As
it is shown, the rst amplier must be adjusted to 21.5 dB and the second to 0
dB hence the maximum allowed gain in the IMD/blocking test is 21.5 dB, as was
mentioned earlier.
Pin: -24 dBm
Plna: -2.5 dBm
LNA
Glna: 21.5 dB
OIP3lna: 38 dBm
BPF2
Gfilt: 0 dB
Pagc: -2.5 dBm
AGC
Gagc: 0 dB
OIP3agc: 38 dBm
Figure 6.5. The conguration for IMD measurements.
As it is shown in the gure, the test signal has a level of -24 dBm which is the
average power of the two IMD tones of -27 dBm each. Together with the given
values, the calculations are done by using Equation 4.7:
6.4 PCB and EMC[13]
PIMLN A
= 3 Plna 2 OIP3LN A = 3 (2.5) 2 38 = 83.5dBm
PIMAGC
= 3 Plna 2 OIP3AGC = 3 (2.5) 2 38 = 83.5dBm
37
Since the VGA is adjusted to 0 dB gain, the calculated IMD3 powers will
remain the same at the input of the ADC. By using these results, a total IMD3
power can be calculated:
PIMtot = 10 log(108.35 + 108.35 ) = 80.5dBm
The calculations result in a total IMD3 power of -80.5 dBm at the ADC input.
In the mentioned IMD/blocker test, the desired signal has a level of -101dBm,
which after amplication of 21.5 dB is brought up to -79.5 dBm. This value is
only 1 dB higher than the level of the IMD3 . This could cause problems if the
IMD product falls inband. The decoding of the signal could be prevented hence
the decoder requires a 12 dB SNR/SFDR.
Despite the result of the calculations above, it is decided to use the chosen
components anyway, hence nding ampliers with higher OIP3 than 38 dBm with
high gain is time consuming. With the tight time schedule of this work this could
not be done.
6.4
PCB and EMC[13]
In order to design a PCB there are many factors to keep in mind. In this work
some actions were taken to avoid performance degradation due to, for example,
EMC problems. A short list covers some of these actions:
The analog and the digital supplies are split up to avoid transfering the noisy
digital supply into the analog region.
The clock signal paths to the ADCs have the same length to minimize clock
skew.
The impedance in components are matched to avoid reections in the signal
path.
Many decoupling capacitors were used in order to prevent unwanted energy
transfer between high frequency devices and the power distribution network.
The rst PCB has four layers including two interconnected ground layers. The
second PCB has six layers to make it easier to route the FPGAs BGA-package
(Ball Grid Array). Also this board has two interconnected ground layers.
Ground layers are important in order to keep the noise generated from ground
at a minimum. They create a good path for returning currents and make it
convinient to route ground pins of devices anywhere on the board, using vias.
It would have been preferable to have two separate ground layers, using one
for the digital parts and the other for the analog parts. This is hard to achieve in
reality hence this was not attempted in this project.
38
Analog Front-End
Chapter 7
Data Packets
To be able to measure the performance of the system, data packets are transmitted
to the receiver. To be able to decode the packet, the packets appearance have
to be known. The packet and how they are processed before transmission will be
described in this chapter. The modulation of the test packet according to GMSK
follows the block schematic depicted in Figure 7.1.
Data
Modulated
signal
Calc.
CRC
Bit
stuffing
Add
Preamble
Modulate
carrier
Gaussian
filter
NRZI
Figure 7.1. Block schematic for the modulation.
7.1
The Packet
The data is transmitted in a packet, which may contain dierent amount of data.
The components that build up the packet and their lengths are shown in Table
7.1 and in Figure 7.2. They will be described in the following sections.
The packet shown in gure 7.2 is transmitted from left to right.
Trainingsequence
Startbyte
FCS
Data
Figure 7.2. A packets dierent components.
39
Stopbyte
40
Data Packets
Name
Training Sequence
Start pattern
Data
FCS
Stop pattern
No. of bits
24
8
168-1008
16
8
Table 7.1. Packet components and their sizes.
7.1.1
Training Sequence
The training sequence can be used by the receiver to synchronize itself to the
transmitter. It consists of a 24-bit long alternating 0 and 1 bit pattern. When the
packet is coded with NRZI encoding it changes its pattern as shown in Figure 7.3.
The NRZI encoding is explained in Section 7.3.
Figure 7.3. The training sequence before and after NRZI encoding.
7.1.2
Start Flag
The start ag consists of a standard high level data link control (HDLC) start ag,
which is an eight bit pattern, 01111110 (7Eh)[2]. The start ag is not bit stued
(see Section 7.2) even though it consists of six consecutive ones.
7.1.3
Data
The data part of the packet is of variable length, but the default length of the test
packages are 168 bits. The data is bit stued together with the FCS before it is
broadcast, this is explained in Section 7.2.
7.2 Bit Stung
7.1.4
41
Frame Check Sequence
The frame check sequence (FCS) is created by a cyclic redundancy check (CRC).
The CRC is preformed by a 16-bit polynomial that calculates a checksum as dened in ISO/IEC 3309:1993. The CRC bits are set to one at the beginning of a
calculation. The FCS is only used to verify the correctness of the data portion of
the packet, consequently the packet has no built in error correction.
End Flag
The end ag is identical to the start ag as described in Section 7.1.2 above.
7.2
Bit Stung
The start and the stop pattern has six consecutive ones, and since the receiver
does not know how long the message will be it can only determine this by the
start and stop pattern. In order for the packet to only contain one stop pattern
the message has to be bit stued to prevent the stop pattern to occur in the data
and FCS. This is done by inserting a zero after every group of ve consecutive
ones that occur, even if the sixth bit is not a one, this is illustrated in Figure 7.4.
Original message:
Bit stued message:
1 0 0 1 1 1 1 1 1 0 1 0 1 1 1 1 1 0 1 1 ...
1 0 0 1 1 1 1 1 0 1 0 1 0 1 1 1 1 1 0 0 1 1 ...
Figure 7.4. An example bit stream which has been bit stued.
It is only the data and the FCS that are subject to the bit stung. After the
bit stung the message is NRZI encoded.
7.3
NRZI
Before the message is broadcast the bit stream is encoded by the Non Return to
Zero Inverted (NRZI) algorithm[20]. NRZI encoding is done by starting with a 1
and every time there is a 0 in the bit stream the resulting bit stream changes sign.
An example can be seen in Figure 7.5.
1
1
0
-1
0
1
1
1
0
-1
1
-1
0
1
0
-1
1
-1
1
-1
Figure 7.5. An example bit stream encoded with NRZI
42
7.4
Data Packets
GMSK
The packet is then modulated with Gaussian Minimum Shift Keying (GMSK)[20]
before it modulates the carrier wave. GMSK is a phase modulation method that
has continuous phase in order to lessen its bandwidth.
7.4.1
Gaussian lter
The signal is passed through a Gaussian low pass lter to eliminate the discontinuities in the NRZI endoded bit stream. The gaussian low pass lter is dened by
Equations 7.1-7.3.
g(t) =
0
Q(t) =

t T /2
t + T /2
1
Q 2Bb
Q 2Bb
2T
ln 2
ln 2
Bb T
2
1
e(x /2) dx
2
(7.1)
(7.2)
(7.3)
The lter is truncated and scaled to represent a /2 phase change for a single
symbol. This is done by choosing K to fulll equation 7.4
T
Kg(t)dt =
T
(7.4)
Chapter 8
FPGA
This chapter will explain the digital signal processing executed by the FPGA.
There are two dierent versions of the code which will be explained in the following
sections. Both attempts were run on the rst hardware platform, but with slight
alterations to t the dierent FPGA:s used. Only the second attempt was run on
the second hardware platform.
The FPGA has a very important role in lessen the amount of data that needs
to be processed by the PC. To do this the FPGA performs several tasks:
Merge the signals from the two ADCs
Filter and decimate the signal
Produce I and Q signals
Detect the angle between two consecutive symbols
Transfer the data to a PC for decoding
Control the VGA
Since the system has a very high sampling rate it is crucial that it is decimated
before transferring. The sampling is done at 380 Msps producing 14 bits at each
sample, that is a bit rate of about 5.3 Gbps. The data link to the PC on the other
hand can only handle a maximum bit-rate of 3 Mbps, which gives a decimation
factor of at least 1770. How this is done will be explained in the following sections,
which starts with the rst attempt and will be followed by the second attempt.
8.1
Hardware Prerequisites
The two dierent hardware platforms use dierent FPGA:s as explained in Chapter
6. The Xilinx FPGA:s Virtex 4 (v4) and Virtex 5 (v5) has somewhat dierent
architectures. Most of these design dierences are handled by the synthesis tool
and does not need any alterations of the code, but one major dierence is the
DSP-slices.
43
44
8.1.1
FPGA
DSP-slices
The DSP-slice is a hardware accelerator that can do multiplications, additions and

subtractions at very high speed, up to 550 MHz[19]. They are very useful in the
FIR lters used in this project. The high required speed in the rst decimation
lters makes it dicult to create a multiplier with only logic, without using many
steps of pipelining. Therefore the DSP-slices have been used to accomplish these
high speed FIR lters, but they dier a bit between the v4 and the v5.
Xilinx Virtex 4
The v4 DSP-slice has a 18 x 18 bits multiplier with a 48 bit long accumulator,
which can be seen in Figure 8.1. The rst attempt therefore had 18 bits in the
signal path. The word lengths will be discussed in Section 8.4.2.
DSP48
A
18 bits
x
+
18 bits
Truncated
output
48 bits
48 bits
Figure 8.1. DSP48-slice in virtex 4.
Xilinx Virtex 5
The v5 has an improved DSP-slice called DSP48E. It has a 25 x 18 bits multiplier
instead and a 48 bit long accumulator, depicted in Figure 8.2. It can also run
faster than its predecessor, up to 550 MHz. This means that the quantization
error will not become as big, since the signal can have 25 bits in the signal bus.
8.2
First Attempt
This is the rst attempt in decoding the encoded message. The overall block
schematic can be seen below in gure 8.3. Each block will be described in detail
in the following sections.
8.2.1
Linearizer
This block corrects the errors produced by the dierences in the two ADCs. Its
function is described in chapter 2.
8.2 First Attempt
45
DSP48E
25 bits
x
+
Truncated
output
18 bits
48 bits
48 bits
Figure 8.2. DSP48E-slice in virtex 5.
cos
DDS
ADC 1
ADC 2
L
i
n
e
a
r
i
z
e
r
h2
h3
Phasediff
h1
x
h2
FIFO
Serialinterface
h3
sin
DDS
Figure 8.3. System overview for the rst attempt.
PC
46
8.2.2
FPGA
First Decimation
This stage decimates the signal with a factor 8, from 380 MHz to 47.5 MHz. The
anti-aliasing lter is made by a 161 tap FIR lter, which is run on 22 parallel
DSP-slices. Half of the DSP-slices work on one of the ADCs and the other half on
the other ADC.
The lters frequency response can be seen in Figure 8.4. It was dicult to
achieve a good lter with narrow passband and high stop band attenuation due
to its high cost in hardware. This was one of the reasons causing the decision to
make a second attempt, which is explained in Section 8.3. The implemented lter
has a stop band attenuation of 41 dB and a passband of 3 MHz.
0
5
10
15
dB
20
25
30
35
40
45
50
20
40
60
80
100
MHz
120
140
160
180
Figure 8.4. The frequency response for the rst decimation lter.
8.2.3
I - Q Modulation
To be able to detect the I and Q the signal is multiplied by a sine and a cosine
signal of the same frequency as the carrier. By doing this the modulated signal is
moved down to DC, where it can be demodulated.
The multiplications are done by two DSP-slices that multiply the input with the
sine value and the cosine value respectively. This is now implemented in parallel,
but if there is a restriction on hardware it could be done on only one DSP-slice in
series instead, since a new output is only produced every other clock cycle.
The sine and cosine waves were implemented as two Direct Digital Synthesis
(DDS) blocks[3]. These are built up by 512 values of the waveform that are stored
in a memory that are stepped through by a phase accumulator. The 16-bit phase
accumulator counts with a step length that corresponds to a wave with the wanted
frequency. Only the 9 most signicant bits (msb) of the phase accumulator are
used to access the right value in the memory. This way of producing a sine and
cosine waveform is not perfect and therefore will add noise to the signal. This
solution turned out to add too much noise which is shown in Equation 8.1. In
the second attempt a more advanced DDS was used, which is explained in Section
8.2 First Attempt
47
8.3.2
SNR = 10 log(
8.2.4
Ps
) = 50.3dB
Pn
(8.1)
Second Decimation
The second decimation lter decimates the signal with 15, from 47.5 MHz to 3.17
MHz. The FIR lter has 60 taps and its impulse response can be seen in Figure
8.5. It uses one DSP-slice for the I channel and one for the Q channel. The shift
register for the FIR lter is implemented as a ring buer in a RAM-block on the
FPGA. The values are added to the buer by one port as the other port reads the
values to the DSP-slice.
0.035
0.03
0.025
0.02
0.015
0.01
0.005
10
20
30
40
50
60
Figure 8.5. Impulse response for the second decimation lter.
8.2.5
Third Decimation
The third decimation lter decimates the signal with 33, from 3.17 MHz to 96 kHz.
The FIR lter has 496 taps and its impulse response can be seen in Figure 8.6. It
also uses a ring buer to store the values while a ROM contains the coecients.
One DSP-slice on the FPGA is used to perform one multiplication on every clock
cycle and then accumulating the result until all the taps have been calculated.
This takes 496 clock cycles, but a new output is performed every 1980 clock cycle,
so it is paused for almost 1500 clock cycles. If the control logic is altered it would
be possible to run the I and Q channel in series and thus save one DSP-slice, but
this was not necessary in this implementation.
48
FPGA
0.025
0.02
0.015
0.01
0.005
0.005
50
100
150
200
250
300
350
400
450
500
Figure 8.6. Impulse response for the third decimation lter.
8.2.6
Phase Dierentiator
To be able to demodulate the signal one needs to nd the angular dierence

between two following symbols. This was implemented by doing a cross product
as described in Equation 8.2.

z1 z2 =
a
b
c
d

= ad bc = |z1 | |z2 | sin(arg(z1 ) arg(z2 ))
(8.2)
By using this equation the sign of the angular dierence can be found, the
actual value is of less importance since it depends on the length of the vectors.
The angle between two following symbols can be either /2 or +/2, as explained
in Section 7.4. Thus by checking the sign of Equation 8.2, the signal becomes the
original NRZI encoded message because of the fact of Equations 8.3 and 8.4. This
is the last step of the decoding done in the FPGA.
sin(/2) =
sin(/2) =
8.2.7
(8.3)
(8.4)
FIFO
To ensure that no data would be lost between transfers to the PC a fo was

implemented to collect the data. With this design the transfers could be made
in bursts to the PC, and the decoding algorithm run on the PC can be made on
batches of data.
8.3 Second attempt
8.2.8
49
Data Transfer
A serial interface is used on the FPGA to be able to communicate with the PC,
while the PC has a USB interface. To convert the serial interface to the USB
interface a chip from FTDI was used. The serial/USB link gives a theoretical
limit of 3 Mbits/s, but would probably be more like 1 Mbit/s in reality. Since
decimation is used and only the sign of the angular dierence is transfered the
transfer rate will be 96 kbits/s, which means that the PC will have enough time
to process the data between collecting batches of data.
8.2.9
DAC Controller
The second amplier used in the analog receiver is a VGA, which amplication
level is controlled by an analog input. To adjust the level of amplication 7 dipswitches on the developmentbord is used to control a DAC, while the DAC controls
the VGA. The signals from the dip-switches are routed via the FPGA to the DAC.
A problem is that the DAC also needs a write signal to take in a new value.
This write signal is produced by the FPGA that continuosly sends out the write
pulse.
The initial plan was to make a digital AGC, that would automatically adjust
to the incoming signal level. It was decided not to do so since such a function was
not needed for the tests.
8.3
Second attempt
Upon completion of the rst attempt there were a few points that called for a
second attempt. The most important reason was the decimation lters. The rst
lter in the rst attempt was dicult to make with sharp transition bands and
with the attenuation in the stop band that was needed for a good sensitivity. The
block schematic for the second attempt can be seen in Figure 8.7. One advantage
that can be seen instantly is that noise from the DDS blocks will be ltered further.
Each block will be described one by one in the following sections.
8.3.1
Linearizer
This block is the same as described in Section 8.2.1.
8.3.2
IQ-modulation
The IQ-modulation block has the same functionality as in the rst attempt, but
since the IQ-modulation block is the rst block in the decoding chain it will have
to run at 380 MHz. Because the FPGA is clocked at 190 MHz the 2 multiplications
are performed by 4 dsp-slices that work in parallel.
50
FPGA
DDS
sin(2n) sin(2n+1)
ADC 1
ADC 2
L
i
n
e
a
r
i
z
e
r
x
h1
h2-h8
x
Phasediff
x
h1
FIFO
Serialinterface
PC
h2-h8
cos(2n) cos(2n+1)
DDS
Figure 8.7. System overview for the second attempt.
DDS
The DDS blocks in the rst attempt generated to much noise and were improved in
this attempt. In the previous version the least signicant bits (lsb) were discarded,
but in this version they are used to enhance the output.
= mem(address(msb))
(8.5)
y
dif f
= mem(address(msb) + 1)
= yx
(8.6)
(8.7)
corr
sin
= dif f address(lsb)
= x + corr
(8.8)
(8.9)
As described by Equations 8.5-8.9, the msb fetches the addressed value and
the next value from the ram, that contains only 256 values now. The lsb are then
multiplied with the dierence between the two fetched values and then added to
the rst. This achieves a linear approximation between the two points on the
wave, thus reduces the error and the noise generated by the DDS. The dierence
can be seen in Figure 8.8.
The new DDS has a signicant improvement in performance which aects the
system as a whole. The SNR Equations 8.10 and 8.11 shows how much better the
new DDS is.
SNRDDS1
= 50.3dB
(8.10)
SNRDDS2
= 91.1dB
(8.11)
8.3 Second attempt
51
x 10
3.2
3.1
2.9
2.8
2.7
1.2
1.4
1.6
1.8
2.2
4
x 10
Figure 8.8. The dierence between the two DDS blocks.
8.3.3
Decimation
Now the signal is moved down to DC, which means that the decimation lters can
all be lowpass lters. This is a great improvement since a good low pass lter chain
requires less hardware to design, than the band pass lter used in the rst attempt.
Another improvement is that the noise from the sine and cosine generator will be
ltered through more lters.
The decimation factor was also changed in this attempt so that the resulting
signal will have a sampling frequency of 105.6 kHz instead of 96 kHz. The dierent
steps to make the decimation from 380 MHz down to 105.6 kHz was divided into
factors of 2, 5, 5, 3, 3, 2, 2. This will give an output of 11 bits per symbol.
The frequency response for the whole decimation is shown in Figure 8.9, and
in Figure 8.10 the passband is zoomed in.
First Decimation
The rst decimation lter gets two inputs every clock cycle and decimates it by a
factor two, which means it produces a new output every clock cycle. The 7 tap
FIR lter is realized with two DSP-slices. Its impulse response can be seen in
Figure 8.11.
Second Decimation
The second lter has 21 taps and is realized with 5 DSP-slices to be able to produce
an output every 5th clock cycle. Its impulse response is depicted in Figure 8.12.
52
FPGA
0
100
200
dB
300
400
500
600
700
800
20
40
60
80
100
MHz
120
140
160
180
Figure 8.9. The frequency response for the complete decimation lter.
20
dB
40
60
80
100
120
140
20
40
60
80
100
kHz
Figure 8.10. A zoomed in portion of the frequency response in Figure 8.9.
8.3 Second attempt
53
0.6
0.5
0.4
0.3
0.2
0.1
0. 1
Figure 8.11. Impulse response for the rst decimation lter.
0.15
0.1
0.05
10
15
20
Figure 8.12. Impulse response for the lter h2
54
FPGA
Third Decimation
The impulse response of the third lter can be seen in Figure 8.13, which also
shows that it has 25 taps. This stage decimates the signal with a factor of 5,
which means that it gives a new output every 25th clock cycle. It consists of one
DSP-slice that accumulates the result, which is then truncated.
0.2
0.15
0.1
0.05
10
15
20
25
Figure 8.13. Impulse response for the lter h3.
Fourth Decimation
With 21 taps and one DSP-slice the fourth lter decimates the signal with a factor
of 3. Its impulse response is seen in Figure 8.14.
0.3
0.25
0.2
0.15
0.1
0.05
0
0.05
10
15
20
Figure 8.14. Impulse response for the lter h4
8.3 Second attempt
55
Fifth Decimation
The fth lter has 19 taps and decimates the signal with a factor 3. After this
step the data speed is about 844 ksps.
0.3
0.25
0.2
0.15
0.1
0.05
0
0.05
0
10
15
20
Sixth Decimation
The sixth decimation lter has 19 taps and it decimates the signal with a factor
2.
0.3
0.25
0.2
0.15
0.1
0.05
0
0.05
0
10
15
20
56
FPGA
Seventh Decimation
The seventh lter has 29 taps and decimates the signal with a factor 2.
0.5
0.4
0.3
0.2
0.1
0. 1
0
10
15
20
25
30
Eighth Decimation
This decimation lter is the last one and it decimates the signal with a factor 2.
Since the speed is very low at this point, this lter has the most taps. It has 257
taps, but it will only need one DSP-slice since the data speed after this step is
only 105.6 ksps, which gives the lter 1800 clockcycles to complete one output. It
is this lter that decides the channel bandwith, which is 25 kHz.
0.25
0.2
0.15
0.1
0.05
0.05
0
50
100
150
200
250
8.4 Calculations
8.3.4
57
Phase Dierentiator
The phase dierentiator is almost identical to the one described in Section 8.2.6,
except the alteration for coping with 11 bits per symbol which is a result of the
changed decimation factors.
8.3.5
FIFO
This function is still the same as in Section 8.2.7.
8.3.6
Serial Interface
The serial interface also has the same functionality as the previous version described in Section 8.2.8.
8.3.7
DAC Controller
The DAC controller is almost identidak to the one described in section 8.2.9, except
that the second board only has 5 available dip-switches. Because of this two zeros
were added to the end to produce a seven bit wide controll signal. The write signal
is still produced as a repeated pulse.
8.4
8.4.1
Calculations
Scaling
When using twos complement representation it is very important not to get overow in the calculations. The FIR lters are sensitive blocks where overow can
easily occur if they are not scaled properly. There are several ways of scaling a
lter. The L2 -norm[9] (see equation 8.12) was used in this case.

1

jT
2
||X||2 =
|X(e
)| dT =
|x(n)|2
(8.12)
2
n=
When scaling a multistage decimator the following algorithm can be used[12]:

1. F1 (z) H1 (z)
2. c1
1
||F1 ||2
3. F2 (z) F1 (z)H2 (z M1 )
4. for i 2 to 8
5.
Calculate ||Fi ||2
6.
ci
i1
j=1(1/ci )
||Fi ||2
58
FPGA
7.
if i = 8
8.
then
9.
10.
stop
else
i
11.
Mi
12.
Fi+1 (z) Fi (z)Hi+1 (z Mi )
+1j=1 Mj
Table 8.1 shows the result from the algorithm above. The third column shows
the chosen scaling factor, which was used in the algorithm on row 5 instead of the
calculated ci . For the rst lter safe scaling was used instead, since it has few taps
and therefore could overow more easily. As can be seen in the table there should
be no overow problems in the decimation lters.
Filter
h1
h2
h3
h4
h5
h6
h7
h8
L2 -norm Scale
1.56
9.02
8.33
13.78
23.37
31.90
44.15
85.59
Chosen Scale
0.5
2
1
1
1
1
1
1
Table 8.1. L2 -norm scaling of the decimation lters.
8.4.2
Word Length
It is important that the signal keeps or improves its SNR through out the processing in the FPGA, hence the importance of the word lengths in the system. The
DSP-slices contains a large accumulator but smaller input ports to the multipliers,
which implies that the results from each lter must be truncated. When a result
is truncated quantization noise is added. How the SNR of the quantization noise
can be calculated can be seen in Equation 8.13 - 8.16[9].
y(n) =
Ps
Ps
Pn
SNR =
2N 1 Q sin(nT )
(2N 1 Q)2
= 22N 3 Q2
2
22N 3 Q2
3
= 22N
Q2
2
12

Ps
10 log
= 6.02N + 1.76
Pn
(8.13)
(8.14)
(8.15)
(8.16)
8.4 Calculations
59
The system should not add any more noise than the ADC has already contributed, so that the ADC is the limiting component. To achieve this the number
of bits needs to be calculated, which is done in Equations 8.17 - 8.18.

SNRtot = SNRADC + 10 log
SNR = 6.02N + 1.76
SNRtot = 111.0
fs /2
BWch

N =

= 72.2 + 38.8 = 111.0
(8.17)
111.0 1.76
= 18.15 bits
6.02
(8.18)
The Equations 8.17 - 8.18 assumes that the quantization noise from the lter
depends only on the last truncation. In order to do a more thorough examination
the following algorithm for quantization noise in multistage decimation lters can
be used[12]:
1. G8 (z) 1
2.
82 82
3. for i 7 downto 1
4.
Gi (z) Gi1 (z Mi )ci Hi (z)
5.
i2 i2 ||Gi ||22
8
= i=1
i2
2
6. tot
ci is the scaling factor, which was treated in section 8.4.1.

This algorithm is applied on the decimation lter in the second attempt. The
result, with the scaling used in Section 8.4.1 and with dierent word lengths, can
be seen in Table 8.2.
No. of bits
16
17
18
19
20
21
22
23
24
25
SNR (dB)
95.53
101.55
107.57
113.59
119.62
125.64
131.66
137.68
143.70
149.72
Table 8.2. SNR for dierent word lengths.
60
FPGA
According to the result in Table 8.2 the v4 with only 18 bits in the signal path
adds more noise during the decimation ltering than the ADC, but it is still below
the required SNR mentioned in Section 6.3.1. Thus the v5 version is better, since
it adds signicantly less noise than the rest of the system and can be neglected.
Chapter 9
PC
To be able to measure the performance of the prototype, some signal processing is
needed. All processing was made on the PC at rst and then one block at a time
was moved to the FPGA, though all blocks were not moved. The tasks that are
performed by the PC at the nal version of the decoding are:
Communicate with FPGA
Symbol Synchronizing
NRZI-decoding
Decode Packets
Verify the Data
9.1
Communication
The PC communicates via USB with the FPGA. As mentioned earlier in Section
8.2.8 it uses a chip from FTDI to convert the serial interface to the USB. A program
was written in C to collect the data on the USB port and pass it on to Matlab for
further processing.
9.2
Matlab
Matlab was used to do the remaining demodulation and decoding of the packets.
This made it possible to take advantage of Matlabs good mathematical functions.
Some statistical tests were also performed, which can be found in chapter 10.
9.2.1
Symbol Syncronization
When a batch of data is received it is rst put through a correlation lter. The
data stream consists of ten or eleven samples per symbol depending on FPGA
61
62
PC
version, which leads to the problem of nding the symbol boundary. By observing
the result from the correlation lter it is possible to nd out if there is a message
and where the correct symbol boundaries are. This is possible since the preamble
of the message is known, which was explained in Chapter 7. The correlation lter,
depicted in Figure 9.1, has the same form as a perfect packet preamble would have
from right to left, but the coecents are weighted after how close to the boundrary
they are.
0.8
0.6
0.4
0.2
0. 2
0. 4
0. 6
0. 8
50
100
150
200
250
300
350
Figure 9.1. The impulse response for the correlation lter.
When the bit stream corresponds to the preamble the correlation is high, but
when there is only noise the correlation is low. This is depicted in Figure 9.2 which
is a plot from the correlation lter. It is easy to see when there is a message in
the bit stream. Figure 9.3 displays a zoomed in part of the peak in Figure 9.2.
The maximum value of the peak indicates the beginning of a message. When
the starting point is found the message can be conceived. This was implemented
in two ways. The rst implemented version was to choose only the center sample,
and in the second version the surrounding samples were taken into consideration
by dierent weight. The output from this stage is either one or negative one.
9.2.2
Decode NRZI
The message has to be decoded before the data is extracted since the message
was encoded with NRZI before transmission. The NRZI encoding is explained
in Section 7.3. The decoding is done by checking the sign of the bits in the bit
stream. If there is a change in sign the output is a zero otherwise a one. An
example is shown in Figure 9.4. The sign of the bit stream is of no importance,
since it will result in the same output. This is a necessity since the sign depends
on what phase the sine and cosine waves in the IQ-demodulation had when the
packet was received.
9.2 Matlab
63
Correlation
350
300
250
200
150
100
50
6
4
x 10
Figure 9.2. An example output from the correlation lter.
Correlation
300
250
200
150
100
50
1.071
1.0715
1.072
1.0725
1.073
1.0735
Sample
1.074
1.0745
1.075
1.0755
1.076
5
x 10
Figure 9.3. Zoomed in on the detected message.
64
PC
Bit stream 1
Bit stream 2
Output
-1
1
-1
1
1
1
-1
0
-1
1
0
-1
1
1
1
-1
0
1
-1
1
-1
1
0
1
-1
0
1
-1
1
1
-1
1
Figure 9.4. An example bit stream decoded from NRZI.
9.2.3
Extraction of the Data
Now the message consists of zeros and ones and the data can be extracted from
the package. By nding the start ag and the stop ag the data is extracted. This
was done with the find(bitstream==pattern) function in Matlab, which returns
the indexes of the positions where the patterns were found.
Now that the data has been extracted it is possible to see what the data
contains and compare it with the same as the transmitted data.
Chapter 10
Tests and Results

In this chapter the test environments will be described and the test results will be
presented. Some tests had to be somewhat modied due to the lab material, e.g.
there were only two signal generators available. It will be explained how the test
was performed in each section.
10.1
Filter Bandwidths
The expected lter bandwidths were presented in Chapter 6, but are they the
same in reality? A frequency sweep was made on both boards to establish the
frequency characteristics of the bandpass lters in the front-end.
10.1.1
Board 1
As can be seen in Figure 10.1, the passband center frequency is shifted to the
left compared to the simulations. This could depend on property variations in
the passive components. This is dicult to aect other than using better quality
components or testing their value before mounting. The lter components were
replaced after the board was delivered, since some components had inaccurate
values.
The lter passband of the rst lter is 137-157 MHz, which is not what was
strived for. 162 MHz, which is the frequency of the test signal, is attenuated with
about 5 dB, which is more than aimed for. The lter has a good attenuation of
frequencies in the FM-band, e.g. it attenuates 100 MHz with 28 dB. This is good
since FM-transmitters usually have high output power.
10.1.2
Board 2
The frequency response for the front-end on board 2 is worse than for board
1, which can be seen in Figure 10.2. This could depend on the fact that the
components on board 1 was replaced with the right components. Some component
values on the second board could be wrong, but they have not been examined as
65
66
Tests and Results
20
dB
40
60
80
100
120
0.2
0.4
0.6
0.8
1
Hz
1.2
1.4
1.6
1.8
2
8
x 10
Figure 10.1. Frequency response for board 1.
the lter functioned properly in the lab. Much better lters would have to be
designed for use in the real world. The passband of the lter is 112-147 MHz,
while 162 MHz is attenuated with 9 dB. If the components were replaced it could
be expected to have about the same characteristics as for board 1.
0
10
20
30
dB
40
50
60
70
80
90
100
0.2
0.4
0.6
0.8
1
Hz
1.2
1.4
1.6
1.8
2
8
x 10
Figure 10.2. Frequency response for board 2.
10.2
External LNA
As it turned out during the time in the lab, non of the boards passed the sensitivity
test, although the theoretical calculations in Section 6.3 showed that they should.
It was decided to use an external ultra-low-noise amplier to see if the problem
lies within the LNA used on the boards.
Table 10.1 shows some characteristics of this external amplier. As it is shown
in the table, the noise gure of this amplifer is very low which suits the purpose
of these tests perfectly.
10.3 SNR
67
The test results with and without the external LNA are presented later in this
chapter.
Gain
NF
OIP3
1dB Compression point
17 dB
< 1.2 dB
>37 dBm
> 20 dBm
Table 10.1. Properties for the external LNA.
10.3
SNR
The SNR for the system is very important, since a good decoder needs the modulated signal to have a 12 dB SNR for correct decoding. In this section some tests
are done to measure the SNR performance of the front-end alone by studying
the sampled data directly after the ADC. The setup for these tests is depicted in
Figure 10.3.
Signalgenerator
-70 dBm
SDRprototype
Matlab
Signalgenerator
-70 dBm
External
LNA
SDRprototype
Matlab
Figure 10.3. Setup for SNR test, without and with external LNA.
10.3.1
Variable Gain - Fixed Signal Level
As explained in Chapter 6, the SNR depends on the gain of the ampliers. Some
tests were run to conrm that the best SNR was achieved while having maximum
receiver gain. This test was done by varying the gain of the VGA while receiving
an unmodulated sine wave at a constant level.
The SNR was calculated using Matlab by cutting out the points in the fast
fourier transform (FFT) that corresponded to the signals frequency, in order to
get the signal power. The noise power was calculated in a similar way, by taking
many surrounding points of the signal in the FFT and calculate the average to get
an approximation of the noise power in the channel.
Tables 10.2 and 10.3 show the test results of both boards with and without
the external LNA. The SNR is given for a -70 dBm input signal at a frequency
of 162 MHz with a channel width of 25 kHz. The same input signal is used on
68
Tests and Results
both boards. The second column presents the results using the external LNA,
mentioned in Section 10.2.
Without the external LNA the performance of the rst board turned out to
be slightly better than for the second. The dierence was bigger than expected.
This could depend on the fact that the second board contains more components,
e.g. FPGA which emits a lot of noise into the ground plane. The dierences in
the analog lters could also be a part of the reson, but the attenuation dierence
was only 4 dB and thus does not explain the whole dierence.
Gain (dB)
0
6
12
18
22
SNR (dB)
38.8
40.8
41.9
42.1
42.8
SNR
LNA
(dB)
46.9
49.1
51.0
51.3
51.6
Table 10.2. SNR for a -70dBm signal without and with external LNA on board 1.
As it is shown in the tables, the SNR value for both systems are relatively
equal when using the external LNA. This result was expected since the signal is
amplied with the same low noise amplier stage before it enters the dierent
boards. The dierence in added noise of the two boards becomes less noticeable
when the external LNA is used because of the changed noise gure, see Equation
4.5.
Gain (dB)
0
6
12
18
22
SNR (dB)
27.5
30.5
31.7
32.5
32.4
SNR
LNA
(dB)
46.7
49.7
50.6
51.1
51.0
Table 10.3. SNR for a -70dBm signal without and with external LNA on board 2.
10.3.2
Fixed Gain - Variable Signal Level
An SNR test with the gain xed at a maximum was also conducted. The input
signal level was adjusted to see at what level the input signal had a lower SNR
than that of 12 dB required by the decoder. The result of this test is shown in
Table 10.4 for board 1 and Table 10.5 for board 2. The test is also done with and
without the external LNA. In both cases the results turned out to be as expected.
Using the LNA, the test results are similar. Without it, the rst board has better
SNR performance. This depends on the same reason as in the previous test, that
it is the slightly more noisy signal path on the second board caused by the FPGA.
10.4 Sensitivity Test

Gain (dB)
-70
-75
-80
-85
-90
-95
-100
-105
-110
-115
69
SNR (dB)
42.8
37.9
31.9
27.6
23.2
17.6
13.0
9.2
6.3
4.7
SNR
LNA
(dB)
51.3
46.9
41.3
36.2
31.4
25.8
20.8
16.7
12.3
8.8
Table 10.4. SNR for various signal levels without and with external LNA on board 1.
The results in Table 10.4, show that it should be possible to decode a -100 dBm
without th external LNA, and -110 dBm with. This agrees well with the result in
the sensitivity tests in the following section.
Signal power
-70
-75
-80
-85
-90
-95
-100
-105
-110
-115
SNR (dB)
32.06
26.82
21.61
16.86
12.93
9.34
6.97
6.89
5.74
5.65
SNR
LNA
(dB)
51.0
46.1
41.2
36.0
31.1
25.6
20.7
16.7
12.7
9.7
Table 10.5. SNR for various signal levels without and with external LNA on board 2.
The result for the second board in Table 10.5 also agrees with the sensitivity
tests. With the external LNA a -110 dBm signal should be possible to decode,
and without a -90 dBm signal.
10.4
Sensitivity Test
The sensitivity test is performed to nd the lowest signal power at which the
system is able to correctly decode a message. The requirement says that it must
be able to decode at least 80% of the packts correct, or with 20% packet error rate
(PER). The packets described in Chapter 7 with 168 data bits were used to test
the system. The signal generator was modulated by a sound le that was played
70
Tests and Results
by a computer. The Matlab program then fetched 100 batches of data that each
contained at least one packet. The packet was decoded and veried against the
known data that had been sent. After 100 messages the result was printed out on
the screen.
The PER values in the following sections are not statistically veried, since it
is based on only 100 packets. Only 100 packets were used because of the tests
were time consuming. The small amount of data can make it seem like the values
are unstable. It is still possible to see were the PER value passes 20%, since the
breaking point is very sharp.
10.4.1
Board 1
The setup for the sensitivity test of board 1 is shown in Figure 10.4. The test
was performed with a coaxial cable connecting the signal generator and the board,
thus the noise added there is negligible.
Clockgenerator
Signalgenerator
SDR-receiver
PC
Figure 10.4. The setup for the sensitivity test for board 1.
When testing the sensitivity for board 1 only the second code version will be
used. This is because only this version can be run on both boards and thus be
used for comparison and evaluation. The test gave the results in Table 10.6.
Level
-85
-88
-90
-92
-94
-95
-96
PER (%)
8
5
2
5
8
15
22
Table 10.6. Sensitivity test using PCB 1.
The system seemed to generate a lot of noise. As depicted in Figure 10.5, the
external LNA, that has a much better noise gure, was attached before the board
and improved the results signicantly. Table 10.7 shows the results from this test.
10.4 Sensitivity Test
71
Clockgenerator
Signalgenerator
External
LNA
SDR-receiver
PC
Figure 10.5. The setup for the sensitivity test for board 1 with LNA.
Level
-95
-97
-99
-101
-103
-105
-107
-109
-110
-111
-112
PER (%)
3
5
6
2
3
8
3
3
12
21
41
Table 10.7. Sensitivity test using PCB 1 with external LNA.
72
Tests and Results
10.4.2
Board 2
The sensitivity test for the second card was performed in the same way as for the
rst board, except for the fact that the second board has an on board clock. The
setup for this test can be seen in Figure 10.6.
Signalgenerator
SDR-receiver
PC
Figure 10.6. The setup for the sensitivity test for board 2.
The test results were not as good as expected by the theoretical calculations.
Level
-85
-90
-91
-92
-93
PER (%)
1
7
9
12
34
Table 10.8. Sensitivity test using PCB 2.
Also for the second board the results became a lot better when the external
LNA was used, which can be seen in Table 10.9.
Signalgenerator
External
LNA
SDR-receiver
PC
Figure 10.7. The setup for the sensitivity test for board 2 with LNA.
10.5
Blocking Test
The blocking test is performed to see how the system handles a strong signal on a
dierent frequency than the wanted signal. This test is a good for measuring the
systems dynamic range. It is an important parameter for an SDR receiver, since
there will almost always be a strong signal somewhere within the frequency band
of interest.
In this work the blocker will determine the maximum gain the system can have,
which means that the wanted signal will not be fully amplied. The setup for the
test is shown in Figure 10.8. The blocker signal power should be -15 dBm and
should have a frequency of 5 MHz above or below the wanted signal.
10.5 Blocking Test
73
Level
-107
-109
-111
-112
-113
PER (%)
1
5
17
27
60
Table 10.9. Sensitivity test using PCB 2 with external LNA.
Signalgenerator
External
LNA
SDR-receiver
PC
Blockergenerator
Figure 10.8. The setup for the blocking test.
The amplication of the LNA on the board has to be adjusted since the external
LNA is used in front of the board. This was done by applying a variable voltage
to the LNA. The gain was adjusted to make the combined signal full swing on the
input of the ADCs.
The critical component in this case will be the ADC, because if the wanted
signal is detectable after the ADCs it could be ltered out. For this the gain must
be enough for the wanted signal to have sucient SNR, as discussed in Section
6.3.1.
To perform this test we needed a second signal source. The only signal generator that was available turned out not to have good enough parameters to perform
the test. The SFDR was too low and the noise it generated was higher than the
wanted signal, which made it impossible to detect. The test that was performed
with the blocker switched on showed that the modulated signal had to have a
power of -72 dBm to be correctly decoded.
A modied test was performed instead to make an estimation of the blocker
case. The systems amplication level was determined in order to make the blocker
signal have full swing. Then the blocker was turned o and the test with the
modulated signal was carried out.
The modied test suggests that it should be possible to decode signals with a
power as low as -97 dBm as long as the blocking signal does not add more noise
than the system itself adds. The result could probably be improved if a better
decoder was used. The requirement was -101 dBm, so the result is 4 dB below.
74
10.6
Tests and Results
Intermodulation Test
The intermodulation test checks the linearity of the analog part of the receiver.
The requirement for the intermodulation is a part of the blocking requirement, but
due to lack of equipment these tests had to be split up in two. There were only
two signal generators available for the tests, thus the test is performed to measure
the power of the IMD3 product.
0
10
20
dBFS
30
40
50
60
70
80
90
1.6
1.605
1.61
1.615
1.62
MHz
1.625
8
x 10
Figure 10.9. Plot from the IMD3 test on board 2.
The test was performed by applying two -27 dBm signals to board 2. This was
only run on the second board since they have the same components. The signals
were 500 kHz apart, thus the IMD3 product appeared 500 kHz on either side of
the signals. This can be seen at 160.5 and 162 MHz in Figure 10.9. The dashed
line is the plot with a 2 dB gain on the VGA, and the solid line is with 1 dB
attenuation on the VGA.
Gain (dB)
-1
2
6
9
IMD3 (dBFS)
-70
-67
-62
-59
Table 10.10. IMD test performed on board 2.
The result was dicult to interpret, due to the noise generated by the signal
generators. According to the Equation 10.1 the IMD3 product should increase
with the increase in gain. It can be seen in Table 10.10 that this was also the case
in our tests.
10.7 Adjacent Channel Selectivity
I3 = 3Po 2OIP3 = 3(Pi + G) 2(IIP3 + G) = 3Pi 2IIP3 + G

IM RR = I3 Po = 67
75
(10.1)
(10.2)
The resulting IMD3 product gives an intermodulation rejection ratio of 67 dBc

for the system, calculated with Equation 10.2. This result is not good enough
since a value of least 86 dBc is needed for the signal to have a 12 dB margin.
10.7
Adjacent Channel Selectivity
The digital lter implemented in the rst version of the FPGA code attenuates
the adjacent channel with 77 dB, which might not be enough. According to the
requirement the receiver should handle an adjacent signal 70 dB stronger than the
signal. The decoder might be able to still decode the messages, but some extra
safety margin would be good.
The second version of the lter attenuates the adjacent channel with 100 dB.
That will be more than enough to fullll the requirements set for the adjacent
channel selectivity.
It is really the ADCs SNR that will be the limiting factor for this requirement,
since it is possible to alter the digital lters so that an even higher attenuation is
achieved.
10.8
Power Consumption
The second PCB turned out to become very hot during the tests. The reason
for this was that the total power consumption on the board was relatively high.
As can be seen in Equation 10.3, the PCB produces a signicant amount of heat.
The used current value for the second PCB are calculated in Section 6.2.8. The
heat problem was solved by using a fan during the tests, which was enough to cool
down the board. If designing a new PCB this fact should be taken into account.
Ptot = Vin Itot = 5 2.4 = 12W
(10.3)
76
Tests and Results
Chapter 11
Conclusions and Future

Work
This chapter will nish the report with the conclusions on the work and some ideas
for future work.
11.1
Conclusions
This thesis work has shown that it is possible to create a direct sampling SDR
receiver for the VHF-band. The requirements that were set up are dicult to
achieve in an ordinary receiver design, but it becomes an even bigger challenge with
an SDR design without sharp analog lters and down-conversion of the frequency.
It has been shown that it should be possible to meet all the requirements, even
though they were not fully met within this work.
11.1.1
Test Results
The main test results of the project are presented in Table 11.1. The blocker result
is just a performance estimate, which is explained in Section 10.5.
Requirement
SNRsensitivity without LNA
SNRsensitivity with LNA
SNRblocker without LNA
SNRblocker with LNA
Sensitivity test
Blocker test
Third-Order Intermodulation
Required
85 dBFS
68 dBFS
101.5 dBFS
107.5 dBFS
-107 dBm
-101 dBm
86 dBc
Table 11.1. Results from the tests
77
Mesured
75 dBFS
91 dBFS
85 dBFS
105 dBFS
-111 dBm
-98 dBm
67 dBc
78
Conclusions and Future Work
11.1.2
Hardware
The second version of the PCB proved to have problems with heat. It was known
that the components used on the PCB generated a lot of heat, but it turned out
to be a bigger problem than predicted. If a cooling fan was applied to the FPGA
the heat was manageable, but without the fan the PCB was overheated after a few
minutes. The number of components, especially the FPGA, on the second board
increased the amount of noise in the signal path compared to the noise on the rst
board. This caused a slight deterioration of the SNR on the second board.
The chosen LNA turned out to be the wrong choise for this application. Although the theoretical calculations showed the opposite, non of the boards managed to pass the sensitivity test. Considering this result, an external LNA, with
very low NF and good properties on linearity, was used to conrm that the problem of the sensitivity lies within the LNA. This turned out to be right hence a
sensitivity of -111 dBm was achieved which is 3 dB under the required value.
The analog lters on both boards turned out to have dierent center frequencies
than what was expected after simulations in Protel. This caused attenuation of
the desired test signal on 162 MHz. This could depend on property variations in
the discrete components. By replacing the components with others which value is
measured, this problem could be solved.
Theoretically, also the blocker test should be passed but this was not the case
during testing hence the actual SNR was lower than the calculated value. A major
reason is that the signal generators that were used for these tests are too noisy.
By using more accurate signal generators, this test could very well be passed.
11.1.3
FPGA
The choice of FPGA for the second version of the PCB, turned out to generate too
much heat. Its full capacity was not needed in this project and therefore another
FPGA could have been a better choice, but for future use the PCB has a lot of
potential which is good for a prototype.
The second version of the FPGA code turned out to be much beter than the
rst code.
Better lters
Improved sine generator
Wider word lengths (only v5)
The decimation lters had better characteristics in the second version. This
was due to the fact that the IQ-modulation was the rst block, thus only lowpass
lters were used. It also required less hardware to implement.
The second version of the DDS generated a sine wave with a much better SNR
for a small increase of used logic. There are still optimazation that could be made
to improve it further but it fullls the requirments.
The Virtex 5 makes it possible to have longer word lengths, which gives less
quantization noise.
11.2 Future Work
11.2
79
Future Work
The electronics market is in constant change. This SDR solution is on the limit of
what is possible, but in the near future this will be a commonly used design. This
work could be used as a base for further development of a true SDR receiver.
The GMSK decoder in this work is very simple. It would be interesting to
further enhance the decoder with a more advanced algorithm to see how that
could improve the performance of the system. Another improvement would be
to integrate it on the FPGA, so that the packets would be fully decoded when
transfered. That way a display could be attached and the data could be presented
directly on the display.
The SDR function could be used further by listening to several channels in
parallel. An FM-demodulator could be implemented to listen to FM broadcasts.
80
Conclusions and Future Work
References
[1] Understanding adc noise for small and large signal inputs for receiver applications. http://www.maxim-ic.com/appnotes.cfm/appnote_number/1929.
[2] ANSI. Iso/iec standard 13239:2002. http://webstore.ansi.org/.
[3] Analog Devices.
A technical tutorial on digital signal synthesis.
http://www.ieee.li/pdf/essay_dds.pdf.
[4] Microwave Encyclopedia. Superheterodyne receivers, microwave encyclopedia. http://www.microwaves101.com/encyclopedia/receivers_superhet.cfm.
[5] R. Gharpurey.
Design considerations in wireless receiver front-ends.
http://engr.smu.edu/orgs/ssc/slides/20010130.pdf.
[6] W. Kester. Adc noise gure - an often misunderstood and misinterpreted
specication. www.analog.com/en/content/0,2886,760_1077_91253,00.html.
[7] W. Kester.
Intermodulation distortion considerations
www.analog.com/en/content/0,2886,760_788_91329,00.html.
for
adcs.
[8] H. Foster L. Bening. Principles of Verifiable RTL Design. Kluwer Academic

Publishers, 2 edition, 1991. ISBN 0-7923-7368-5.
[9] H. Johansson L. Wanhammar. Digital Filters. Linkping Univerity, 1997.
[10] M.
Looney.
Advanced
digital
post-processing
http://www.analog.com/library/analogDialogue/archives/3708/post_processing.html.
techniques.
[11] P. Lwenborg. Mixed-signal Processing. Linkping Univerity, 2 edition, 2006.

[12] H. Johansson M. Olsson, P. Lwenborg. Scaling and roundo noise in multistage interpolators and decimators.
[13] M. Montrose. EMC and the PCB. IEEE, 1998. ISBN 0-7803-4703-X.
[14] PTS. Post- och telestyrelsens almnna rd om den svenska frekvensplanen.
www.pts.se/Archive/Documents/SE/frekvensplanen2005_4.PDF.
[15] S. Ramos S. Lucas. Comparison of modern radio receiver architechtures.
Masters thesis, Linkping University, Sweden, 2005.
81
82
References
[16] S. Sderkvist. Kretsteori & Elektronik. 3 edition, 1999.

[17] A. Svrdstrm. Modulation och teleteknik. Studentlitteratur, 1 edition, 1996.
ISBN 0-13-348624-9.
[18] et al T. Padamanabhan. Design Through Verilog HDL. IEEE, 1 edition, 2004.
ISBN 0-471-44148-1.
[19] Xilinx. Xilinx homepage. http://www.xilinx.com.
[20] F. Xiong. Digital Modulation Techniques. Artech House, 1 edition, 2000.
ISBN 0-89006-970-0.
[21] P. Young. Electronic Communication Techniques. Prentice Hall Inc., 3 edition, 1994. ISBN 0-13-348624-9.
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ELECTRONIC PRESS
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83

Design and Implementation of An SDR Receiver For The VHF Band

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Design and Implementation of An SDR Receiver For The VHF Band

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Department of Electrical Engineering

Design and Implementation of an SDR receiver for

Examensarbete utfrt i Elektroniksystem

Department of Electrical Engineering

Linkpings tekniska hgskola

Design and Implementation of an SDR receiver for

Examensarbete utfrt i Elektroniksystem

Linkping, 31 January, 2007

Design och implementation av en SDR-mottagare fr VHF-bandet

Frfattare Emad Athari & Petter Lerenius

3 Superheterodyne vs. SDR

4 Basic RF Receiver Concepts

Eective Number of Bits . . . . . . . . . . . . . . . . . . . . . . . .

10 Tests and Results

11 Conclusions and Future Work

8.2.5 Third Decimation .

Eect of problems that occur when interleaving ADCs. . . . . . . .

Superheterodyne receiver architecture . . . . . . . . . . . . . . . .

Intercept Points/1-dB Compression Points . . . . . . . . . . . . . .

The architecture of the analog front-end. .

Block schematic for the modulation. . . . . . . . . . . .

The impulse response for the correlation lter. . . . . . . . . . . .

An example bit stream decoded from NRZI. . . . . . . . . . . . . .

Frequency response for board 1. . . . . . . . . . . . . . .

Time-interleaved ADC matching requirements at 180 MHz clock

SNR requirement at dierent sampling frequencies.

Packet components and their sizes. . . . . . . . . . . . . . . . . . .

L2 -norm scaling of the decimation lters. . . . . . . . . . . . . . .

Properties for the external LNA. . . . . . . . . . . . . . . . . . . .

11.1 Results from the tests . . . . . . . . . . . . . . . . . . . . . . . . .

Purpose and Method

The purpose of this thesis is to design, implement and analyze a prototype of

Matlab and Simulink

Xilinx ISE is an integrated development environment (IDE) for Xilinx FPGAs. It

Microsoft Visual Studio

C code was written to produce a dynamically linked library (dll) le used by

Microsoft Visual Studio environment. Visual Studio is Microsofts IDE for C,

Resulting digital signal

Desired digital signal

Figure 2.1. Eect of problems that occur when interleaving ADCs.

Problems with Interleaved ADCs

2.1 Problems with Interleaved ADCs

Figure 2.2. Result of a gain error in an ADC.

Figure 2.3. Result of an oset error in an ADC.

Figure 2.4. Result of time-skew in an ADC.

Figure 2.5. The block diagram of the linearizer

2.2 The Solution

just one example made possible by the linearizer.

Superheterodyne vs. SDR

Traditional Superheterodyne RF Receiver

Figure 3.1. Superheterodyne receiver architecture

Superheterodyne vs. SDR

A major advantage of the superheterodyne receiver is that by mixing down

One of the biggest cons of the superheterodyne receiver is the amount of

3.3 Software-Dened Radio Receiver

Software-Dened Radio Receiver

Superheterodyne vs. SDR

Basic RF Receiver Concepts

Basic RF Receiver Concepts

Intermodulation Distortion & Intercept Point

4.3 Intermodulation Distortion & Intercept Point

Basic RF Receiver Concepts