Microprocessor and Interfaces

MicroprocessorandInterfaces
MinimumMode

Minimum Mode Interface

MinimumModeInterface
Whenthe
e t e Minimummodeoperationisselected,
u
ode ope at o s se ected,
the8086providesallcontrolsignalsneeded
to implementthememoryandI/Ointerface
Theminimum mode signal canbe
divided into thefollowingbasicgroups

Address/Databus
/
Status
Control
Interrupt
DMA

Address/Data Bus
Address/DataBus
theselinesservetwofunctions.As anaddressbusis20bits
longandconsistsofsignallinesA0throughA19.A19
representstheMSBandA0LSB.A20bitaddressgivesthe
8086a1Mbytememoryaddressspace.Moreoverithas
an independentI/Oaddressspacewhichis64Kbytesin
i d
d t I/O dd
hi h i 64K b t i
length
The 16 data bus lines D0throughD15areactually
multiplexedwithaddresslinesA0throughA15respectively.
lti l d ith dd
li
A0 th
h A15
ti l
Bymultiplexedwemeanthatthebusworkasanaddress
busduringfirstmachinecycleandasadata busduringnext
machine cycles D15 is the MSB and D0 LSB
machinecycles.D15istheMSBandD0LSB
Whenactingasadatabus,theycarryread/writedatafor
memory,input/outputdataforI/O devices,andinterrupt
type codes from an interruptcontroller
typecodesfroman
interrupt controller

Status signal
Statussignal
ThefourmostsignificantaddresslinesA19through
A16arealsomultiplexedbutinthiscasewithstatus
signalsS6throughS3.Thesestatusbitsareoutputon
thebusatthesametime thatdataaretransferredover
theotherbuslines
Bit S4andS3togetherfroma2bitbinarycodethat
identifies which of the 8086 internal segment registers
identifieswhichofthe8086internalsegmentregisters
areusedtogeneratethephysicaladdressthatwas
outputontheaddressbusduringthecurrentbuscycle
Code S4S3=00identifiesaregisterknownas
S4S3 = 00 identifies a register known as
extra segmentregisterasthesourceofthesegment
address

Status signal
Statussignal
S4

S3

Segment
Register

Extra

Stack

Code

Data

Status line S5reflectsthestatusofanother

internalcharacteristicofthe8086.Itisthe
logiclevel oftheinternalenableflag.Thelast
statusbitS6isalwaysatthelogic0level
y
g

Control Signals
ControlSignals
The
Thecontrolsignalsareprovidedtosupport
control signals are provided to support
the8086memoryI/O interfaces.Theycontrol
functions such as when the bus is to carry a
functionssuchaswhenthebusistocarrya
validaddressinwhichdirectiondataaretobe
transferred over the bus when valid write
transferredoverthebus,whenvalidwrite
dataareonthe busandwhentoputreaddata
on the system bus
onthesystembus

Control Signals
ControlSignals
ALEisa pulseto logic1thatsignalsexternalcircuitrywhen
avalidaddresswordis onthebus.Thisaddressmustbe
latchedinexternalcircuitryonthe1to0edgeofthepulse
atALE
Anothercontrolsignalthatisproducedduringthebuscycle
isBHE_bar bankhighenable.Logic0 onthisusedasa
memoryenablesignalforthemostsignificantbytehalf
off thedatabusD8throughD1.Theselinesalsoservesa
th d t b D8 th
h D1 Th
li
l
secondfunction,whichisastheS7statusline
UsingtheM/IO_bar andDT/R_bar lines,the 8086 signals
whichtypeofbuscycleisin
hi h t
fb
l i i progressandinwhichdirection
d i hi h di ti
dataaretobetransferredoverthebus

Control Signals
ControlSignals
The logic level of M/IO_bar tellsexternal
circuitry whetheramemoryorI/Otransferistaking
placeover thebus.Logic1atthisoutputsignals
a memoryoperationandlogic0anI/Ooperation
y p
g
p
The direction of datatransferoverthebusissignaled
bythelogicleveloutputatDT/R_bar.Whenthisline
is logic1duringthedatatransferpartofabus
logic 1 during the data transfer part of a bus cycle,
cycle,
thebusisin thetransmitmode.Therefore,dataare
eitherwrittenintomemoryoroutputtoanI/Odevice
Onthe
On the otherhand,logic0atDT/R_bar
other hand logic 0 at DT/R bar signalsthatthe
signals that the
busisinthereceivemode.This correspondstoreading
datafrommemoryorinputofdatafromaninputport.

Control Signals
ControlSignals
ThesignalreadRD_bar andwriteWR_bar indicates
thatareadbuscycleorawritebus cycleisinprogress.
The8086switchesWR_bar tologic0to signalexternal
devicethatvalidwriteoroutputdataareonthebus
p
On theother hand,RD_bar indicates that the8086is
performingareadofdataofthe bus.Duringread
operations, one other control signal is also supplied.
operations,oneothercontrolsignalisalsosupplied.
ThisisDEN_bar (data enable) andit signalsexternal
deviceswhentheyshouldputdataonthebus
There is one other controlsignal
control signal thatisinvolved
that is involved
with thememoryandI/Ointerface.Thisisthe READY
signal

Control Signals
ControlSignals
READY
READYsignalis
signal is used toinsertwaitstatesinto
to insert wait states into
the buscyclesuchthatitis extendedbya
number of clock periods This signal
numberofclockperiods.Thissignal
is providedbyanexternalclockgenerator
device and can be supplied by the memory or
deviceandcanbesuppliedbythememoryor
I/Osubsystemtosignalthe8086whenthey
are ready to permitthedatatransferto
arereadyto
permit the data transfer to be
be
completed

Interrupt signals
Interruptsignals
Thekeyinterruptinterfacesignalsareinterrupt
y
p
g
p
request(INTR)andinterruptacknowledge
(INTA_bar)
INTR is an inputtothe
input to the 8086 that canbeusedby
can be used by
anexternaldevicetosignalthatitneedtobe
serviced
Logic1atINTRrepresentsanactiveinterrupt
request.Whenaninterruptrequesthas been
recognized by the8086 it indicates this fact to
recognizedbythe8086,itindicatesthisfactto
externalcircuitwithpulsetologic0atthe
INTA_bar output

Interrupt signals
Interruptsignals
The
TheTEST_bar
TEST bar inputisalsorelatedtotheexternal
input is also related to the external
interruptinterface.Executionofa
WAIT instructioncausesthe8086tocheckthe
logiclevelattheTEST_bar input
Ifthe
If the logic1isfound,the
logic 1 is found, the MPUsuspend
MPU suspend
operation andgoesintotheidlestate.The8086
no longerexecutesinstructions,insteadit
g
repeatedlychecksthelogiclevelof theTEST_bar
inputwaitingforits transitionbacktologic0

Interrupt signals
Interruptsignals
AsTEST_bar switchesto0,executionresumewiththe
nextinstructionintheprogram.Thisfeaturecanbe
usedtosynchronizetheoperationofthe8086toan
eventinexternalhardware
Therearetwomoreinputsintheinterruptinterface:
thenonmaskable interruptNMIandtheresetinterrupt
RESET
Onthe 0to1 transition ofNMIcontrolispassedto a
nonmaskable interruptserviceroutine.TheRESET
input is used to provide a hardware reset for the 8086
inputisusedtoprovideahardwareresetforthe8086.
SwitchingRESETtologic0initializesthe internal
registerofthe8086andinitiatesaresetserviceroutine

DMA Interface signals

DMAInterfacesignals
ThedirectmemoryaccessDMAinterfaceofthe8086
y
minimummodeconsistoftheHOLDandHLDAsignals
When an external device wantsto take controlofthe
systembus,itsignalstothe8086byswitchingHOLDto
t
b it i l t th 8086 b
it hi HOLD t
thelogic1level.At thecompletionofthecurrentbus
cycle,the8086enterstheholdstate.In
y
theholdstate,
signallinesAD0throughAD15,A16/S3throughA19/S6
,BHE_bar,M/IO_bar,DT/R_bar,RD_bar,WR_bar,
DEN bar andINTRareallin
DEN_bar
and INTR are all in thehighZstate.The8086
the high Z state The 8086
signalsexternaldevicethatitis inthisstateby
switchingits HLDAoutputtologic1level

MINIMUM MODE OPERATION

MINIMUMMODEOPERATION

Minimum Mode 8086 System

MinimumMode8086System
Ina minimummode 8086 system,the
y
,
microprocessor8086isoperatedinminimummodeby
strappingitsMN/MX_bar pintologic1
Inthismode,allthecontrolsignalsaregivenoutbythe
I thi
d ll th
t l i l
i
t b th
microprocessorchipitself.Thereisasingle
microprocessorintheminimummodesystem
p
y
Theremainingcomponentsinthesystemarelatches,
transreceivers,clockgenerator,memoryandI/O
devices Some type of chip selection logic may be
devices.Sometypeofchipselectionlogicmaybe
requiredforselectingmemoryorI/O devices,
dependingupontheaddressmapofthesystem

Minimum Mode 8086 System

MinimumMode8086System
Latchesare ggenerallyy buffered output
p Dtypeflip
yp p
flops like74LS373or8282.Theyareusedforseparating
thevalidaddressfromthemultiplexedaddress/data
signals and arecontrolledbytheALEsignalgenerated
signalsand
are controlled by the ALE signal generated
by8086
Transreceivers are the bidirectional buffersand some
timestheyarecalledasdataamplifiers.Theyare
requiredtoseparatethevaliddatafrom thetime
multiplexed address/data signals
multiplexedaddress/datasignals
They arecontrolledbytwo signalsnamely, DEN_bar
andDT/R_bar

Minimum Mode 8086 System

MinimumMode8086System
The DEN_bar signal
g indicates the direction of dat
a, i.e.from ortotheprocessor.Thesystem
containsmemoryforthemonitorandusers
program storage
programstorage
Usually,EPROM areusedformonitorstorage,
whileRAMforusersprogramstorage.Asystem
may containI/Odevices
The clock generator generates the clock fromthe
crystal oscillator and then shapes it and divides to
crystaloscillatorandthenshapesitanddividesto
makeitmoreprecisesothatitcanbeusedas an
accuratetimingreferenceforthesystem

ReadCycleTimingDiagram
f MinimumMode
for
d

Hold Response sequence

HoldResponsesequence
TheHOLDpinischeckedatleadingedgeofeachclock
p
g g
pulse.Ifitis receivedactivebytheprocessorbeforeT4
ofthepreviouscycleorduringT1stateofthecurrent
cycle the CPU activates HLDA inthenextclockcycle
cycle,theCPUactivatesHLDA
in the next clock cycle
andforsucceedingbuscycles,thebuswillbegivento
anotherrequestingmaster
Thecontrolof thebusisnotregainedby theprocessor
untiltherequestingmasterdoesnotdropthe
HOLD pinlow.Whentherequestisdroppedbythe
pin low When the request is dropped by the
requestingmaster,theHLDAisdroppedbythe
processorat thetrailingedgeofthenextclock

BusRequestandBusGrantTimings
in MinimumModeSystem
d